DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Republic of Korea on 02/24/2025. It is noted, however, that applicant has not filed a certified copy of the KR10-2025-0023432 application as required by 37 CFR 1.55.
Information Disclosure Statement
The references cited in the IDS have been considered by examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: DISPLAY DEVICE AND ELECTRONIC APPARATUS HAVING A PLURALITY OF PIXELS BETWEEN VOLTAGE LINES.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 6 and 18-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xu et al (U.S. Patent Pub. No. 2022/0254857; already of record in IDS).
Regarding claim 1, Xu discloses a display device, (fig. 1, [0078]), comprising:
a display panel (AA) comprising a plurality of pixels (pixel driving circuit of fig. 7), each of the plurality of pixels comprising a light emitting element (OLED) and a pixel circuit (T1-T3 and Cst) connected to the light emitting element (OLED), a plurality of data lines (Data1-Data3) connected to the plurality of pixels (pixel A and pixel B, reproduced below), and a plurality of voltage lines (VDD) connected to the plurality of pixels, (figs. 1, 7, [0078 and 0153-0154]);
a data driver (20) connected to the plurality of data lines (Data1-Data3), (fig. 1, [0110]); and
a voltage generator (power supply wiring 301) providing a plurality of voltages (VDD) to the plurality of voltage lines (VDD), wherein the plurality of pixels (pixel A and pixel B) comprises a first pixel (pixel A) and a second pixel (pixel B), each of the first pixel and the second pixel comprising a first sub-pixel (100C), a second sub-pixel (100B), and a third sub-pixel (100A), sequentially arranged in a first direction (horizontal direction), (figs. 1 and fig. 4 reproduced below, [0078-0079 and 0123]),
the plurality of data lines (Data1-Data3) comprises a first data line (Data3) connected to the first sub-pixel (100C), a second data line (Data2) connected to the second sub-pixel (100B), and a third data line (Data1) connected to the third sub-pixel (100A), (fig. 4, [0144]),
the first data line (Data3), the second data line (Data2), and the third data line (Data1) are disposed between the first sub-pixel (100C) and the third sub-pixel (100A) in a plan view, (fig. 4, [0144-0145]), and
the plurality of voltage lines (VDD) is spaced apart from the first data line (Data3), the second data line (Data2), and the third data line (Data1) with the first sub-pixel (100C) or the third sub-pixel (100A) interposed therebetween in the plan view (i.e. the left voltage line VDD and the right voltage line VDD are spaced apart from data lines Data1-Data3 with the subpixels 100A and 100C interposed therebetween), (fig. 4, [0144-0145]).
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Regarding claim 2, Xu discloses wherein:
the first data line (Data3) is disposed between the first sub-pixel (100C) and the second sub-pixel (100B) in the plan view; and
the second data line (Data2) and the third data line (Data1) are disposed between the second sub-pixel (100B) and the third sub-pixel (100A) in the plan view, (fig. 4, [0144-0145]).
Regarding claim 3, Xu discloses wherein the third sub-pixel (100A) is symmetrically arranged with respect to the second sub-pixel (100B) based on the second data line (Data2) and the third data line (Data1), (fig. 4, [0148]).
Regarding claim 6, Xu discloses wherein the plurality of data lines (Data1-Data3) and the plurality of voltage lines (VDD) are disposed on a same layer as each other (i.e. disposed on the same driving structure layer), (fig. 1, [0078]).
Regarding claim 18, Xu discloses everything as specified above in claim 1. In addition, Xu discloses an electronic device (i.e. device of fig. 1) comprising: a display device, (fig. 1, [0104]); and
a processor (peripheral circuit board) controlling operation of the display device (i.e. the peripheral circuit board is electrically connected to the bonding pad, the second power supply wiring, and the source driving chip through the flexible signal line respectively, and is configured to supply power to the first power wiring through the bonding pad, and supply power to the second power supply wiring, and provide a signal to the source driving chip), (fig. 1, [0018]).
Regarding claim 19, please refer to claims 2 and 3 for details.
Regarding claim 20, please refer to claim 6 for details.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xu in view of Yang et al (U.S. Patent Pub. No. 2021/0233455).
Regarding claim 4, Xu discloses everything as specified above in claim 1. However, Xu does not mention wherein the first and second data lines are disposed between the first sub-pixel and the second sub-pixel in the plan view.
In a similar field of endeavor, Yang teaches
wherein the first and second data lines (RDL1 and LDL2, respectively) are disposed between the first sub-pixel (R1) and the second sub-pixel (G1) in the plan view; and
the third data line (LDL3) is disposed between the second sub-pixel (G1) and the third sub-pixel (B1) in the plan view, (fig. 2, [0083]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Xu, by specifically providing the first and second data lines are disposed between the first sub-pixel and the second sub-pixel in the plan view, as taught by Yang, for the purpose of preventing a coupling between data lines, [0005].
Regarding claim 5, Yang discloses wherein the first sub-pixel (R1) is symmetrically arranged with respect to the second sub-pixel (G1) based on the first data line (RDL1) and the second data line (LDL2), (fig. 2, [0083]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Xu, by specifically providing first sub-pixel is symmetrically arranged with respect to the second sub-pixel, as taught by Yang, for the purpose of preventing a coupling between data lines, [0005].
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xu in view of Shin et al (U.S. Patent Pub. No. 2024/0423039).
Regarding claim 7, Xu discloses wherein:
the display panel further comprises a plurality of horizontal voltage lines (VL), (fig. 4, [0119]);
the plurality of voltage lines (VDD) is respectively connected to the plurality of horizontal voltage lines (VL), (fig. 4, [0119]).
However, Xu does not mention a light shielding pattern.
In a similar field of endeavor, Shin teaches
the display panel (fig. 1 shows display are of a light emitting display device) further comprises a plurality of horizontal voltage lines (174) and a light shielding pattern (BML), (fig. 1, [0087]);
the plurality of horizontal voltage lines (174) and the light shielding pattern (BML) are disposed on a same layer as each other (i.e. the lower shielding layer BML and an auxiliary low driving voltage line (refer to 174 of FIG. 1), which applies a low driving voltage ELVSS, may be disposed on the same layer), (fig. 1, [0087]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Xu, by specifically providing the light shielding pattern, as taught by Shin, for the purpose of having a light emitting display device capable of preventing a color appearance phenomenon, [0005].
Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xu in view of Min et al (U.S. Patent Pub. No. 2024/0324348).
Regarding claim 8, Xu discloses everything as specified above in claim 1. However, Xu does not mention an insulating pattern.
In a similar field of endeavor, Min teaches wherein the display panel (DA) further comprises:
an insulating pattern (113) partially covering a semiconductor pattern (D2, A2 and S2), and disposed under a gate (G2), (fig. 7, [0159 and 0174]); and
a first insulating layer (114) that covers the semiconductor pattern (D2, A2 and S2) and the gate (G2), (fig. 7, [0178]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Xu, by specifically providing the insulating pattern, as taught by Min, for the purpose of improving dead space, [0008].
Regarding claim 9, Min discloses wherein the plurality of data lines (DL) and the plurality of voltage lines (PL) are disposed on the first insulating layer (114), (fig. 8, [0178 and 0184]).
Claim(s) 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xu in view of Mok et al (U.S. Patent Pub. No. 2024/0224642).
Regarding claim 10, Xu discloses everything as specified above in claim 1. However, Xu does not mention the plurality of voltage lines comprises a first driving voltage line, a second driving voltage line, a reference voltage line, and an initialization voltage line.
In a similar field of endeavor, Mok teaches wherein:
the plurality of voltage lines comprises a first driving voltage line (VDLb), a second driving voltage line (VSLb), a reference voltage line (VRLb), and an initialization voltage line (VILb), (fig. 5a, [0186-0187, 0191 and 0207]);
the second driving voltage line (VSLb), the initialization voltage line (VILb), and the reference voltage line (VRLb) are spaced apart from the first data line (DL1) with the first sub-pixel (PE11) interposed therebetween in the plan view, (fig. 5a, [0159 and 0207]); and
the first driving voltage line (VDLb) is spaced apart from the third data line (DL3) with the third sub-pixel (PE13) interposed therebetween in the plan view, (fig. 5a, [0159, 0165 and 0191]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Xu, by specifically providing the first driving voltage line, the second driving voltage line, the reference voltage line, and the initialization voltage line, as taught by Mok, for the purpose of improving image quality, [0006].
Regarding claim 11, Mok discloses wherein the pixel circuit (PX) comprises a plurality of transistors (T1-T4), each of the plurality of transistors comprising a semiconductor pattern (ACT1) and a gate (GE1), (figs. 3 and 15, [0144, 0242 and 0246]); and
each of the plurality of transistors comprises:
a first transistor (T1) connected between the first driving voltage line (VDL) and the light emitting element (LEL), (fig. 3, [0144-0145]);
a second transistor (T2) connected between one of the plurality of data lines (DL) and the first transistor (T1), (fig. 3, [0149]); and
a third transistor (T3) connected to the reference voltage line (VRL), (fig. 3, [0150]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Xu, by specifically providing the plurality of transistors, as taught by Mok, for the purpose of improving image quality, [0006].
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xu in view of Mok and in view of Shin.
Regarding claim 12, Shin discloses wherein the semiconductor pattern (ACT) of the first transistor (driving transistor) is connected to a light shielding pattern (BML) overlapping the semiconductor pattern of the first transistor, (fig. 3, [0087-0088]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Xu in view of Mok, by specifically providing the light shielding pattern, as taught by Shin, for the purpose of having a light emitting display device capable of preventing a color appearance phenomenon, [0005].
Allowable Subject Matter
Claims 13-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reasons for Allowance
Claim 13, none of the prior art of record teaches alone or in combination the limitation “wherein the pixel circuit further comprises: a first capacitor formed by the light shielding pattern and the gate of the first transistor; and a second capacitor formed by the light shielding pattern and a capacitor electrode, and the capacitor electrode is disposed on a same layer as the semiconductor pattern of the first transistor.”
Claims 14-17 are dependent upon claim 13 and are allowed for the reason mentioned above in claim 13.
Inquiries
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/LONG D PHAM/
Primary Examiner, Art Unit 2623
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