DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The references cited in the IDS have been considered by examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: PIXEL CIRCUIT HAVING A PLURALITY OF DRIVING TRANSISTORS DRIVEN BASED ON DISPLAY MODES, DISPLAY DEVICE AND ELECRONIC DEVICE THEREOF.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4, 9-10 and 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al (U.S. Patent Pub. No. 2023/0230545).
Regarding claim 1, Kim discloses a pixel circuit (PX), (fig. 2, [0073]), comprising:
a light-emitting element (OLED) connected between a first power line (ELVDD) and a second power line (ELVSS), (fig. 2, [0052 and 0059]);
a first driving transistor (T11) connected between the first power line (ELVDD) and the light-emitting element (OLED), and comprising a source terminal and a drain terminal, (fig. 2, [0076-0077]); and
a second driving transistor (T12) connected between the first power line (ELVDD) and the light-emitting element (OLED), and comprising a source terminal connected to the source terminal of the first driving transistor (T11), and a drain terminal connected to the drain terminal of the first driving transistor, (fig. 2, [0076-0077]),
wherein, based on a display mode (i.e. based on high brightness or low brightness mode), either only the first driving transistor is driven (i.e. the first driving transistor T11 is driven during the high brightness mode), (fig. 3, [0094-0097]).
Regarding claim 2, Kim discloses further comprising a switching circuit (T9) configured to either turn off the second driving transistor (i.e. when transistor T9 is off, the driving transistor T12 is turn off), based on the display mode (high brightness mode), (figs. 2-3, [0095]).
Regarding claim 4, Kim discloses wherein the drain terminal of the first driving transistor (T11) and the drain terminal of the second driving transistor (T12) are connected to an anode of the light-emitting element (OLED) through transistor T6, (fig. 2, [0076]).
Regarding claim 9, Kim discloses a pixel circuit (PX), (fig. 6, [0106]), comprising:
a light-emitting element (OLED) connected between a first power line (ELVDD) and a second power line (ELVSS), (fig. 6, [0074, 0086 and 0119]);
a first driving transistor (T11) connected between the first power line (ELVDD) and the light-emitting element (OLED), and comprising a source terminal, (fig. 6, [0109]); and
a second driving transistor (T12) connected between the first power line (ELVDD) and the light-emitting element (OLED), and comprising a drain terminal connected to the source terminal of the first driving transistor (T11), (fig. 6, [0109]),
wherein, based on a display mode (i.e. high brightness mode), both the first driving transistor (T11) and the second driving transistor (T12) are driven together, (figs. 6-7, [0125]).
Regarding claim 10, Kim discloses further comprising a switching circuit (T8 and T9) configured to either connect a gate terminal of the first driving transistor (T11) to a gate terminal of the second driving transistor (T12) or turn on the second driving transistor (T12), based on the display mode (i.e. high brightness mode), (figs. 6-7, [0125]).
Regarding claim 12, Kim discloses wherein the drain terminal of the second driving transistor (T12) is connected to an anode of the light-emitting element (OLED) through transistor T6, (fig. 6, [0109]) .
Claim(s) 17 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chae (U.S. Patent Pub. No. 2023/0402007).
Regarding claim 17, Chae discloses an electronic device (2000), (fig. 18, [0151]), comprising:
a memory (2020), (fig. 18, [0154]);
a processor (2010) configured to execute an application stored in the memory, (fig. 18, [0153-0154]); and
a display module (1000) configured to process a signal transmitted from the processor (2010), and to output image information, the display module (1000) comprising pixel circuits (P), (figs. 1 and 18, [0158]), the pixel circuits (P) comprising:
a light-emitting element (EE) connected between a first power line (ELVDD) and a second power line (ELVSS), (fig. 5, [0069]); and
a driving transistor (T1-1) connected between the first power line (ELVDD) and the light-emitting element (EE), comprising a first gate terminal (gate) and a second gate terminal (back gate), and configured to be controlled to have a source-sync structure or a gate-sync structure (i.e. the gate and the back gate are connected) based on a display mode, (fig. 5, [0076 and 0100]).
Regarding claim 20, Chae discloses wherein the pixel circuit further comprises:
a substrate (SUB), (fig. 3c, [0081]);
an active pattern (ACT) above the substrate, and extending in a first direction on a plane, (fig. 3c, [0081]);
a buffer layer (BUFFER) between the substrate (SUB) and the active pattern (ACT), (fig. 3c, [0081]);
an upper gate pattern (GAT1) above the active pattern (ACT), (fig. 3c, [0081]); and
a lower gate pattern (BML1) between the substrate (SUB) and the buffer layer (BUFFER), (fig. 3c, [0081]), and
wherein the driving transistor (T1-1) comprises the active pattern (ACT), a portion of the upper gate pattern (GAT1) overlapping the active pattern (ACT), and a portion of the lower gate pattern (BML1) overlapping the active pattern (ACT), (fig. 3c, [0081]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5-7 and 13-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Chae.
Regarding claim 5, Kim discloses further comprising:
a storage capacitor (Cst) having a first terminal connected to a gate terminal of the first driving transistor (T11), and a second terminal connected to the first power line (ELVDD), (fig. 2, [0085]); and
a scan transistor (T2), (fig. 2, [0078]).
However, Kim does not mention a scan transistor connected between a data line and the gate terminal of the first driving transistor.
In a similar field of endeavor, Chae teaches a scan transistor (T2) connected between a data line (VDATA) and the gate terminal of the first driving transistor (T1-1), and configured to be turned on in response to a scan signal (GW), (fig. 3a, [0069]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Kim, by specifically providing the scan transistor connected between the data line and the gate terminal of the first driving transistor, as taught by Chae, for the purpose of increasing a driving range of a driving transistor, [0005].
Regarding claim 6, Kim discloses everything as specified above in claim 1. However, Kim does not mention a substrate.
In a similar field of endeavor, Chae teaches further comprising:
a substrate (SUB), (fig. 3c, [0081]);
a first active pattern (i.e. left side active layer ACT) above the substrate (SUB), and extending in a first direction on a plane, (fig. 3c, [0081]);
a second active pattern (i.e. right side active layer ACT) above the substrate (SUB), and extending in the first direction on the plane, (fig. 3c, [0081]); and
an upper gate pattern (GAT1),
wherein the first driving transistor (T1-1) comprises the first active pattern (i.e. left ACT), and a first portion of the upper gate pattern (GAT1) overlapping the first active pattern (ACT), and
wherein the second driving transistor (T1-2) comprises the second active pattern (i.e. right ACT), and a second portion of the upper gate pattern (GAT2) overlapping the second active pattern (ACT), (fig. 3c, [0081]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Kim, by specifically providing the substrate and active layers, as taught by Chae, for the purpose of providing a structure for the transistors.
Regarding claim 7, Kim discloses wherein a length of the first active pattern in the first direction is different from a length of the second active pattern in the first direction (i.e. the channel length of the second driving transistor T12 may be greater than the channel length of the first driving transistor T11), (fig. 2, [0073]).
Regarding claim 13, please refer to claim 5 for details.
Regarding claim 14, please refer to claim 6 for details.
Regarding claim 15, please refer to claim 7 for details.
Claim(s) 8 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Chae and in view of Chen (U.S. Patent No. 10,593,271).
Regarding claim 8, Kim in view of Chae discloses everything as specified above in claim 6. However, Kim in view of Chae does not mention wherein a width of the first active pattern in a second direction crossing the first direction is different from a width of the second active pattern in the second direction.
In a similar field of endeavor, Chen teaches wherein a width of the first active pattern (W1) in a second direction crossing the first direction is different from a width of the second active pattern (W2) in the second direction, (figs. 5a-5b, col. 5, lines 34-67).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Kim in view of Chae, by specifically providing different widths of the active pattern, as taught by Chen, for the purpose of enabling a high dynamic range display, (col. 1, lines 8-10).
Regarding claim 16, please refer to claim 8 for details.
Allowable Subject Matter
Claims 3, 11 and 18-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reasons for Allowance
Claim 3, none of the prior art of record teaches alone or in combination the limitation “wherein the switching circuit comprises: a first switching transistor connected between the gate terminal of the first driving transistor and the gate terminal of the second driving transistor; and a second switching transistor connected between an off-voltage line and the gate terminal of the second driving transistor.”
Claim 11 is allowed for similar reasons as mentioned above in claim 3.
Claim 18, none of the prior art of record teaches alone or in combination the limitation “wherein the pixel circuit further comprises a switching circuit configured to control the second gate terminal of the driving transistor to be connected to the first gate terminal of the driving transistor, or to control the second gate terminal of the driving transistor to be connected to a source terminal of the driving transistor, based on the display mode.”
Claim 19 is dependent upon claim 18 and is allowed for the reasons mentioned above in claim 18.
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/LONG D PHAM/ Primary Examiner, Art Unit 2623
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