DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of Species I [figs. 2-3, corresponding to claims 1, 4-7, 9, 12-15, 17, & 20] in the reply filed on 8/11/2026 is acknowledged.
Claims 2-3, 8, 10-11, 16, & 18-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 8/11/2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/5/2025 is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 5-7, 9, 13-15, & 17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang (US 20230267882).
As to claim 1, Yang discloses a pixel circuit [abstract & fig. 4] comprising:
a first transistor (first transistor t1) [fig. 4 & para. 86] comprising a control electrode connected to a first node (second node n2) [fig. 4], a first electrode connected to a second node (node shared with eighth transistor t8) [fig. 4], and a second electrode connected to a third node (node shared with third transistor t3) [fig. 4];
a second transistor (second transistor t2) [fig. 4 & para. 86] comprising a control electrode configured to receive a writing gate signal (data write line GWLi) [fig. 4], a first electrode configured to receive a data voltage (data voltage vdata) [fig. 4], and a second electrode connected to a fourth node (first node n1) [fig.4];
a third transistor (third transistor t3) [fig. 4] comprising a control electrode configured to receive a compensation gate signal (compensation scan signal GCi) [fig. 4], a first electrode connected to the first node (second node n2) [fig. 4], and a second electrode connected to the third node (node shared with first transistor t1) [fig. 4];
a fourth transistor (eight transistor t8) [fig. 4] comprising a control electrode configured to receive a first emission signal (first emission signal Em1i) [fig. 4], a first electrode configured to receive a first driving voltage (first driving voltage elvdd) [fig 4], and a second electrode connected to the second node (node shared with first transistor t1) [fig 4];
a fifth transistor (fifth transistor t5) [fig. 4] comprising a control electrode configured to receive the compensation gate signal (compensation scan signal GCi) [fig. 4], a first electrode connected to the fourth node (first node n1) [fig. 4], and a second electrode configured to receive a reference voltage (reference voltage vref) [fig. 4];
a sixth transistor (fourth transistor t4) [fig. 4] comprising a control electrode configured to receive a first initialization gate signal (initialization scan signal GIi) [fig. 4], a first electrode connected to the first node (second node n2) [fig. 4], and a second electrode configured to receive a first initialization voltage (first initialization voltage Vint) [fig. 4];
a seventh transistor (tenth transistor t10) [fig .4] comprising a control electrode configured to receive a second initialization gate signal (initialization scan signal GIi) [fig. 4], a first electrode configured to receive a second initialization voltage (first driving voltage elvdd) [figs. 4, 7, & 8a], and a second electrode connected to the fourth node (first node n1) [fig. 4];
a first capacitor (second capacitor cst2) [fig. 4] comprising a first electrode connected to the fourth node (first node n1) [fig. 4] and a second electrode connected to the first node (second node n2) [fig. 4];
a second capacitor (first capacitor cst1) [fig. 4] comprising a first electrode configured to receive the first driving voltage (first driving voltage elvdd) [fig. 4] and a second electrode connected to the fourth node (first node n1) [fig. 4]; and
a light emitting element (light emitting diode OLED) [fig. 4] comprising an anode and a cathode configured to receive a second driving voltage (second driving voltage ELVSS) [fig. 4].
As to claim 5, Yang discloses the pixel circuit of claim 1, wherein the pixel circuit further comprises an eighth transistor (sixth transistor t6) [fig. 4] comprising a control electrode configured to receive a second emission signal (second emission signal em2i) [fig. 4], a first electrode connected to the third node (node shared with first transistor t1) [fig. 4], and a second electrode connected to the anode of the light emitting element (node shared with light emitting diode OLED) [fig. 4].
As to claim 6, Yang discloses the pixel circuit of claim 1, wherein the pixel circuit further comprises a ninth transistor (seventh transistor t7) [fig. 4] comprising a control electrode configured to receive a bias gate signal (initialization signal Ebi) [fig. 4], a first electrode configured to receive an anode initialization voltage (second initialization voltage Vaint) [fig. 4 & para. 98], and a second electrode connected to the anode of the light emitting element (light emitting diode OLED) [fig. 4].
As to claim 7, Yang discloses the pixel circuit of claim 1, wherein the pixel circuit further comprises a tenth transistor (ninth transistor t9) [fig. 4] comprising a control electrode configured to receive a bias gate signal (initialization signal Ebi) [fig. 4], a first electrode connected to the second node (node shared with first transistor t1) [fig. 4], and a second electrode configured to receive a bias voltage (bias voltage vbias) [fig. 4 & para. 100].
As to claim 9, Yang discloses a display device [abstract & fig. 3] comprising:
a display panel (display layer 100) [figs. 1 & 3] comprising a pixel circuit (pixels px11 to pxnm) [figs. 3-4]; and
a display panel driver (data driving circuit ddc & scan driving circuit scd) [fig. 3] configured to drive the display panel,
wherein the pixel circuit [fig.4] comprises:
a first transistor (first transistor t1) [fig. 4 & para. 86] comprising a control electrode connected to a first node (second node n2) [fig. 4], a first electrode connected to a second node (node shared with eighth transistor t8) [fig. 4], and a second electrode connected to a third node (node shared with third transistor t3) [fig. 4];
a second transistor (second transistor t2) [fig. 4 & para. 86] comprising a control electrode configured to receive a writing gate signal (data write line GWLi) [fig. 4], a first electrode configured to receive a data voltage (data voltage vdata) [fig. 4], and a second electrode connected to a fourth node (first node n1) [fig.4];
a third transistor (third transistor t3) [fig. 4] comprising a control electrode configured to receive a compensation gate signal (compensation scan signal GCi) [fig. 4], a first electrode connected to the first node (second node n2) [fig. 4], and a second electrode connected to the third node (node shared with first transistor t1) [fig. 4];
a fourth transistor (eight transistor t8) [fig. 4] comprising a control electrode configured to receive a first emission signal (first emission signal Em1i) [fig. 4], a first electrode configured to receive a first driving voltage (first driving voltage elvdd) [fig 4], and a second electrode connected to the second node (node shared with first transistor t1) [fig 4];
a fifth transistor (fifth transistor t5) [fig. 4] comprising a control electrode configured to receive the compensation gate signal (compensation scan signal GCi) [fig. 4], a first electrode connected to the fourth node (first node n1) [fig. 4], and a second electrode configured to receive a reference voltage (reference voltage vref) [fig. 4];
a sixth transistor (fourth transistor t4) [fig. 4] comprising a control electrode configured to receive a first initialization gate signal (initialization scan signal GIi) [fig. 4], a first electrode connected to the first node (second node n2) [fig. 4], and a second electrode configured to receive a first initialization voltage (first initialization voltage Vint) [fig. 4];
a seventh transistor (tenth transistor t10) [fig .4] comprising a control electrode configured to receive a second initialization gate signal (initialization scan signal GIi) [fig. 4], a first electrode configured to receive a second initialization voltage (first driving voltage elvdd) [figs. 4, 7, & 8a], and a second electrode connected to the fourth node (first node n1) [fig. 4];
a first capacitor (second capacitor cst2) [fig. 4] comprising a first electrode connected to the fourth node (first node n1) [fig. 4] and a second electrode connected to the first node (second node n2) [fig. 4];
a second capacitor (first capacitor cst1) [fig. 4] comprising a first electrode configured to receive the first driving voltage (first driving voltage elvdd) [fig. 4] and a second electrode connected to the fourth node (first node n1) [fig. 4]; and
a light emitting element (light emitting diode OLED) [fig. 4] comprising an anode and a cathode configured to receive a second driving voltage (second driving voltage ELVSS) [fig. 4].
As to claim 13, Yang discloses the display device of claim 9, wherein the pixel circuit further comprises an eighth transistor (sixth transistor t6) [fig. 4] comprising a control electrode configured to receive a second emission signal (second emission signal em2i) [fig. 4], a first electrode connected to the third node (node shared with first transistor t1) [fig. 4], and a second electrode connected to the anode of the light emitting element (node shared with light emitting diode OLED) [fig. 4].
As to claim 14, Yang discloses the display device of claim 9, wherein the pixel circuit further comprises a ninth transistor (seventh transistor t7) [fig. 4] comprising a control electrode configured to receive a bias gate signal (initialization signal Ebi) [fig. 4], a first electrode configured to receive an anode initialization voltage (second initialization voltage Vaint) [fig. 4 & para. 98], and a second electrode connected to the anode of the light emitting element (light emitting diode OLED) [fig. 4].
As to claim 15, Yang discloses the display device of claim 9, wherein the pixel circuit further comprises a tenth transistor (ninth transistor t9) [fig. 4] comprising a control electrode configured to receive a bias gate signal (initialization signal Ebi) [fig. 4], a first electrode connected to the second node (node shared with first transistor t1) [fig. 4], and a second electrode configured to receive a bias voltage (bias voltage vbias) [fig. 4 & para. 100].
As to claim 17, Yang discloses an electronic device [fig. 1] comprising:
a processor (timing controller tc) [fig. 3 & para. 69-71] configured to generate an input control signal (data control signal dcs & scan control signal scs) [fig. 3 & para. 70] and input image data (image datad-rgb) [fig. 3 & para. 70];
a display panel (display layer 100) [figs. 1 & 3] comprising a pixel circuit (pixels px11 to pxnm) [figs. 3-4]; and
a display panel driver (data driving circuit ddc & scan driving circuit scd) [fig. 3] configured to drive the display panel based on the input control signal and the input image data [fig. 3 & para. 70-71 & 73],
wherein the pixel circuit [fig.4] comprises:
a first transistor (first transistor t1) [fig. 4 & para. 86] comprising a control electrode connected to a first node (second node n2) [fig. 4], a first electrode connected to a second node (node shared with eighth transistor t8) [fig. 4], and a second electrode connected to a third node (node shared with third transistor t3) [fig. 4];
a second transistor (second transistor t2) [fig. 4 & para. 86] comprising a control electrode configured to receive a writing gate signal (data write line GWLi) [fig. 4], a first electrode configured to receive a data voltage (data voltage vdata) [fig. 4], and a second electrode connected to a fourth node (first node n1) [fig.4];
a third transistor (third transistor t3) [fig. 4] comprising a control electrode configured to receive a compensation gate signal (compensation scan signal GCi) [fig. 4], a first electrode connected to the first node (second node n2) [fig. 4], and a second electrode connected to the third node (node shared with first transistor t1) [fig. 4];
a fourth transistor (eight transistor t8) [fig. 4] comprising a control electrode configured to receive a first emission signal (first emission signal Em1i) [fig. 4], a first electrode configured to receive a first driving voltage (first driving voltage elvdd) [fig 4], and a second electrode connected to the second node (node shared with first transistor t1) [fig 4];
a fifth transistor (fifth transistor t5) [fig. 4] comprising a control electrode configured to receive the compensation gate signal (compensation scan signal GCi) [fig. 4], a first electrode connected to the fourth node (first node n1) [fig. 4], and a second electrode configured to receive a reference voltage (reference voltage vref) [fig. 4];
a sixth transistor (fourth transistor t4) [fig. 4] comprising a control electrode configured to receive a first initialization gate signal (initialization scan signal GIi) [fig. 4], a first electrode connected to the first node (second node n2) [fig. 4], and a second electrode configured to receive a first initialization voltage (first initialization voltage Vint) [fig. 4];
a seventh transistor (tenth transistor t10) [fig .4] comprising a control electrode configured to receive a second initialization gate signal (initialization scan signal GIi) [fig. 4], a first electrode configured to receive a second initialization voltage (first driving voltage elvdd) [figs. 4, 7, & 8a], and a second electrode connected to the fourth node (first node n1) [fig. 4];
a first capacitor (second capacitor cst2) [fig. 4] comprising a first electrode connected to the fourth node (first node n1) [fig. 4] and a second electrode connected to the first node (second node n2) [fig. 4];
a second capacitor (first capacitor cst1) [fig. 4] comprising a first electrode configured to receive the first driving voltage (first driving voltage elvdd) [fig. 4] and a second electrode connected to the fourth node (first node n1) [fig. 4]; and
a light emitting element (light emitting diode OLED) [fig. 4] comprising an anode and a cathode configured to receive a second driving voltage (second driving voltage ELVSS) [fig. 4].
Allowable Subject Matter
Claims 4, 12, & 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Sun et al. (US 20250124862).
Toyomura (US 20210233468).
Xuan et al. (US 20210005143).
Kim et al. (US 20210142733).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID TUNG whose telephone number is (571)270-3385. The examiner can normally be reached Monday-Friday; 10:00AM - 6:00PM.
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/DAVID TUNG/Primary Examiner, Art Unit 2622
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