CTNF 19/411,732 CTNF 84118 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Priority 02-26 AIA Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Specification 06-11 AIA The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-2, 4, 7, 11, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Iwase et al (US 2010/0199354 A1) in view of Park et al (US 2006/0227094 A1) . Claim 1 , Iwase (Fig. 1-16) discloses a scanning signal line drive circuit (401; Fig. 2) configured to supply scanning signals (Fig. 6) to multiple scanning signal lines (GL1-GLi-1; Fig. 2) included in a display device (Fig. 2), the scanning signal line drive circuit (401; Fig. 3) comprising: a shift register circuit (410; Fig. 3) including multiple stages (41(1) 41(i/2); Fig. 3), wherein each of the multiple stages (41(1) 41(i/2); Fig. 3 and 4) includes a first clock terminal (CLKA; Fig. 4; 45; Fig. 1) configured to receive a first clock signal (GCK1; Fig. 4), a set terminal (S; Fig. 4; 43; Fig. 1) configured to receive a set signal (GSP1; Fig. 4), a reset terminal (R; Fig. 4; 44; Fig. 1) configured to receive a reset signal (Q from (41(2); Fig. 4), a first output terminal (Q; Fig. 4; 49; Fig. 1) configured to output a scanning signal (Fig. 6), a 1st transistor including (T1; Fig. 1) a gate (GATE; Fig. 1) electrically connected to a first internal node (netA; Fig. 1), and a source (source; Fig. 1) and a drain (drain; Fig. 1), one of the source (source; Fig. 1) and the drain electrically connected to the clock terminal (CKA and 45; Fig. 1) and another of the source and the drain (drain; Fig. 1) electrically connected to the first output terminal (Q and 49; Fig. 1), a 2nd transistor (T5; Fig. 1) including a gate electrically connected to the set terminal (S and 43; Fig. 1), and a source and a drain (Fig. 1; wherein figure shows transistor T5 with two electrodes), one of the source and the drain (Paragraph [0218]) electrically connected to the first internal node (netA; Fig. 1), a 3rd transistor (T7; Fig. 1) including a gate electrically connected to the reset terminal (R and 44; Fig. 1), and a source and a drain (Fig. 1; wherein figure shows transistor T7 with two electrodes), one of the source and the drain (Paragraph [0218]) electrically connected to the first internal node (netA; Fig. 1) and another of the source and the drain (T7; Fig. 1) electrically connected to a first reference voltage source (Vss; Fig. 1), a stabilization circuit (Paragraph [0217]; wherein discloses a bistable circuit; T3, T6, T2, and T10; Fig. 1) electrically connected to the first internal node (netA; Fig. 1) and the first output terminal (Q and 49; Fig. 1), and configured to suppress fluctuations in potentials of the first internal node (netA; Fig. 9A-10) and the first output terminal (Q; Fig. Fig. 9A-10) during a non-select period (Paragraph [0237] and [0243]), the stabilization circuit (T3, T6, T2, and T10; Fig. 1) includes at least one of a 4th transistor (T2; Fig. 1) including a gate electrically connected to a second internal node (netB; Fig. 1), and a source and a drain (Fig. 1; wherein figure shows transistor T2 with two electrodes), one of the source and the drain (T2; Fig. 1) electrically connected to the first internal node (netA; Fig. 1), and another of the source and the drain (T2; Fig. 1) supplied with a first reference potential (Vss; Fig. 1), and a 5th transistor (T10; Fig. 1) including a gate electrically connected to the second internal node (netB; Fig. 1), and a source and a drain (Fig. 1; wherein figure shows transistor T10 with two electrodes), one of the source and the drain (T10; Fig. 1) electrically connected to the first output terminal (Q and 49; Fig. 1) and another of the source and the drain (T10; Fig. 1) configured to be supplied with a second reference potential (Vss; Fig. 1), the second reference potential (Vss; Fig. 1) being identical to (Fig. 1) or different from the first reference potential (Vss; Fig. 1). Iwase does not expressly disclose during at least part of a vertical blanking period of an effective display period and the vertical blanking period included in a vertical scanning period, a potential of the second internal node is lower than the potential of the first internal node, the potential of the first output terminal, the first reference potential, and the second reference potential. Park (Fig. 1-10) discloses during at least part of a vertical blanking period (Vertical Blank Time; Fig. 6) of an effective display period (Frame 1 and vertical blank time; Fig. 6) and the vertical blanking period (Vertical Blank Time; Fig. 6) included in a vertical scanning period (Frame 1; Fig. 6), a potential of the second internal node (QB; Fig. 8) is lower (Vneg; Fig. 8; Paragraph [0058-0059]) than the potential of the first internal node (Q; Fig. 8), the potential of the first output terminal (Gout5; Fig. 8), the first reference potential (VSS; Fig. 8), and the second reference potential (VSS; Fig. 8). Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Iwase’s scanning signal line drive circuit by applying a negative voltage during blank time, as taught by Iwase, so to use a scanning signal line drive circuit with a negative voltage during blank time for providing the cumulative stress voltage can be further reduced to minimize malfunction of the liquid crystal display and damages to the liquid crystal display (Paragraph [0059]). Claim 2 , Iwase (Fig. 1-16) discloses wherein the stabilization circuit (T3, T6, T2, and T10; Fig. 1) includes at least the 4th transistor (T2; Fig. 1) of the 4th transistor (T2; Fig. 1) and the 5th transistor (T10; Fig. 1), the other of the source and the drain of the 4th transistor (T2; Fig. 1) is electrically connected to the first reference voltage source (Vss; Fig. 1), the stabilization circuit (T3, T6, T2, and T10; Fig. 1) further includes a 6th transistor (T6; Fig. 1) including a gate electrically connected to the first internal node (netA; Fig. 1), and a source and a drain (Fig. 1; wherein figure shows transistor T10 with two electrodes), one of the source and the drain (T6; Fig. 1) electrically connected to the second internal node (netB; Fig. 1) and another of the source and the drain (T6; Fig. 1) electrically connected to a second reference voltage source (Vss; Fig. 1), and a potential of the second reference voltage source (Vss connected to T6; Fig. 1) is practically identical to a potential of the first reference voltage source (Vss connected to T2; Fig. 1) during the effective display period (Fig. 7). Park (Fig. 1-10) discloses a potential of the second reference voltage source (Vneg; Fig. 8) is lower than the potential of the first reference voltage source (Vss; Fig. 8) during the at least part of the vertical blanking period (Vertical Blank Time; Fig. 6). Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Iwase’s scanning signal line drive circuit by applying a negative voltage during blank time, as taught by Iwase, so to use a scanning signal line drive circuit with a negative voltage during blank time for providing the cumulative stress voltage can be further reduced to minimize malfunction of the liquid crystal display and damages to the liquid crystal display (Paragraph [0059]). Claim 4 , Park (Fig. 1-10) discloses wherein the stabilization circuit (M3, M4, M8, M1, M6, and M9; Fig. 8) further includes an 8th transistor (M9; Fig. 8) including a gate electrically connected to the set terminal (Gout4; Fig. 8), and a source and a drain (Fig. 8; wherein figure further shows transistor M8 has two electrodes), one of the source and the drain (M8; Fig. 9) electrically connected to the second internal node (QB; Fig. 8) and another of the source and the drain (M8; Fig. 8) electrically connected to the second reference voltage source (VSS; Fig. 8). Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Iwase’s scanning signal line drive circuit by applying a negative voltage during blank time, as taught by Iwase, so to use a scanning signal line drive circuit with a negative voltage during blank time for providing the cumulative stress voltage can be further reduced to minimize malfunction of the liquid crystal display and damages to the liquid crystal display (Paragraph [0059]). Claim 7 , Iwase (Fig. 1-16) discloses wherein each of the multiple stages (41; Fig. 3) further includes an 11th transistor (T8; Fig. 1) including a gate configured to be supplied with a signal output from another stage (R and 44; Fig. 1; Fig. 4; wherein figure shows reset terminal being connected to an output terminal another stage), and a source and a drain (Fig. 1; wherein figure shows transistor with two electrodes), one of the source and the drain (T8; Fig. 1) electrically connected to the first output terminal (Q and 49; Fig. 1) and another of the source and the drain (T8; Fig. 1) electrically connected to the first reference voltage source (VSS; Fig. 1). Claim 10 , Iwase (Fig. 1-16) discloses wherein the stabilization circuit (T3, T6, T2, and T10; Fig. 1) includes both the 4th transistor (T2; Fig. 1) and the 5th transistor (T10; Fig. 1), and the other of the source and the drain of the 4th transistor (T2; Fig. 1) and the other of the source and the drain of the 5th transistor (T10; Fig. 1) are each electrically connected to the first reference voltage source (Vss; Fig. 1), and the first reference (Vss; Fig. 1) potential is identical to the second reference potential (Vss; Fig. 1). Claim 14 , Iwase (Fig. 1-16) discloses a display device (Fig. 2) having multiple pixels arranged in a matrix (Paragraph [0201]) including multiple pixel rows and multiple pixel columns (600; Fig. 2), the display device (Fig. 2) comprising: multiple scanning signal lines (GL1-GLi; Fig. 2), each of the multiple scanning signal lines (GL1-GLi; Fig. 2) being associated with one of the multiple pixel rows (600; Fig. 2); and the scanning signal line drive circuit (401 and 402; Fig. 2) according to claim 1 (see rejection to claim 1 above) configured to supply scanning signals (Fig. 6) to the multiple scanning signal lines (GL1-GLi; Fig. 2) . 07-22-aia AIA Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Iwase et al (US 2010/0199354 A1) in view of Park et al (US 2006/0227094 A1) as applied to claim 2 above, and further in view of Jang et al (US 2005/0156856 A1) . Claim 3 , Iwase (Fig. 1-16) discloses wherein the stabilization circuit (T3, T6, T2, and T10; Fig. 1) further includes a 7th transistor (T3; Fig. 1) including a source and a drain (Fig. 1; wherein figure shows transistor T3 with two electrodes), one of the source and the drain electrically connected (T3; Fig. 1) to a first charge supply source (47 and CKC; Fig. 1) configured to supply charge (Paragraph [0222]) to the second internal node (netB; Fig. 1) and another of the source and the drain electrically connected (T3; Fig. 1) to the second internal node (netB; Fig. 1). Iwase in view of Park does not expressly disclose a potential of the first charge supply source is lower than the potential of the first reference voltage source during the at least part of the vertical blanking period. Jang (Fig. 1-11) discloses a potential of the first charge supply source (VDD1 or VDD2; Fig. 5) is lower than (-20V; Fig. 5) the potential of the first reference voltage source (VSS or -5V; Fig. 6) during the at least part of the vertical blanking period (Paragraph [0092]). Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Iwase in view of Park’s scanning signal line drive circuit by applying an alternating voltage source, as taught by Jang, so to use a scanning signal line drive circuit with an alternating voltage source for providing an active matrix display device capable of preventing degradation of a shift register to improve its life span and improve picture quality (Paragraph [0025]) . 07-22-aia AIA Claim 5-6, 8-9, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Iwase et al (US 2011/0199354 A1) in view of Park et al (US 2006/0227094 A1) as applied to claim s 1 and 2 above, and further in view of Takahashi et al (US 2019/0164516 A1) . Claim 5 , Iwase in view of Park discloses the scanning signal line drive circuit according to claim 1. Iwase in view of Park does not expressly disclose wherein each of the multiple stages further includes a second output terminal configured to output a signal configured to drive another stage at the same timing as the scanning signal is output from the first output terminal, and a 9th transistor including a gate electrically connected to the first internal node, and a source and a drain, one of the source and the drain electrically connected to the clock terminal and another of the source and the drain electrically connected to the second output terminal. Takahashi (Fig. 1-7) discloses wherein each of the multiple stages (10; Fig. 1) further includes a second output terminal (Qn; Fig. 6) configured to output a signal (Qn; Fig. 7) configured to drive another stage (10; Fig. 1) at the same timing (Fig. 7) as the scanning signal (Gout; Fi7) is output from the first output terminal (Gout; Fig. 6), and a 9th transistor (M2; Fig. 6) including a gate electrically connected to the first internal node (netA; Fig. 6), and a source and a drain (Fig. 6; wherein figure shows transistor M2 having two electrodes), one of the source and the drain (M2; Fig. 6) electrically connected to the clock terminal (CKA; Fig. 6) and another of the source and the drain (M2; Fig. 6) electrically connected to the second output terminal (Qn; Fig. 6). Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Iwase in view of Park’s scanning signal line drive circuit by applying a second output terminal, as taught by Takahashi, so to use a scanning signal line drive circuit with a second output terminal for providing a drive circuit capable of suppressing delay of a drive signal and a display apparatus including the drive circuit (Paragraph [0007]). Claim 6 , Takahashi (Fig. 1-7) discloses wherein each of the multiple stages (10; Fig. 1) further includes a 10th transistor (M11; Fig. 6) including a gate electrically connected to the second internal node (netB; Fig. 6), and a source and a drain (Fig. 6; wherein figure shows transistor M11 with two electrodes), one of the source and the drain (M11; Fig. 6) electrically connected to the second output terminal (Qn; Fig. 6) and another of the source and the drain (M11; Fig. 6) electrically connected to the first reference voltage source (Vpl; Fig. 6). Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Iwase in view of Park’s scanning signal line drive circuit by applying a second output terminal, as taught by Takahashi, so to use a scanning signal line drive circuit with a second output terminal for providing a drive circuit capable of suppressing delay of a drive signal and a display apparatus including the drive circuit (Paragraph [0007]). Claim 8 , Takahashi (Fig. 1-7) discloses wherein the stabilization circuit (Fig. 6) includes at least the 5th transistor (M10; Fig. 6) of the 4th transistor (M9; Fig. 6) and the 5th transistor (M10: Fig. 6), each of the multiple stages (10; Fig. 1) further includes a 10th transistor (M11; Fig. 6) including a gate electrically connected to the second internal node (netB; Fig. 6), and a source and a drain (Fig. 6; wherein figure shows transistor M11 having two electrodes), one of the source and the drain (M11; Fig. 6) electrically connected to the second output terminal (Qn; Fig. 6) and another of the source and the drain (M11; fig. 6) electrically connected to the first reference voltage source (Vpl; Fig. 6), the other of the source and the drain of the 5th transistor (M10; Fig. 6) is electrically connected to a third reference voltage source (Vgl; Fig. 6), and a potential of the third reference voltage source (Vgl; Fig. 6) is higher than (Paragraph [0027]) a potential of the first reference voltage source (Vpl; Fig. 6). Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Iwase in view of Park’s scanning signal line drive circuit by applying a second output terminal, as taught by Takahashi, so to use a scanning signal line drive circuit with a second output terminal for providing a drive circuit capable of suppressing delay of a drive signal and a display apparatus including the drive circuit (Paragraph [0007]). Claim 9 , Takahashi (Fig. 1-7) discloses wherein each of the multiple stages (10; Fig. 1) further includes an 11th transistor (M5; Fig. 6) including a gate configured to be supplied with a signal output from another stage (R1(Qn+2); Fig. 6), and a source and a drain (M5; Fig. 6; wherein figure shows transistor M5 having two electrodes), one of the source and the drain (M5; Fig. 6) electrically connected to the first output terminal (Gout; Fig. 6) and another of the source and the drain (M5; Fig. 6) electrically connected to the third reference voltage source (Vgl; Fig. 6). Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Iwase in view of Park’s scanning signal line drive circuit by applying a second output terminal, as taught by Takahashi, so to use a scanning signal line drive circuit with a second output terminal for providing a drive circuit capable of suppressing delay of a drive signal and a display apparatus including the drive circuit (Paragraph [0007]). Claim 11 , Iwase in view of Park the scanning signal line drive circuit according to claim 2. Iwase in view of Park does not expressly disclose wherein each of the multiple stages further includes a second clock terminal configured to receive a second clock signal having a phase identical to or a phase shifted from a phase of the first clock signal, and a third clock terminal configured to receive a third clock signal having a phase shifted from the phase of the second clock signal, and the stabilization circuit further includes a 12th transistor including a gate electrically connected to the second clock terminal and a source and a drain, one of the source and the drain electrically connected to the second internal node, and a 13th transistor including a gate electrically connected to the third clock terminal, and a source and a drain, one of the source and the drain electrically connected to the second internal node and another of the source and the drain electrically connected to the second reference voltage source. Takahashi (Fig. 1-7) discloses wherein each of the multiple stages (10; Fig. 1) further includes a second clock terminal (CKD; Fig. 6) configured to receive a second clock signal (CKD; Fig. 7) having a phase identical to or a phase shifted (CKD; Fig. 7) from a phase of the first clock signal (CKA; Fig. 7), and a third clock terminal (CKC; Fig. 6) configured to receive a third clock signal (CKC; Fig. 7) having a phase shifted (CKC; Fig. 7) from the phase of the second clock signal (CKD; Fig. 7), and the stabilization circuit (Fig. 6) further includes a 12th transistor (M6; Fig. 6) including a gate electrically connected to the second clock terminal (CKD; Fig. 6) and a source and a drain (Fig. 6; wherein figure shows transistor M6 with two electrodes), one of the source and the drain (M6; Fig. 6) electrically connected to the second internal node (netB; Fig. 6), and a 13th transistor (M7; Fig. 6) including a gate electrically connected to the third clock terminal (CKC; Fig. 6), and a source and a drain (Fig. 6; wherein figure shows transistor M7 with two electrodes), one of the source and the drain (M7; Fig. 6) electrically connected to the second internal node (netB; Fig. 6) and another of the source and the drain (Fig. 6; wherein figure shows transistor M6 with two electrodes) electrically connected to the second reference voltage source (Vpl; Fig. 6). Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Iwase in view of Park’s scanning signal line drive circuit by applying a second output terminal, as taught by Takahashi, so to use a scanning signal line drive circuit with a second output terminal for providing a drive circuit capable of suppressing delay of a drive signal and a display apparatus including the drive circuit (Paragraph [0007]) . 07-22-aia AIA Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Iwase et al (US 2011/0199354 A1) in view of Park et al (US 2006/0227094 A1) and Jang et al (US 2005/0156856 A1) as applied to claim 3 above, and further in view of Ning et al (US 2022/0293035 A1) . Claim 12 , Jang (Fig. 1-11) discloses a potential of the second charge supply source (VDD2; Fig. 5) is lower than the potential (-20V; Fig. 6) of the first reference voltage source (VSS and -5V; Fig. 6) during the at least part of the vertical blanking period (Paragraph [0092]), and the potential of the first charge supply source (VDD1; Fig. 6) is higher than (20V; Fig. 6) the potential of the second charge supply source (VDD2; Fig. 6) during the effective display period of one (Odd frame; Fig. 6) of two consecutive vertical scanning periods (odd and even frame; Fig. 6), and the potential of the second charge supply source (VDD2; Fig. 6) is higher than (20V; Fig. 6) the potential of the first charge supply source (VDD1; Fig. 6) during the effective display period of another (Even frame; Fig. 6) of the two consecutive vertical scanning periods (odd and even frame; Fig. 6). Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Iwase in view of Park’s scanning signal line drive circuit by applying an alternating voltage source, as taught by Jang, so to use a scanning signal line drive circuit with an alternating voltage source for providing an active matrix display device capable of preventing degradation of a shift register to improve its life span and improve picture quality (Paragraph [0025]). Iwase in view of Park and Jang does not expressly disclose wherein the stabilization circuit further includes a 14th transistor including a gate electrically connected to a third internal node, and a source and a drain, one of the source and the drain electrically connected to the first internal node and another of the source and the drain configured to be supplied with the first reference potential, a 15th transistor including a gate electrically connected to the third internal node, and a source and a drain, one of the source and the drain electrically connected to the first output terminal and another of the source and the drain configured to be supplied with the second reference potential, a 16th transistor including a gate electrically connected to the first internal node, and a source and a drain, one of the source and the drain electrically connected to the third internal node and another of the source and the drain electrically connected to the second reference voltage source, and a 17th transistor including a source and a drain, one of the source and the drain electrically connected to a second charge supply source configured to supply charge to the third internal node and another of the source and the drain electrically connected to the third internal node. Ning (Fig. 1-3) discloses wherein the stabilization circuit (Fig. 1) further includes a 14th transistor (M8B; Fig. 1) including a gate electrically connected to a third internal node (PD2; Fig. 1), and a source and a drain (M8B; Fig. 1; wherein figure shows transistor M8B having two electrodes), one of the source and the drain (M8B; Fig. 1) electrically connected to the first internal node (PU1 and PU2; Fig. 1) and another of the source and the drain (M8B; Fig. 1) configured to be supplied with the first reference potential (VGL; Fig. 1), a 15th transistor (M11B; Fig. 1) including a gate electrically connected to the third internal node (PD2; Fig. 1), and a source and a drain (M11B; Fig. 1; wherein figure shows transistor M11B having two electrodes), one of the source and the drain (M11B; Fig. 1) electrically connected to the first output terminal (Gout; Fig. 1) and another of the source and the drain (M11B; Fig. 1) configured to be supplied with the second reference potential (VGL; Fig. 1), a 16th transistor (M6B; Fig. 1) including a gate electrically connected to the first internal node (PU1 and PU2; Fig. 1), and a source and a drain (M6B; Fig. 1; wherein figure shows transistor M6B having two electrodes), one of the source and the drain (M6B; Fig. 1) electrically connected to the third internal node (PD2; Fig. 1) and another of the source and the drain (M6B; Fig. 1) electrically connected to the second reference voltage source (LVGL; Fig. 1), and a 17th transistor (M5B; Fig. 1) including a source and a drain (M5B; Fig. 1; wherein figure shows transistor M5B having two electrodes), one of the source and the drain (M5B; Fig. 1) electrically connected to a second charge supply source (VDDe; Fig. 1) configured to supply charge to the third internal node (PD2; Fig. 1) and another of the source and the drain (M5B; Fig. 1) electrically connected to the third internal node (PD2; Fig. 1). Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Iwase in view of Park and Jang’s scanning signal line drive circuit by applying a driving method, as taught by Ning, so to use a scanning signal line drive circuit with a driving method for providing an active matrix display device capable of preventing degradation of a shift register to improve its life span and improve picture quality (Paragraph [0025]) . 07-22-aia AIA Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Iwase et al (US 2011/0199354 A1) in view of Park et al (US 2006/0227094 A1) and Jang et al (US 2005/0156856 A1) as applied to claim 3 above, and further in view of Tobita (US 2008/0219401 A1) . Claim 13 , Jang (Fig. 1-11) discloses a 23rd transistor (T6; Fig. 5) including a gate electrically connected to the set terminal (SP and 35; Fig. 5), and a source and a drain (Fig. 5; wherein figure shows transistor T6 with two electrodes), one of the source and the drain (T6; Fig. 5) electrically connected to the second internal node (QBO; Fig. 5) and another of the source and the drain (T6; Fig. 5) electrically connected (Fig. 5; wherein figure shows an additional transistor T8 also enabled by set signal (SP) therefore both transistors are enabled at the same time which means the other electrode of transistor T6 is electrically connected to node QBE through transistor T8 and voltage source Vss) to the third internal node (QBE; Fig. 5), the potential of the first charge supply source (VDD1; Fig. 5) and a potential of the second charge supply source (VDD2; Fig. 5) are each lower than the potential (-20V; Fig. 6) of the first reference voltage source (VSS and -5V; Fig. 6) during the at least part of the vertical blanking period (Paragraph [0092]), and during the effective display period of one (Odd frame; Fig. 6) of two consecutive vertical scanning periods (odd and even frame; Fig. 6), the potential of the first charge supply source (VDD1; Fig. 6) is higher than (20V; Fig. 6) the potential of the second charge supply source (VDD2; Fig. 6), and during the effective display period of another (Even frame; Fig. 6) of the two consecutive vertical scanning periods (odd and even frame; Fig. 6), the potential of the second charge supply source (VDD2; Fig. 6) is higher than (20V; Fig. 6) the potential of the first charge supply source (VDD1; Fig. 6). Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Iwase in view of Park’s scanning signal line drive circuit by applying an alternating voltage source, as taught by Jang, so to use a scanning signal line drive circuit with an alternating voltage source for providing an active matrix display device capable of preventing degradation of a shift register to improve its life span and improve picture quality (Paragraph [0025]). Iwase in view of Park and Jang does not expressly disclose wherein the stabilization circuit further includes a 14th transistor including a gate electrically connected to a third internal node, and a source and a drain, one of the source and the drain electrically connected to the first internal node and another of the source and the drain configured to be supplied with the first reference potential, a 15th transistor including a gate electrically connected to the third internal node, and a source and a drain, one of the source and the drain electrically connected to the first output terminal and another of the source and the drain configured to be supplied with the second reference potential, an 18th transistor including a source and a drain, one of the source and the drain electrically connected to the first charge supply source configured to supply charge to the second internal node and another of the source and the drain electrically connected to the second internal node, a 19th transistor including a gate, a source, and a drain, the gate and one of the source and the drain electrically connected to the second internal node and another of the source and the drain electrically connected to the first charge supply source, a 20th transistor including a source and a drain, one of the source and the drain electrically connected to a second charge supply source configured to supply charge to the third internal node and another of the source and the drain electrically connected to the third internal node, a 21st transistor including a gate, a source, and a drain, the gate and one of the source and the drain electrically connected to the third internal node and another of the source and the drain electrically connected to the second charge supply source, a 22nd transistor including a gate electrically connected to the first internal node, and a source and a drain, one of the source and the drain electrically connected to the second internal node and another of the source and the drain electrically connected to the third internal node. Tobita (Fig. 1-40) discloses wherein the stabilization circuit (41 and 42; Fig. 24; 42; Fig. 13A; 41; Fig. 13B) further includes a 14th transistor (Q5A; Fig. 13B) including a gate electrically connected to a third internal node (N3; Fig. 13B), and a source and a drain (Fig. 13B; wherein figure shows transistor Q5A with two electrodes), one of the source and the drain (Q5A; Fig. 13B) electrically connected to the first internal node (N1; Fig. 13B) and another of the source and the drain (Q5A; Fig. 13B) configured to be supplied with the first reference potential (S1; Fig. 13B), a 15th transistor (Q2; Fig. 24) including a gate electrically connected to the third internal node (N3; Fig. 24), and a source and a drain (Fig. 13B; wherein figure shows transistor Q2 with two electrodes), one of the source and the drain (Q2; Fig. 24) electrically connected to the first output terminal (OUT and Gk; Fig. 24) and another of the source and the drain (Q2; Fig. 24) configured to be supplied with the second reference potential (S1 and VSS; Fig. 24), an 18th transistor (Q6B; Fig. 13A) including a source and a drain (Fig. 13A; wherein figure shows transistor Q6B with two electrodes), one of the source and the drain (Q6B; Fig. 13A) electrically connected to the first charge supply source (/CLK and CK2; Fig. 13A) configured to supply charge to the second internal node (N4; Fig. 13A) and another of the source and the drain (Q6B; Fig. 13A) electrically connected to the second internal node (N4; Fig. 13A), a 19th transistor (Q10B; Fig. 13A) including a gate, a source, and a drain (Fig. 13A; wherein figure shows transistor Q10B with three electrodes), the gate and one of the source and the drain electrically (Q10B; Fig. 13A) connected to the second internal node (N4; Fig. 13A) and another of the source and the drain electrically (Q10B; Fig. 13A) connected to the first charge supply source (/CLK and CK2; Fig. 13A), a 20th transistor (Q6A; Fig. 13B) including a source and a drain (Fig. 13B; wherein figure shows transistor Q6A with two electrodes), one of the source and the drain (Q6A; Fig. 13B) electrically connected to a second charge supply source (CLK and CK1; Fig. 13B) configured to supply charge to the third internal node (N3; Fig. 13B) and another of the source and the drain (Q6A; Fig. 13B) electrically connected to the third internal node (N3; Fig. 13B), a 21st transistor (Q10A; Fig. 13B) including a gate, a source, and a drain (Fig. 13B; wherein figure shows transistor Q10A with three electrodes), the gate and one of the source and the drain (Q10A; Fig. 13B) electrically connected to the third internal node (N3; Fig. 13B) and another of the source and the drain (Q10A; Fig. 13B) electrically connected to the second charge supply source (CLK and CK1; Fig. 13B), a 22nd transistor (Q7B; Fig. 13A) including a gate electrically connected to the first internal node (N1; Fig. 13A), and a source and a drain (Fig. 13B; wherein figure shows transistor Q7B with two electrodes), one of the source and the drain (Q7B; Fig. 13A) electrically connected to the second internal node (N4; Fig. 13A) and another of the source and the drain (Q7B; Fig. 13A) electrically connected (Fig. 13A and 13B; wherein figure shows an additional transistor Q7A also enabled by node N1 therefore both transistors are enabled at the same time which means the other electrode of transistor Q7B is electrically connected to node N3 through transistor Q7A and voltage source S1 (VSS)) to the third internal node (N3; Fig. 13B). Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Iwase in view of Park and Jang’s scanning signal line drive circuit by applying two pull down circuits, as taught by Tobita, so to use a scanning signal line drive circuit with two pull down circuits for providing threshold voltage shifts of transistors which are constituents of a shift register circuit are controlled to prevent a malfunction in the shift register circuit (Paragraph [0025]). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM J SNYDER whose telephone number is (571)270-3460. The examiner can normally be reached Monday-Friday 8am-4:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh D Nguyen can be reached at (571)272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Adam J Snyder/Primary Examiner, Art Unit 2623 06/11/2026 Application/Control Number: 19/411,732 Page 2 Art Unit: 2623 Application/Control Number: 19/411,732 Page 3 Art Unit: 2623 Application/Control Number: 19/411,732 Page 4 Art Unit: 2623 Application/Control Number: 19/411,732 Page 5 Art Unit: 2623 Application/Control Number: 19/411,732 Page 6 Art Unit: 2623 Application/Control Number: 19/411,732 Page 7 Art Unit: 2623 Application/Control Number: 19/411,732 Page 8 Art Unit: 2623 Application/Control Number: 19/411,732 Page 9 Art Unit: 2623 Application/Control Number: 19/411,732 Page 10 Art Unit: 2623 Application/Control Number: 19/411,732 Page 11 Art Unit: 2623 Application/Control Number: 19/411,732 Page 12 Art Unit: 2623 Application/Control Number: 19/411,732 Page 13 Art Unit: 2623 Application/Control Number: 19/411,732 Page 14 Art Unit: 2623 Application/Control Number: 19/411,732 Page 15 Art Unit: 2623 Application/Control Number: 19/411,732 Page 16 Art Unit: 2623 Application/Control Number: 19/411,732 Page 17 Art Unit: 2623 Application/Control Number: 19/411,732 Page 18 Art Unit: 2623 Application/Control Number: 19/411,732 Page 19 Art Unit: 2623 Application/Control Number: 19/411,732 Page 20 Art Unit: 2623 Application/Control Number: 19/411,732 Page 21 Art Unit: 2623 Application/Control Number: 19/411,732 Page 22 Art Unit: 2623
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