DETAIL ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. In response to the restriction claims 1-23 and 47-69 have been selected and claims 24-46 have been withdrawn.
ACKNOWLEDGEMENT OF REFERENCES CITED BY APPLICANT
Information Disclosure Statement
3. As required by M.P.E.P. 2001.06(b) and 37 C.F.R. 1.98(d), since the instant application has been identified as a continuation application of an earlier filed application and is relied upon for an earlier filing date under 35 U.S.C. 120, the examiner has reviewed the prior art cited in the earlier related application as required by M.P.E.P. 707.05 and 904 and as stated in M.P.E.P. 2001.06(b), no separate citation of the same prior art need be made by the applicants in the instant application.
INFORMATION CONCERNING DRAWING:
4. The applicant’s drawings submitted on 12/08/2025 are acceptable for examination purposes.
RELEVANT PRIOR ART THE EXAMINER:
5. The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure. See MPEP 707.05(c).
Harris et al. (US 11,543,972 B1) teaches “…Dual In-line Memory Module (DIMM) wherein each of the memory devices 110-1 through 110-N comprises a Double Data Rate (DDR) dynamic random access memory (DRAM) device having a particular density, e.g., 256 Mb, 512 Mb, 1 Gb or 2 Gb, etc. Also, the memory devices can be of any known or heretofore unknown DDR type, e.g., DDR2 (operable with 1.8 V), DDR3 (operable with 1.35V to 1.5V), and the like. Further, the DIMM configuration of an exemplary memory module may include unbuffered DIMMs, registered DIMMs (RDIMMs), or fully buffered DIMMs...” (par. 009).
HSU et al. (US 20090103385 A1) teaches “… the voltage regulator 200 comprises a controller 12 having a feedback terminal and an output terminal, a filter 14 having an input terminal and an output terminal, a linear voltage regulator 16, and a feedback circuit 18. The output of the controller 12 is connected to the input terminal of the filter 14, and the filter 14 outputs a VDD voltage at the output terminal thereof. The VDD voltage is transmitted to the linear voltage regulator 16, and is converted into a VTT voltage transmitted to the DDR2 slots and the DDR3 slots...” (par. 0017)
Berke (US 20100135097 A1) teaches “…includes a voltage optimized dual in-line memory module (DIMM) 102 and a system board 104. The DIMM 102 includes dynamic random access memories (DRAMs) 106 and a voltage regulator 108. The system board 104 includes a setup module 110, a voltage regulator 112 …”(par. 0015).
INFORMATION CONCERNING CLAIMS:
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
5. Claims 1-23 and 47-69 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
6. The independent claim 1, in part recites:
“…a set of power conduits … a set of data conduits … set of address and control conduits …”
The claimed specification does not appear to describe/support the above limitations as claimed. The independent claim 47 recites similar limitations and are rejected based on the same ground of rejection. Claims 1-23 and 48-66 are rejected at least based on their respected independent base claims.
7. The independent claim 1, in part recites:
“each component of the plurality of components is electrically connected to one or more of the plurality of regulated voltage lines, and receives power exclusively from the plurality of regulated voltage lines” (emphasis added).
The claimed specification does not appear to describe/support the above limitations as claimed. The independent claim 47 recites similar limitations and are rejected based on the same ground of rejection. Claims 1-23 and 48-66 are rejected at least based on their respected independent base claims.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
8. Claims 1-23 and 47-66 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-38 of U.S. Patent No. 12,373,366 B2 (hereinafter “the patent”). Although the claims at issue are not identical, they are not patentably distinct from each other because minor difference in claims language and change in order of limitations in the claims does not make the claims patentably distinct from each.
9. claims 1-23 of the instant application compared with claims patent in the following table. Claims 47-66 of the instant application substantially recite similar limitations are not shown in the table.
US Patent 12,373,366 B2
US Application 19/412,697
2. (Currently Amended) A dual in-line memory module (DIMM) configured to fit into a memory slot connector of a system board of a computer system, the memory slot connector including a set of power conduits, a set of data conduits, and a set of address and control conduits, wherein data signals are transferred between the system board and the DIMM via the set of data conduits, and address and control signals are delivered from the system board to the DIMM via the set of address and control conduits, the DIMM comprising:
a printed circuit board (PCB) having edge connections configured to fit into the memory slot connector of the system board,
the PCB including: a first set of edge connections configured to be electrically connected to the set of power conduits and operable to deliver to the DIMM power from power rails of the system board via the set of power conduits, wherein the power delivered to the DIMM from the power rails of the system board is the only power received by the DIMM;
a second set of edge connections configured to be electrically connected to the set of data conduits,
and a third set of edge connections configured to be electrically connected to the set of address and control conduits, a set of voltage supply lines electrically connected to the first set of edge connections and configured to receive the power delivered to the DIMM from the power rails of the system board by way of the memory slot connector of the system board and the first set of edge connections of the DIMM, a set of data lines electrically connected to the second set of edge connections, and a set of address and control lines electrically connected to the third set of edge connections;
a controller including a voltage monitor circuit and nonvolatile memory, the controller coupled to the PCB and to an input voltage supply line of the set of voltage supply lines, the voltage monitor circuit configured to:
monitor an input voltage supplied via the input voltage supply line;
generate a trigger signal upon detecting a trigger condition; and (iii) transmit the trigger signal to at least one other portion of the controller, wherein the controller is configured to perform, in response to the trigger signal, a write operation to write data into the nonvolatile memory, and wherein the trigger condition occurs when the input voltage exceeds a first threshold voltage;
a set of components coupled to the PCB, the set of components including a plurality of double data rate (DDR) synchronous dynamic random access memory (SDRAM) devices coupled to the set of address and control lines and to the set of data lines, the DDR SDRAM devices being operable to receive or output data signals via the set of data lines based on address and control signals received from the system board via the set of address and control lines;
and first, second, third, and fourth converter circuits coupled to the PCB and to the input voltage supply line, and configured to receive power from the input voltage supply line and to deliver power via first, second, third, and fourth regulated voltage lines, wherein the set of components includes: a first component configured to receive power via at least the first regulated voltage line; a second component configured to receive power via at least the second regulated voltage line; a third component configured to receive power via at least the third regulated voltage line; and a fourth component configured to receive power via at least the fourth regulated voltage line; wherein each component of the set of components: (i) is electrically connected to one or more of the first, second, third, and fourth regulated voltage lines; and (ii) receives power only via the one or more of the first, second, third, and fourth regulated voltage lines, wherein the plurality of DDR SDRAM devices includes: a first group of at least five DDR SDRAM devices that are each connected to a first chip select line configured to electrically conduct a first chip select signal; a second group of at least four DDR SDRAM devices that are each connected to a second chip select line configured to electrically conduct a second chip select signal; wherein when power from the power rails of the system board is provided to the DIMM and each group of the first and second groups of DDR SDRAM devices is not in self-refresh mode: the first group of DDR SDRAM devices is configured to be enabled, in response to the first chip select signal, to receive or output at least 40 1-bit DDR data signals in parallel via at least 40 data lines of the set of data lines independently of whether the second group of DDR SDRAM devices is enabled, in response to the second chip select signal, to receive or output an integer number of 1-bit DDR data signals in parallel via an integer number of data lines of the set of data lines; the at least 40 1-bit DDR data signals include at least 32 1-bit wide DDR data signals and at least eight 1-bit DDR error-correcting code (ECC) data signals; and wherein the sum of the at least 40 data lines and the integer number of data lines equals a total number of data conduits of the set of data conduits of the memory slot connector, and the total number of data conduits is at least 72 data conduits.
1.A dual in-line memory module (DIMM) configured to fit into a memory slot connector of a system board of a host computer system, the system board having power rails, where the memory slot connector includes a set of power conduits connected to the power rails, a set of data conduits, and a set of address and control conduits, the DIMM comprising:
a printed circuit board (PCB) including an interface having PCB edge connections configured to fit into the memory slot connector of the system board,
wherein the PCB edge connections include a first set of edge connections configured to electrically connect to the set of power conduits that are configured to exclusively deliver power to the DIMM from the power rails,
wherein the first set of edge connections are electrically connected to a set of input voltage supply lines that are configured to receive the power delivered to the DIMM from the power rails via the interface,
a second set of edge connections configured to electrically connect to the set of data conduits,
wherein the third set of edge connections are electrically connected to a set of address and control lines via the interface;
a controller, wherein the controller is coupled to the PCB and to an input voltage supply line of the set of input voltage supply lines and is configured to
monitor an input voltage supplied by the input voltage supply line, and
perform, in response to a first trigger signal, a write operation that causes data to be written to a nonvolatile memory;
a power module including a voltage conversion element,
wherein the power module is coupled to the PCB and to the input voltage supply line, and is configured to continuously receive input power from the input voltage supply line and to deliver an output power via a plurality of regulated voltage lines having a corresponding plurality of regulated voltages, wherein the output power is derived from the input power, and the plurality of regulated voltage lines includes at least a first regulated voltage line for delivering a first regulated voltage and a second regulated voltage line for delivering a second regulated voltage, and the voltage conversion element is configured to produce the first regulated voltage and the second regulated voltage;
and a plurality of components coupled to the PCB and the power module, the plurality of components including a plurality of volatile memory devices coupled to the set of address and control lines and to the set of data lines, wherein the plurality of volatile memory devices are operable to receive or output data signals via the set of data lines based on address and control signals received from the system board via the set of address and control lines, and each component of the plurality of components is electrically connected to one or more of the plurality of regulated voltage lines, and receives power exclusively from the plurality of regulated voltage lines.
Claim 1:
DDR SDRAM devices
2. The DIMM of claim 1,
wherein the plurality of volatile memory devices includes a plurality of double data rate (DDR) synchronous dynamic random access memory (SDRAM) devices.
Claim 1:
wherein the plurality of DDR SDRAM devices includes: a first group of at least five DDR SDRAM devices that are each connected to a first chip select line configured to electrically conduct a first chip select signal; a second group of at least four DDR SDRAM devices that are each connected to a second chip select line configured to electrically conduct a second chip select signal
3. The DIMM of claim 2,
wherein the plurality of DDR SDRAM devices includes a first group of DDR SDRAM devices that are each connected to a first chip select line configured to electrically conduct a first chip select signal, and are coupled to a first subset of data lines of the set of data lines, a second group of DDR SDRAM devices that are each connected to a second chip select line configured to electrically conduct a second chip select signal and are coupled to a second subset of data lines of the set of data lines.
Claim 1:
a first group of at least five DDR SDRAM devices that are each connected to a first chip select line configured to electrically conduct a first chip select signal; a second group of at least four DDR SDRAM devices
4. The DIMM of claim 3,
wherein the first group of DDR SDRAM devices includes at least five DDR SDRAM devices, and the second group of DDR SDRAM devices includes at least four DDR SDRAM devices.
Claim 1:
wherein when power from the power rails of the system board is provided to the DIMM and each group of the first and second groups of DDR SDRAM devices is not in self-refresh mode: the first group of DDR SDRAM devices is configured to be enabled, in response to the first chip select signal, to receive or output at least 40 1-bit DDR data signals in parallel via at least 40 data lines of the set of data lines independently of whether the second group of DDR SDRAM devices is enabled, in response to the second chip select signal, to receive or output an integer number of 1-bit DDR data signals in parallel via an integer number of data lines of the set of data lines
5. The DIMM of claim 3,
wherein, when power from the power rails of the system board is provided to the DIMM and each group of the first and second groups of DDR SDRAM devices is not in self-refresh mode, the first group of DDR SDRAM devices is configured to be enabled, in response to the first chip select signal, to receive or output at least 16 1-bit DDR data signals in parallel via the first subset of data lines of the set of data lines independently of whether the second group of DDR SDRAM devices is enabled, in response to the second chip select signal, to receive or output at least 16 1-bit DDR data signals in parallel via the second subset of data lines of the set of data lines.
Claim 1:
wherein the sum of the at least 40 data lines and the integer number of data lines equals a total number of data conduits of the set of data conduits of the memory slot connector, and the total number of data conduits is at least 72 data conduits
6. The DIMM of claim 5,
wherein a sum of a number of data lines of the first and second subsets of data lines equals a total number of data conduits of the set of data conduits of the memory slot connector, and the total number of data conduits is at least 32 data conduits.
Claim 1:
the at least 40 1-bit DDR data signals include at least 32 1-bit wide DDR data signals and at least eight 1-bit DDR error-correcting code (ECC) data signals
7. The DIMM of claim 5,
wherein the first subset of data signals includes an integer number of error-correcting code (ECC) data lines.
Claim 1:
at least eight 1-bit DDR error-correcting code (ECC) data signals
8. The DIMM of claim 5,
wherein an integer number of 1-bit wide DDR ECC data lines equals eight.
Claim 1:
wherein the controller is configured to perform, in response to the trigger signal, a write operation to write data into the nonvolatile memory, and wherein the trigger condition occurs when the input voltage exceeds a first threshold voltage
9. The DIMM of claim 1,
wherein the controller is further configured to receive the first trigger signal from a voltage monitoring circuit upon a detection of a first trigger condition, and the first trigger condition occurs when the input voltage exceeds a first threshold voltage.
Claim 1:
a controller including a voltage monitor circuit … generate a trigger signal upon detecting a trigger condition… the trigger condition occurs when the input voltage exceeds a first threshold voltage
10. The DIMM of claim 9,
wherein the controller includes a voltage monitoring circuit, wherein the voltage monitoring circuit is configured to monitor the input voltage, generate the first trigger signal upon a detection of a first trigger condition, and the first trigger condition occurs when the input voltage exceeds a first threshold voltage.
Claim 1:
controller including a voltage monitor circuit and nonvolatile memory
11. The DIMM of claim 10,
wherein the controller includes the nonvolatile memory.
11. The DIMM of claim 1,
Wherein when power is provided to the DIMM from the power rails of the system board the voltage monitor circuit compares the input voltage to a plurality of threshold voltages including the first threshold voltage and a second threshold voltage.
13. The DIMM of claim 12, wherein, when power from the power rails of the system board is provided to the DIMM,
an additional trigger condition occurs when the input voltage is above the first threshold and below the second threshold; and wherein, in response to the additional trigger condition,
the voltage monitor circuit is further configured to generate and transmit a second trigger signal.
12. The DIMM of claim 10,
wherein when power is provided to the DIMM from the power rails of the system board, the voltage monitor circuit compares the input voltage to a plurality of threshold voltages including the first threshold voltage and a second threshold voltage, and wherein the voltage
monitoring circuit generates a second trigger signal upon a detection of a second trigger condition, the second trigger condition occurs when the input voltage is below the second threshold voltage.
Claim 1:
first, second, third, and fourth converter circuits coupled to the PCB and to the input voltage supply line, and configured to receive power from the input voltage supply line and to deliver power via first, second, third, and fourth regulated voltage lines, wherein the set of components includes: a first component configured to receive power via at least the first regulated voltage line; a second component configured to receive power via at least the second regulated voltage line; a third component configured to receive power via at least the third regulated voltage line; and a fourth component configured to receive power via at least the fourth regulated voltage line
13. The DIMM of claim 12,
wherein the voltage conversion element is configured to continuously receive the input power from the input voltage supply line and to deliver the output power via the plurality of regulated voltage lines, wherein the plurality of regulated voltage lines further includes a third regulated voltage line for delivering a third regulated voltage, and a fourth regulated voltage line for delivering a fourth regulated voltage, and the voltage conversion element is further configured to produce the first regulated voltage, the second regulated voltage, the third regulated voltage, and the fourth regulated voltage using the input power received exclusively from the input voltage supply line.
15. The DIMM of claim 1,
wherein each of the first, second, and third converter circuits is a buck converter, and the fourth converter circuit is a voltage reducing circuit.
14. The DIMM of claim 13,
wherein the voltage conversion element further includes a first buck converter configured to produce the first regulated voltage, a second buck converter configured to produce the second regulated voltage, a third buck converter configured to produce the third regulated voltage, and a converter circuit configured to produce the fourth regulated voltage.
Claim 1:
first, second, third, and fourth converter circuits coupled to the PCB and to the input voltage supply line, and configured to receive power from the input voltage supply line and to deliver power via first, second, third, and fourth regulated voltage lines, wherein the set of components includes: a first component configured to receive power via at least the first regulated voltage line; a second component configured to receive power via at least the second regulated voltage line; a third component configured to receive power via at least the third regulated voltage line; and a fourth component configured to receive power via at least the fourth regulated voltage line; wherein each component of the set of components: (i) is electrically connected to one or more of the first, second, third, and fourth regulated voltage lines; and (ii) receives power only via the one or more of the first, second, third, and fourth regulated voltage line
15. The DIMM of claim 13,
wherein the plurality of components includes a first component coupled to three regulated voltage lines of the first regulated voltage line, the second regulated voltage line, the third regulated voltage line, and the fourth regulated voltage line and configured to receive power via the three regulated voltage lines, a second component coupled to two regulated voltage lines of the first, regulated voltage line, the second regulated voltage line, the third regulated voltage line, and the fourth regulated voltage lines and configured to receive power via the two regulated voltage lines, and each component of the plurality of components is electrically connected to one or more of the first, second, third, and fourth regulated voltage lines, and receives power only via the one or more of the first, second, third, and fourth regulated voltage lines.
2. The DIMM of claim 1,
wherein the controller further includes: a data storage element configured to store a plurality of data bits and a logic element coupled to the nonvolatile memory and the data storage element and configured to electrically communicate with the nonvolatile memory and the data storage element, and
wherein the write operation conducted by the controller in response to the trigger signal includes: a first write operation to write a first set of data bits into a first portion of the data storage element;
a second write operation to write a second set of data bits into a second portion of the data storage element; and subsequently a third write operation to write a third set of data bits from the data storage element into the nonvolatile memory,
wherein the third set of data bits includes the first and second sets of data bits written during the first and second write operations.
16. The DIMM of claim 12,
wherein the controller further includes: a data storage element is coupled to the nonvolatile memory and is configured to store a plurality of data bits, and to electrically communicate with the nonvolatile memory,
wherein the write operation performed by the controller in response to the trigger signal includes: a first write operation to write a first set of data bits into a first portion of the data storage element;
a second write operation to write a second set of data bits into a second portion of the data storage element; and
subsequently, a third write operation to write a third set of data bits from the data storage element into the nonvolatile memory.
Claim 2:
wherein the third set of data bits includes the first and second sets of data bits written during the first and second write operations.
17. The DIMM of claim 16,
wherein the third set of data bits includes data based on the first and second sets of data bits written during the first and second write operations.
5. The DIMM of claim 2,
wherein, prior to performing the third write operation, the logic element is configured to perform, in response to the detected trigger signal, a plurality of read operations to read the first and second sets of data bits from the first and second portions of the data storage element, respectively, and to generate the third set of data bits based on the read first and second sets of data bits.
18. The DIMM of claim 16,
wherein, prior to performing the third write operation, the controller is configured to perform, in response to the generated first trigger signal, a plurality of read operations to read the first and second sets of data bits from the first and second portions of the data storage element, respectively, and to generate the third set of data bits based on the read first and second sets of data bits.
6. The DIMM of claim 2,
wherein, prior to performing the third write operation, the logic element is configured to perform, in response to the detected trigger signal, a read operation to read the first and second sets of data bits from the first and second portions of the data storage element, respectively, and to generate the third set of data bits based on the read first and second sets of data bits.
19. The DIMM of claim 16,
wherein, prior to performing the third write operation, the controller is configured to perform, in response to the generated first trigger signal, a read operation to read the first and second sets of data bits from the first and second portions of the data storage element, respectively, and to generate the third set of data bits based on the read first and second sets of data bits.
7. The DIMM of claim 2,
wherein, prior to performing the first and second write operations, the logic element is configured to perform, in response to the detected trigger signal, one or more read operations.
20. The DIMM of claim 16,
wherein, prior to performing the first and second write operations, the controller is configured to perform, in response to the generated first trigger signal, one or more read operations.
Claim 1:
wherein the plurality of DDR SDRAM devices includes:
a first group of at least five DDR SDRAM devices that are each connected to a first chip select line configured to electrically conduct a first chip select signal;
a second group of at least four DDR SDRAM devices that are each connected to a second chip select line configured to electrically conduct a second chip select signal;
8. The DIMM of claim 7,
wherein the logic element is configured to perform a first read operation of the one or more read operations by reading the first and second sets of data bits from the first and second groups of DDR SDRAM devices, respectively.
21. The DIMM of claim 20,
wherein the plurality of volatile memory devices includes a plurality of double data rate (DDR) synchronous dynamic random access memory (SDRAM) devices, the plurality of DDR SDRAM devices includes a first group of DDR SDRAM devices that are each connected to a first chip select line configured to electrically conduct a first chip select signal, and
a second group of DDR SDRAM devices that are each connected to a second chip select line configured to electrically conduct a second chip select signal, and
the controller is configured to perform a first read operation of the one or more read operations by reading the first and second sets of data bits from the first group of DDR SDRAM devices and the second group of DDR SDRAM devices, respectively.
10. The DIMM of claim 2,
wherein the data storage element is a buffer configured to store a plurality of data bits or a First-In First-Out (FIFO) buffer configured to store the plurality of data bits
22. The DIMM of claim 16,
wherein the data storage element is a buffer configured to store the plurality of data bits or a First-In First-Out (FIFO) buffer configured to store the plurality of data bits.
13. The DIMM of claim 12,
wherein, when power from the power rails of the system board is provided to the DIMM, an additional trigger condition occurs when the input voltage is above the first threshold and below the second threshold; and wherein, in response to the additional trigger condition, the voltage monitor circuit is further configured to generate and transmit a second trigger signal.
23. The DIMM of claim 12,
wherein, when power from the power rails of the system board is provided to the DIMM, an additional trigger condition occurs when the input voltage is above the first threshold and below the second threshold, and wherein, in response to the additional trigger condition, the voltage monitor circuit is further configured to generate and transmit the second trigger signal.
Direction OF FUTURE CORRESPONDENCES:
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to HASHEM FARROKH whose telephone number is (571)272-4193. The examiner can normally be reached Monday through Friday from 8:30 am - 5:00 pm.
11. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Mr. Tim Vo can be reached on (571)272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HASHEM FARROKH/Primary Examiner, Art Unit 2138
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