Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Summary
2. The continuation application filed on December 17, 2025, has been received and recorded. There are 1-14 claims in the continuation application of which claims 1, and 8 are independent claims. claims 2-7 and 9-14 are dependent claims. Therefore, claims 1-14 are pending for consideration.
Information Disclosure Statement
3. The information disclosure statement (IDS) submitted was filed along with the mailing date of the continuation application on December 17, 2025. A second IDS was filed on March 31, 2026. Both submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Double Patenting
4. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
4. Claims 1-14 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No.US 12,004,404 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because except for minor wording and insignificant changes in terminology, each and every limitation of claims 1-20 of U.S. Patent No. US 12,004,404 B2 reads on the corresponding limitation of claims 1-14 of the current application 19/422,640. Both the US published Patent and current application recite an electronic apparatus having touch sensor with mesh pattern electrodes.
Comparing claims of the current application and claims 1-20 of the US Patent No. US 12,004,404 B2 is given below:-
Current Application No. 19/422,640
US Patent No.
US 12,004,404 B2
Claim 1: An electronic apparatus comprising:
a display panel comprising a plurality of light emitting pixels;
a first electrode disposed on the display panel and comprising a plurality of first sensor patterns and a plurality of first connection patterns respectively connecting adjacent first sensor patterns;
a second electrode disposed on the display panel and comprising a plurality of second sensor patterns and a plurality of second connection patterns respectively connecting adjacent second sensor patterns; and
an insulating layer disposed between the plurality of first connection patterns and the plurality of second connection patterns; and
a dummy electrode disposed on the insulating layer,
wherein the first sensor patterns, the second sensor patterns, and the second connection patterns are disposed on the same layer as the dummy electrode,
wherein each of the plurality of the first connection patterns comprises a first-first pattern and a first-second pattern spaced apart from each other in a first direction, and respectively extending along a second direction crossing the first direction,
wherein each of the plurality of the second connection patterns comprises a second-first pattern and a second-second pattern spaced apart from each other in the second direction, and respectively extending along the first direction, and
wherein the dummy electrode is disposed between the first-first pattern and the first-second pattern and between the second-first pattern and the second-second pattern in a plan view.
Claim 1: An electronic apparatus comprising:
a display panel including an active region which includes a plurality of light-emitting regions;
a first electrode comprising a plurality of first sensor patterns disposed in the active region and a plurality of first connection patterns respectively connecting adjacent first sensor patterns;
a second electrode comprising a plurality of second sensor patterns insulated from the first electrode and disposed in the active region, and a plurality of second connection patterns respectively connecting adjacent second sensor patterns; and
an insulating layer disposed between the plurality of first connection patterns and the plurality of second connection patterns,
wherein each of the plurality of first connection patterns comprises:
a first pattern and a second pattern spaced apart from each other in a first direction, respectively having a bar shape extending along a second direction crossing the first direction, and each connecting the adjacent first sensor patterns through contact holes formed in the insulating layer,
a third pattern extending along the first direction and connected to each of the first pattern and the second pattern, and
a fourth pattern extending along the first direction, spaced apart from the third pattern in the second direction, and connected to each of the first pattern and the second pattern, wherein each of the plurality of light-emitting regions comprise a light-emitting pixel, and
wherein the light-emitting pixel includes a plurality of sub-pixels disposed between the first pattern and the second pattern along the first direction.
Part of claim 5: The electronic apparatus of claim 4, further comprising a floating pattern insulated from the first electrode and the second electrode, and disposed between the first pattern and the second pattern, ----.
Claim 2 corresponds to part of claim 5 of U.S. Patent No. US 12,004,404 B2;
Claim 3 corresponds to claim 6 of U.S. Patent No. US 12,004,404 B2;
Claim 4 corresponds to claim 4 of U.S. Patent No. US 12,004,404 B2;
Claim 5 corresponds to part of claim 12 and claim 8 of U.S. Patent No. US 12,004,404 B2;
Claim 6 corresponds to part of claim 9 of U.S. Patent No. US 12,004,404 B2;
Claim 7 corresponds to claim 10 of U.S. Patent No. US 12,004,404 B2(it is obvious that the pixels be placed in open areas surrounding by mesh lines);
Claim 8 corresponds to part of claims 12 and 14 of U.S. Patent No. US 12,004,404 B2;
Claim 9 corresponds to part of claim 12 of U.S. Patent No. US 12,004,404 B2;
Claim 10 corresponds to part of claim 12 of U.S. Patent No. US 12,004,404 B2;
Claim 11 corresponds to claim 7 of U.S. Patent No. US 12,004,404 B2;
Claim 12 corresponds to part of claims 8 and 12 of U.S. Patent No. US 12,004,404 B2;
Claim 13 corresponds to part of claim 9 of U.S. Patent No. US 12,004,404 B2; and
Claim 14 corresponds to claim 18 of U.S. Patent No. US 12,004,404 B2(it is obvious that the pixels be placed in open areas surrounding by mesh lines).
5. Claims 1-14 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-19 of U.S. Patent No. US 12,527,198 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because except for minor wording and insignificant changes in terminology, each and every limitation of claims 1-19 of U.S. Patent No. US 12,527,198 B2 reads on the corresponding limitation of claims 1-14 of the current application 19/422,640. Both the US published Patent and current application recite an electronic apparatus having touch sensor with mesh pattern electrodes.
Comparing claims of the current application and claims 1-19 of the US Patent No. US 12,004,404 B2 is given below:-
Current Application No. 19/422,640
US Patent No.
US 12,527,198 B2
Claim 1: An electronic apparatus comprising:
a display panel comprising a plurality of light emitting pixels;
a first electrode disposed on the display panel and comprising a plurality of first sensor patterns and a plurality of first connection patterns respectively connecting adjacent first sensor patterns;
a second electrode disposed on the display panel and comprising a plurality of second sensor patterns and a plurality of second connection patterns respectively connecting adjacent second sensor patterns; and
an insulating layer disposed between the plurality of first connection patterns and the plurality of second connection patterns; and
a dummy electrode disposed on the insulating layer,
wherein the first sensor patterns, the second sensor patterns, and the second connection patterns are disposed on the same layer as the dummy electrode,
wherein each of the plurality of the first connection patterns comprises a first-first pattern and a first-second pattern spaced apart from each other in a first direction, and respectively extending along a second direction crossing the first direction,
wherein each of the plurality of the second connection patterns comprises a second-first pattern and a second-second pattern spaced apart from each other in the second direction, and respectively extending along the first direction, and
wherein the dummy electrode is disposed between the first-first pattern and the first-second pattern and between the second-first pattern and the second-second pattern in a plan view.
Claim 1: An electronic apparatus comprising:
a display panel comprising a plurality of light emitting pixels;
a first electrode disposed on the display panel and comprising a plurality of first sensor patterns and a plurality of first connection patterns respectively connecting adjacent first sensor patterns;
a second electrode disposed on the display panel and comprising a plurality of second sensor patterns and a plurality of second connection patterns respectively connecting adjacent second sensor patterns; and
an insulating layer disposed between the plurality of first connection patterns and the plurality of second connection patterns, wherein each of the plurality of first connection patterns comprises: a first pattern and a second pattern spaced apart from each other in a first direction, respectively having a bar shape extending along a second direction crossing the first direction, and each connecting the adjacent first sensor patterns through contact holes formed in the insulating layer; a third pattern extending along the first direction and connected to each of the first pattern and the second pattern; and a fourth pattern extending along the first direction, spaced apart from the third pattern in the second direction, and connected to each of the first pattern and the second pattern, and wherein the contact holes are arranged along each of the third pattern and the fourth pattern.
Claim 15: The electronic apparatus of claim 8, wherein the floating pattern is disposed on a same layer as the plurality of connecting patterns.
Claim 2 corresponds to part of claim 3 of U.S. Patent No. US 12,527,198 B2;
Claim 3 corresponds to part of claim 7 of U.S. Patent No. US 12,527,198 B2;
Claim 4 corresponds to claim 5 of U.S. Patent No. US 12,527,198 B2;
Claim 5 corresponds to part of claim 6 of U.S. Patent No. US 12,527,198 B2;
Claim 6 corresponds to part of claim 7 of U.S. Patent No. US 12,527,198 B2;
Claim 7 corresponds to claim 8 of U.S. Patent No. US 12,527,198 B2;
Claim 8 corresponds to claim 4 of U.S. Patent No. US 12,527,198 B2;
Claim 9 corresponds to part of claim 12 and claim 8 of U.S. Patent No. US 12,527,198 B2;
Claim 10 corresponds to part of claim 5 of U.S. Patent No. US 12,527,198 B2;
Claim 11 corresponds to claim 6 of U.S. Patent No. US 12,527,198 B2;
Claim 12 corresponds to claim 4 of U.S. Patent No. US 12,527,198 B2;
Claim 13 corresponds to part of claim 12 and claim 8 of U.S. Patent No. US 12,527,198 B2; and
Claim 14 corresponds to part of claim 5 of U.S. Patent No. US 12,527,198 B2(it is obvious that the pixels be placed in open areas surrounding by mesh lines).
Contact
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MD SAIFUL A SIDDIQUI whose telephone number is (571)270-1530. The examiner can normally be reached on Mon-Fri: 9:00AM - 5:30PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Temesghen Ghebretinsae, can be reached on (571)272-3017. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MD SAIFUL A SIDDIQUI/Primary Examiner, Art Unit 2626
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