DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 – 3, 13 – 15 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (2024/0090264) in view of Yanagisawa (4,707,625).
Regarding claim 1, Kim discloses a scan driving circuit (Figure 1: Comprising 200; Figure 4), comprising:
a first inverter circuit (Comprising T3, T4, T7) configured to, output a first signal to a first node (Comprising QB) in response to a carry input signal (Comprising Carry[n-1]), a first clock signal and a second clock signal (Comprising SxCLK1, SxCLK2), and output a second signal to a second node (Comprising Q2), the second signal being obtained by inverting the carry input signal (Comprising Carry[n-1]);
a circuit (Comprising T4, Ta) configured to transmit the second signal of the second node (Comprising Q2) to a third node (Comprising Q) in response to the first signal of the first node (Comprising QB); and
a second inverter circuit (Comprising 404, 50) configured to output a scan signal (Comprising SCANx[n]) and a carry output signal (Comprising Carry[n]) in response to a third signal of the third node (Comprising Q),
the scan signal (Comprising SCANx[n]) and the carry output signal (Comprising Carry[n]) being complementary signals (Carry is negative [0107], scan is positive [0116]).
Kim does not explicitly disclose a diode circuit.
In the same field of endeavor, Yanagisawa discloses an integrated circuit (col. 1, ll. 7 – 12) comprising a diode circuit (Figure 13: Comprising Q64, Q65) configured to transmit the second signal of the second node (Comprising unlabeled common drain junction of Q65, Q66; hereinafter *B*) to a third node (Comprising N2) in response to the first signal of the first node (Receiving
φ
b
m
at Q65, Q66 gates). This is among measures implemented to reduce power consumption (col. 1, ll. 53 – 56).
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the circuit of Kim to be modified with a diode circuit, in view of the teaching of Yanagisawa, to reduce power consumption.
Regarding claim 2, Kim in view of Yanagisawa discloses the scan driving circuit of claim 1. Kim discloses the circuit wherein the circuit includes: a first transistor connected (Comprising T4) to the second node (Figure 4: Comprising Q2); and a second transistor (Comprising Ta) connected between the second node (Comprising Q2) and the third node (Comprising Q).
Kim does not explicitly disclose the diode circuit includes: the first transistor connected between the second node and a first voltage terminal, the first transistor including a gate electrode connected to the first node; and the second transistor including a gate electrode connected to the first voltage terminal.
In the same field of endeavor, Yanagisawa discloses an integrated circuit (col. 1, ll. 7 – 12) wherein the diode circuit includes: the first transistor (Figure 13: Comprising Q65) connected between the second node (Comprising *B*) and a first voltage terminal (Receiving Vcc), the first transistor including a gate electrode (Comprising gate of Q65) connected to the first node (Receiving
φ
b
m
); and the second transistor including a gate electrode (Comprising gate of Q64) connected to the first voltage terminal (Receiving Vcc). This is among measures implemented to reduce power consumption (col. 1, ll. 53 – 56).
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the circuit of Kim to be modified wherein the diode circuit includes: the first transistor connected between the second node and a first voltage terminal, the first transistor including a gate electrode connected to the first node; and the second transistor including a gate electrode connected to the first voltage terminal, in view of the teaching of Yanagisawa, to reduce power consumption.
Regarding claim 3, Kim in view of Yanagisawa discloses the scan driving circuit of claim 2. Kim discloses the circuit wherein the second transistor (Figure 4: Comprising Ta) is a P-type transistor [0112].
Kim does not explicitly disclose the circuit wherein the first transistor is an N-type transistor.
In the same field of endeavor, Yanagisawa discloses an integrated circuit (col. 1, ll. 7 – 12) wherein the first transistor (Figure 13: Comprising Q65) is an N-type transistor (col. 6, ll. 48 – 50) and the second transistor (Comprising Q64) is a P-type transistor (col. 6, ll. 38 – 43). This is among measures implemented to reduce power consumption (col. 1, ll. 53 – 56).
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the circuit of Kim to be modified wherein the first transistor is an N-type transistor, in view of the teaching of Yanagisawa, to reduce power consumption.
Regarding claim 13, Kim discloses an electronic device [0195], comprising:
a display module (Figure 1) configured to display an image [0035]; and
processing circuitry configured to transmit an electrical signal1 to the display module, the display module including, a display panel (Comprising 100) including pixels (Comprising P) connected to a scan line (Comprising GLx2[n]), and a scan driving circuit (Comprising 200; Figure 4) configured to output a scan signal to the scan line ([0042], [0043]) in response to a carry input signal [0098], a first clock signal and a second clock signal (Comprising SxCLK1, SxCLK2), the scan driving circuit including, a first inverter circuit (Comprising T3, T4, T7) configured to,
output a first signal to a first node (Comprising QB) in response to the carry input signal (Comprising Carry[n-1]), the first clock signal and the second clock signal (Comprising SxCLK1, SxCLK2), and
output a second signal to a second node (Comprising Q2), the second signal being obtained by inverting the carry input signal (Comprising Carry[n-1]),
a circuit (Comprising T4, Ta) configured to transmit the second signal of the second node (Comprising Q2) to a third node (Comprising Q) in response to the first signal of the first node (Comprising QB), and
a second inverter circuit (Comprising 404, 50) configured to output the scan signal (Comprising SCANx[n]) in response to a third signal of the third node (Comprising Q),
the carry input signal (Comprising Carry[n]) and the scan signal (Comprising Scanx[n]) being complementary signals (Carry is negative [0107], scan is positive [0116]).
Kim does not explicitly disclose a diode circuit.
In the same field of endeavor, Yanagisawa discloses an integrated circuit (col. 1, ll. 7 – 12) comprising a diode circuit (Figure 13: Comprising Q64, Q65) configured to transmit the second signal of the second node (Comprising unlabeled common drain junction of Q65, Q66; hereinafter *B*) to a third node (Comprising N2) in response to the first signal of the first node (Comprising
φ
b
m
at Q65, Q66 gates). This is among measures implemented to reduce power consumption (col. 1, ll. 53 – 56).
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the device of Kim to be modified with a diode circuit in view of the teaching of Yanagisawa, to reduce power consumption.
Device claims 14, 15 are rejected as reciting limitations similar to those recited in circuit claims 2, 3, respectively.
Allowable Subject Matter
Claims 4 – 12, 16 – 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 4, Kim in view of Yanagisawa discloses the scan driving circuit of claim 1.
The cited prior art fails to singularly or collectively disclose the circuit wherein the first inverter circuit includes: a first transistor connected between a carry input terminal and the first node, the first transistor including a gate electrode connected to a first clock terminal, the first clock terminal configured to receive the first clock signal, and the carry input terminal is configured to receive the carry input signal; a second transistor connected between the carry input terminal and the first node, the second transistor including a gate electrode connected to a second clock terminal configured to receive the second clock signal; a third transistor connected between the second node and a first voltage terminal, the third transistor including a gate electrode connected to the first node; and a fourth transistor connected between a second voltage terminal and the second node, the fourth transistor including a gate electrode connected to the first node.
Thus, claim 4 is objected to.
Claims 5, 6 depend from and inherit limitations of claim 4.
Thus, claims 5, 6 are objected to.
Regarding claim 7, Kim in view of Yanagisawa discloses the scan driving circuit of claim 1.
The cited prior art fails to singularly or collectively disclose the circuit wherein the second inverter circuit includes: a first transistor connected between a first voltage terminal and an output terminal, the first transistor including a gate electrode connected to the first node, and the output terminal being configured to output the scan signal; a second transistor connected between the output terminal and a second voltage terminal, the second transistor including a gate electrode connected to the third node; a third transistor connected between the first voltage terminal and a carry output terminal, the third transistor including a gate electrode connected to the third node, and the carry output terminal being configured to output the carry output signal; and a fourth transistor connected between the carry output terminal and a third voltage terminal, the fourth transistor including a gate electrode connected to the third node.
Thus, claim 7 is objected to.
Claim 8 depends from and inherits limitations of claim 7.
Thus, claim 8 is objected to.
Regarding claim 9, Kim in view of Yanagisawa discloses the scan driving circuit of claim 1.
The cited prior art fails to singularly or collectively disclose the circuit wherein the second inverter circuit includes: a first transistor connected between a first voltage terminal and an output terminal, the first transistor including a gate electrode connected to the first node, and the output terminal being configured to output the scan signal; a second transistor connected between the output terminal and a second voltage terminal, the second transistor including a gate electrode connected to the third node; a third transistor connected between the first voltage terminal and a carry output terminal, the third transistor including a gate electrode connected to the second node, and the carry output signal being configured to output the carry output signal; and a fourth transistor connected between the carry output terminal and a third voltage terminal, the fourth transistor including a gate electrode connected to the second node.
Thus, claim 9 is objected to.
Claim 10 depends from and inherits limitations of claim 9.
Thus, claim 10 is objected to.
Regarding claim 11, Kim in view of Yanagisawa discloses the scan driving circuit of claim 1.
The cited prior art fails to singularly or collectively disclose the circuit wherein the second inverter circuit includes: a first transistor connected between a first voltage terminal and an output terminal, the first transistor including a gate electrode connected to the first node, and the output terminal being configured to output the scan signal; a second transistor connected between the output terminal and a first clock terminal, the second transistor including a gate electrode connected to the third node, and the first clock terminal being configured to receive the first clock signal; a third transistor connected between the first voltage terminal and a carry output terminal, the third transistor including a gate electrode connected to the third node, and the carry output terminal being configured to output the carry output signal; and a fourth transistor connected between the carry output terminal and a second voltage terminal, the fourth transistor including a gate electrode connected to the third node.
Thus, claim 11 is objected to.
Claim 12 depends from and inherits limitations of claim 11.
Thus, claim 12 is objected to.
Device claim 16 recites limitations similar to those recited in circuit claim 4.
Thus, device claim 16 is objected to.
Regarding claim 17, Kim in view of Yanagisawa discloses the electronic device of claim 13.
The cited prior art fails to singularly or collectively disclose the device wherein the second inverter circuit includes: a first transistor connected between a first voltage terminal and an output terminal, the first transistor including a gate electrode connected to the first node, and the output terminal being configured to output the scan signal; and a second transistor connected between the output terminal and a second voltage terminal, the second transistor including a gate electrode connected to the third node.
Thus, claim 17 is objected to.
Claim 18 depends from and inherits limitations of claim 17.
Thus, claim 18 is objected to.
Regarding claim 19, Kim in view of Yanagisawa discloses the electronic device of claim 13.
The cited prior art fails to singularly or collectively disclose the device wherein the second inverter circuit includes: a first transistor connected between a first voltage terminal and an output terminal, the first transistor including a gate electrode connected to the first node, and the output terminal being configured to output the scan signal; a second transistor connected between the output terminal and a second voltage terminal, the second transistor including a gate electrode connected to the third node; a third transistor connected between the first voltage terminal and a carry output terminal, the third transistor including a gate electrode connected to the second node, and the carry output terminal being configured to output a carry output signal; and a fourth transistor connected between the carry output terminal and a third voltage terminal, the fourth transistor including a gate electrode connected to the second node.
Thus, claim 19 is objected to.
Regarding claim 20, Kim in view of Yanagisawa discloses the electronic device of claim 13.
The cited prior art fails to singularly or collectively disclose the device wherein: the second inverter circuit includes: a first transistor connected between a first voltage terminal and an output terminal, the first transistor including a gate electrode connected to the first node, and the output terminal being configured to output the scan signal; a second transistor connected between the output terminal and a first clock terminal, the second transistor including a gate electrode connected to the third node, and the first clock terminal being configured to receive the first clock signal; a third transistor connected between the first voltage terminal and a carry output terminal, the third transistor including a gate electrode connected to the third node, and the carry output terminal being configured to output a carry output signal; and a fourth transistor connected between the carry output terminal and a second voltage terminal, the fourth transistor including a gate electrode connected to the third node.
Thus, claim 20 is objected to.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure follows:
Kim et al. (2022/0375412; Figure 7A) and Ji et al. (2023/0075449; Figure 5) provide relevant teaching of shift register circuitry.
Inquiries
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Aaron Midkiff whose telephone number is (571)270-5875. The examiner can normally be reached Monday - Friday, 8:00am - 4:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amr Awad can be reached at (571)272-7764. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/AARON MIDKIFF/
Examiner, Art Unit 2621
/AMR A AWAD/Supervisory Patent Examiner, Art Unit 2621
1 Deemed to be among known related technologies omitted by Kim [0023]; amounting to an inherent feature by which the system is rendered inoperable; please see evidentiary reference Chang (2019/0130832) | Figure 1: Comprising 110, 120; [0042], [0043].
2 x = placeholder for illustrated 1, 2, 3 identifying respective ones among gate lines.
Prosecution Insights