DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priorities
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. KR10-2024-0202554, filed on 12/31/2024.
Information Disclosure Statement
The information disclosure statements filed 12/22/2025 has been acknowledged and considered by the examiner. An initialed copy of the PTO-1449 is included in this correspondence.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5-6, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US Pub. 2013/0088417 A1).
Regarding claim 1; Kim teaches a display device (a display device 100, Fig.1) comprising:
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(Fig.2 of Kim reproduced)
a display panel (a display panel 110, Fig. 1) comprising a pixel (a pixel SP, Fig. 1), the pixel (Fig. 2) comprising:
a light-emitting element (an OLED, Fig. 2) comprising an anode and a cathode (Fig. 2);
a first transistor (a driving transistor Tdr, Fig. 2) connected between a first power line (VDD) and the anode (an anode of the OLED, para. [0050]), and configured to operate according to a potential of a first node (para. [0038, 0048 and 0051], the first capacitor C1 may be a sensing capacitor that is connected between the first node N1 and a third node N3 and used to sense the threshold voltage "Vth" of the driving transistor Tdr and a gate terminal of the driving transistor Tdr is connected to a third node N3. The driving transistor Tdr may adjust the amount of a current flowing in the OLED according to a voltage applied to the third node N3 corresponding to the gate terminal of the driving transistor Tdr. The voltage applied to the third node N3 is higher by a threshold voltage "Vth" of the driving transistor T5 than the data voltage Vdata. Therefore, the amount of the current flowing in the OLED is proportional to the level of the data voltage Vdata);
a second transistor (a first transistor T1, Fig. 2) connected between the first node (first node N1, Fig. 2) and a data line (a data line supplies a data voltage Vdata, Fig. 2), and configured to receive a first scan signal (a scan signal SCAN, Fig. 2);
a third transistor (a fifth transistor T5, Fig. 2) connected between a second node (a second node N2, Fig.2) and a reference voltage line (a reference voltage Vref, Fig. 2), and configured to receive the first scan signal (the scan signal Scan, Fig. 2);
a fourth transistor (a fourth transistor T4, Fig. 2) connected between the second node (the second node N2, Fig.2) and an initialization voltage line (an initialization voltage Vinitial, Fig. 2), and configured to receive a second scan signal (an initialization signal Initial, Fig. 2); and
a storage capacitor (a second capacitor C2, Fig. 2) connected between the first node and the second node (Fig. 2, the second capacitor C2 is connected between the first node N1 and the second node N2).
Regarding claim 2; Kim teaches the display device of claim 1 as discussed above. Kim further teaches wherein, during a data write period (Fig. 3, para. [0070], a data application time period t3), the first scan signal is configured to have an active level (Fig. 3, in the time period t3, the scan signal Scan is high level), and the second scan signal is configured to have an inactive level (Fig. 3, in the time period t3, the initialization signal Initial is low level), and wherein, during an initialization period following the data write period (Fig. 3, in a next frame, an initialization time period t1 following the data application time period t3), the first scan signal is configured to have the inactive level, and the second scan signal is configured to have the active level (Fig. 3, in the initialization time period t3, the initialization signal Initial is high level and the scan signal Scan is low level).
Regarding claim 3; Kim teaches the display device of claim 2 as discussed above. Kim further teaches wherein, during the data write period, the first node is configured to receive a data voltage, and the second node is configured to be initialized with a reference voltage from the reference voltage line (Figs.2 and 3 and [0037, 0046] during the data application time period t3, the scan signal Scan is high level. Accordingly, the first node N1 receives a data voltage Vdata, and the second node N2 receives a reference voltage Vref).
Regarding claim 5; Kim teaches the display device of claim 2 as discussed above. Kim further teaches the cathode of the light-emitting element is connected to a second power line configured to receive a second driving voltage (Fig. 2, the cathode of the OLED is connected to a low-level power supply voltage VSS); wherein the reference voltage line is configured to receive a reference voltage having a higher voltage level than that of the second driving voltage (para. [0042], the reference voltage Vref may be from -5V to 5V. Para. [0054], the low-level power supply voltage VSS may be from 0V to 5V. Therefore, the reference voltage Vref may be higher than the low-level power supply voltage VSS. For example, the reference voltage may be 5V and the low-level power supply voltage VSS may be 0V).
Regarding claim 6; Kim teaches the display device of claim 5 as discussed above. Kim further teaches the initialization voltage line is configured to receive an initialization voltage having a voltage level that is lower than or equal to that of the second driving voltage (para. [0044], the initial voltage Vinitial is lower than the threshold voltage of OLED, and, for example, may be -10V to 0V. Therefore, the initial voltage Vinitial is lower than the low-level power supply voltage VSS, which is from 0V to 5V [0054]).
Regarding claim 20; Kim teaches an electronic apparatus (a display device 100, Fig. 1) comprising:
a display module (a display panel 110) comprising a pixel (a pixel SP); and
a processor (a timing controller 120) configured to drive the display module (para. [0029]), wherein the pixel (the pixel SP, Fig. 2) comprises:
a light-emitting element (an OLED, Fig. 2) comprising an anode and a cathode (Fig. 2);
a first transistor (a driving transistor Tdr, Fig. 2) connected between a first power line (VDD) and the anode (an anode of the OLED, para. [0050]), and configured to operate according to a potential of a first node (para. [0038,0048 and 0051], the first capacitor C1 may be a sensing capacitor that is connected between the first node N1 and a third node N3 and used to sense the threshold voltage "Vth" of the driving transistor Tdr and a gate terminal of the driving transistor Tdr is connected to a third node N3. The driving transistor Tdr may adjust the amount of a current flowing in the OLED according to a voltage applied to the third node N3 corresponding to the gate terminal of the driving transistor Tdr. The voltage applied to the third node N3 is higher by a threshold voltage "Vth" of the driving transistor T5 than the data voltage Vdata. Therefore, the amount of the current flowing in the OLED is proportional to the level of the data voltage Vdata);
a second transistor (a first transistor T1, Fig. 2) connected between the first node (first node N1, Fig. 2) and a data line (a data line supplies a data voltage Vdata, Fig. 2), and configured to receive a first scan signal (a scan signal SCAN, Fig. 2);
a third transistor (a fifth transistor T5, Fig. 2) connected between a second node (a second node N2, Fig.2) and a reference voltage line (a reference voltage Vref, Fig. 2), and configured to receive the first scan signal (the scan signal Scan, Fig. 2);
a fourth transistor (a fourth transistor T4, Fig. 2) connected between the second node (the second node N2, Fig.2) and an initialization voltage line (an initialization voltage Vinitial, Fig. 2), and configured to receive a second scan signal (an initialization signal Initial, Fig. 2); and
a storage capacitor (a second capacitor C2, Fig. 2) connected between the first node and the second node (Fig. 2, the second capacitor C2 is connected between the first node N1 and the second node N2).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 7-9, 11, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US Pub. 2013/0088417 A1) in view of Lee et al. (US Pub. 2026/0186601 A1).
Regarding claim 7; Kim teaches the display device of claim 2 as discussed above. Kim does not teach a first emission control transistor connected between the second node and the anode, and configured to receive a first emission control signal.
Lee teaches a first emission control transistor (a fifth transistor M5, Fig. 9) connected between the second node (a third node n3, Fig. 9) and the anode (an anode of a light emitting element EL, Fig. 9), and configured to receive a first emission control signal (Fig. 9, the fifth transistor M5 receives a second emission control signal EM2).
At the time of invention was effectively filed, it would have been obvious to one of ordinary skill in the art to modify the display device of Kim to include the teaching of Lee of providing a transistor connected between a third node and an anode of a light emitting element. The motivation would have been in order to reduce leakage current flowing through the light emitting element in a non-emission period.
Regarding claim 8; Kim in view of Lee teaches the display device of claim 7 as discussed above. Kim does not teach the first emission control signal is configured to have the inactive level during an inactive period, and is configured to have the active level during an active period, wherein the inactive period overlaps the data write period, and wherein the initialization period comprises a first initialization period overlapping the inactive period, and a second initialization period overlapping the active period.
Lee teaches the first emission control signal is configured to have the inactive level during an inactive period (Fig. 10, the emission signal EM2 is a low level VGL in an inactive period), and is configured to have the active level during an active period (Fig. 9, the emission signal EM2 is high level VGH in an active period), wherein the inactive period overlaps the data write period (Fig. 10, the inactive period of EM2 (i.e., EM2 is low level VGL) overlaps a data period when a scan signal SC1 is high level), and wherein the initialization period (Fig.10, a scan signal SC3 is high level in an initialization period) comprises a first initialization period overlapping the inactive period (Fig. 10, the initialization period overlaps the inactive period of the emission signal EM2), and a second initialization period overlapping the active period (Fig. 10, the initialization period overlaps the active period of the emission signal EM2).
At the time of invention was effectively filed, it would have been obvious to one of ordinary skill in the art to modify the display device of Kim to include the teaching of Lee of configuring timings of the emission signal in an initialization period, a data writing period, and . The motivation would have been in order to properly control the pixel circuit.
Regarding claim 9; Kim in view of Lee teaches the display device of claim 8 as discussed above. Kim teaches during the data write period (the data application period t3, Fig. 3), the first node is configured to receive a data voltage (Figs. 2 and 3, during the data application period t3, the scan signal SCAN is high level. Accordingly, the first transistor T1 is turned on so that the first node N1 receives a data voltage Vdata), and the second node is configured to be initialized with a reference voltage from the reference voltage line (Figs. 2 and 3, during the data application period t3, the fifth transistor T5 is turned on to apply a reference voltage Vref to the second node N2).
Regarding claim 11; Kim in view of Lee teaches the display device of claim 7 as discussed above. Kim does not teach a second emission control transistor connected between the first power line and the first transistor, and configured to receive a second emission control signal; and a hold capacitor connected between the second node and the first power line.
Lee teaches a second emission control transistor (a fourth transistor M4, Fig. 9) connected between the first power line and the first transistor (Fig. 9, the fourth transistor M4 is connected between a pixel driving voltage EVDD and a driving transistor M6), and configured to receive a second emission control signal (a first emission control signal EM1, Fig. 9); and a hold capacitor (a second capacitor CA, Fig. 9) connected between the second node and the first power line (Fig. 9, the second capacitor is connected between the third node n3 and the pixel driving voltage EVDD).
At the time of invention was effectively filed, it would have been obvious to one of ordinary skill in the art to modify the display device of Kim to include the teaching of Lee of providing the fourth transistor M4 and the second capacitor CA. The motivation would have been in order to prevent leakage current flowing through the light emitting element during a non-emission period; and to prevent loss of data voltage (Lee, para. [0115]).
Regarding claim 13; Kim teaches the display device of claim 1 as discussed above. Kim does not teach the first transistor, the second transistor, the third transistor, and the fourth transistor comprise an oxide semiconductor.
Lee teaches the first transistor, the second transistor, the third transistor, and the fourth transistor comprise an oxide semiconductor (para. [0048], the transistors can be implemented as an oxide TFT including oxide semiconductor).
At the time of invention was effectively filed, it would have been obvious to one of ordinary skill in the art to modify the display device of Kim to include the teaching of Lee of implementing transistors as oxide TFT including oxide semiconductor. The motivation would have been in order to reduce leakage current and to increase carrier mobility.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US Pub. 2013/0088417 A1) in view of Li et al. (US Pub. 2026/0188213 A1).
Regarding claim 12; Kim teaches the display device of claim 2 as discussed above. Kim does not teach the display panel is configured to display an image during driving frames comprising a write frame and at least one holding frame, wherein the write frame comprises the data write period and the initialization period, and wherein the holding frame does not comprise the data write period, and comprises the initialization period.
Li teaches the display panel is configured to display an image during driving frames comprising a write frame (Fig. 32, a refresh frame) and at least one holding frame (Fig. 32, a hold frame), wherein the write frame comprises the data write period (Figs. 31 and 32, during the refresh frame, a fourth transistor T4 is turned on to write a data voltage to a second node N2 in a data writing period) and the initialization period (Figs. 31 and 32, during the refresh frame, a seventh transistor T7 is turned on to apply an initialization voltage to a fourth node N4 in an initialization period), and wherein the holding frame does not comprise the data write period (Fig. 32, the hold frame does not include a data writing period during), and comprises the initialization period (Fig. 32, during the hold frame, the seventh transistor T7 is turned on in response to the fourth scan line signal S4).
At the time of invention was effectively filed, it would have been obvious to one of ordinary skill in the art to modify the display device of Kim to include the teaching of Li of driving a display device in a refresh frame and a hold frame. The motivation would have been in order to reduce power consumption.
Claims 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US Pub. 2013/0088417 A1) in view of Park et al. (US Pub. 2024/0257735 A1).
Regarding claim 14; Kim teaches a display device (a display device 100, Fig. 1) comprising:
a display panel comprising a pixel (a pixel SP, Fig. 1), the pixel (a pixel SP, Fig. 2) comprising:
a light-emitting element (an OLED) comprising an anode and a cathode (see Fig. 2, para. [0043, 0050, 0054, 0061, and 0067]);
a first transistor (a driving transistor Tdr) connected between a first power line (VDD) and the anode (the anode of OLED), and configured to operate according to a potential of a first node (para. [0038, 0048 and 0051], the first capacitor C1 may be a sensing capacitor that is connected between the first node N1 and a third node N3 and used to sense the threshold voltage "Vth" of the driving transistor Tdr and a gate terminal of the driving transistor Tdr is connected to a third node N3. The driving transistor Tdr may adjust the amount of a current flowing in the OLED according to a voltage applied to the third node N3 corresponding to the gate terminal of the driving transistor Tdr. The voltage applied to the third node N3 is higher by a threshold voltage "Vth" of the driving transistor T5 than the data voltage Vdata. Therefore, the amount of the current flowing in the OLED is proportional to the level of the data voltage Vdata);
a second transistor (a first transistor T1, Fig. 2) connected between the first node (first node N1, Fig. 2) and a data line (a data line Vdata), and configured to receive a first scan signal (a scan signal SCAN, Fig. 2);
a third transistor (a fifth transistor T5, Fig. 2) connected between a second node (a second node N2, Fig. 2) and a reference voltage line (a reference voltage line Vref, Fig.2), and configured to receive the first scan signal (the scan signal SCAN, Fig. 2);
a fourth transistor (a fourth transistor T4, Fig. 2) connected between the anode (an anode of the OLED, Fig. 2) and an initialization voltage line (an initialization voltage line Vinitial, Fig. 2), and configured to receive a second scan signal (a control signal Initial, Fig. 2); and
a storage capacitor (a second capacitor C2, Fig. 2) connected between the first node and the second node (Fig. 2, the second capacitor C2 is connected between the first node N1 and the second node N2).
Kim does not teach an emission control transistor connected between the second node and the anode, and configured to receive an emission control signal.
Park teaches an emission control transistor (a sixth transistor T6, Fig. 5) connected between the second node (a source node DTS, Fig. 5) and the anode (an anode of a light emitting element EL, Fig. 5), and configured to receive an emission control signal (Fig. 9, the sixth transistor T6 receives a second emission control signal EM2).
At the time of invention was effectively filed, it would have been obvious to one of ordinary skill in the art to modify the display device of Kim to include the teaching of Park of providing a transistor connected between a source node and an anode of a light emitting element. The motivation would have been in order to reduce leakage current flowing through the light emitting element in a non-emission period.
Regarding claim 15; Kim in view of Park teaches the display device of claim 14 as discussed above. Kim further teaches wherein, during a data write period (Fig. 3, para. [0070], a data application time period t3), the first scan signal is configured to have an active level (Fig. 3, in the time period t3, the scan signal Scan is high level), and the second scan signal is configured to have an inactive level (Fig. 3, in the time period t3, the initialization signal Initial is low level), and wherein, during an initialization period following the data write period (Fig. 3, in a next frame, an initialization time period t1 following the data application time period t3), the first scan signal is configured to have the inactive level, and the second scan signal is configured to have the active level (Fig. 3, in the initialization time period t3, the initialization signal Initial is high level and the scan signal Scan is low level).
Regarding claim 16; Kim in view of Park teaches the display device of claim 15 as discussed above. Kim does not teach the emission control signal is configured to have the inactive level during an inactive period, and is configured to have the active level during an active period, and wherein the inactive period overlaps the data write period and does not overlap the initialization period.
Park teaches the emission control signal is configured to have the inactive level during an inactive period (Fig. 6, the second emission control signal EM2 is low level (i.e., OFF)), and is configured to have the active level during an active period (Fig. 6, the second emission control signal EM2 is high level (i.e., ON)), and wherein the inactive period overlaps the data write period (Fig. 6, the inactive period of the second emission control signal EM2 overlaps the data writing period Pw (i.e., when a fourth scan signal SC4 is high level)) and does not overlap the initialization period (Fig. 6, the inactive period of the second emission control signal EM2 (i.e., OFF) does not overlap an initialization period Pi (i.e., when a second scan signal SC2 is high level). In other words, the source node DTS is initialized during an initialization period (i.e., the active period of the second emission control signal EM2). The source node DTS is not initialized during the inactive period of the second emission control signal EM2).
At the time of invention was effectively filed, it would have been obvious to one of ordinary skill in the art to modify the display device of Kim to include the teaching of Park of driving the emission transistor to be not overlapping an initialization period. The motivation would have been in order to reset the second node N2 to the initialization voltage Vinitial during the initialization period t1.
Regarding claim 17; Kim in view of Park teaches the display device of claim 16 as discussed above. Kim further teaches during the data write period, the first node is configured to receive a data voltage, and the second node is configured to be initialized with a reference voltage from the reference voltage line (Figs. 2 and 3, during the data application period t3, the first node N1 receives a data voltage Vdata, and the second node N2 receives a reference voltage Vref).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US Pub. 2013/0088417 A1) in view of Lee et al. (US Pub. 2026/0186601 A1) as applied to claim 15 above; further in view of Li et al. (US Pub. 2026/0188213 A1).
Regarding claim 19; Kim in view of Park teaches the display device of claim 15 as discussed above. Kim in view of Park does not teach the display panel is configured to display an image during driving frames comprising a write frame and at least one holding frame, wherein the write frame comprises the data write period and the initialization period, and wherein the holding frame does not comprise the data write period, and comprises the initialization period.
Li teaches the display panel is configured to display an image during driving frames comprising a write frame (Fig. 32, a refresh frame) and at least one holding frame (Fig. 32, a hold frame), wherein the write frame comprises the data write period (Figs. 31 and 32, during the refresh frame, a fourth transistor T4 is turned on to write a data voltage to a second node N2 in a data writing period) and the initialization period (Figs. 31 and 32, during the refresh frame, a seventh transistor T7 is turned on to apply an initialization voltage to a fourth node N4 in an initialization period), and wherein the holding frame does not comprise the data write period (Fig. 32, the hold frame does not include a data writing period during), and comprises the initialization period (Fig. 32, during the hold frame, the seventh transistor T7 is turned on in response to the fourth scan line signal S4).
At the time of invention was effectively filed, it would have been obvious to one of ordinary skill in the art to modify the display device of Kim and Park to include the teaching of Li of driving a display device in a refresh frame and a hold frame. The motivation would have been in order to reduce power consumption.
Allowable Subject Matter
Claims 4, 10, and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Prior art fails to teach that “during the initialization period, the second node is configured to be initialized with an initialization voltage from the initialization voltage line, and wherein a gate-source voltage of the first transistor during the initialization period is configured to be equal to the gate-source voltage of the first transistor during the data write period”.
Inquiries
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NGUYEN H TRUONG whose telephone number is (571)270-1630. The examiner can normally be reached M-F: 10-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached at 571-272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NGUYEN H TRUONG/Examiner, Art Unit 2623
/CHANH D NGUYEN/Supervisory Patent Examiner, Art Unit 2623
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