Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Drawings
The drawings filed 12-29-25 have been accepted by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-18, 38, and 40 of U.S. Patent No. 12,542,077. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of U.S. Patent No. 12,542,077 encompasses all the claim limitation of pending claims 1-20 of the Instant Application.
Pending Claim 1 of the Instant Application
Claim 1 of Patent 12,542,077
A display device comprising:
A display device comprising:
a first pixel and a second pixel in a display area of the display device, each of the first pixel and the second pixel including a transistor and a light emitting diode;
a first pixel, a second pixel and a third pixel in a display area of the display device, each of the first pixel and the second pixel including a transistor and a light emitting diode;
a first signal line electrically connected to the first pixel and extended in a first direction;
a first signal line electrically connected to the first pixel and extended in a first direction;
a second signal line electrically connected to the second pixel and spaced apart from the first signal line and extended in the first direction;
a second signal line electrically connected to the second pixel and spaced apart from the first signal line and extended in the first direction;
a first wire electrically connected to the first signal line;
a first wire electrically connected to the first signal line;
a second wire electrically connected to the second signal line and extended in the first direction; and
a second wire electrically connected to the second signal line and extended in the first direction; and
a connecting wire electrically connecting the second signal line to the second wire,
a connecting wire electrically connecting the second signal line to the second wire,
wherein the connecting wire comprises a first section and a second section,
wherein the connecting wire comprises a first section and a second section,
wherein the second section of the connecting wire is directly connected to the first section of the connecting wire and overlaps the first signal line,
wherein the second section of the connecting wire is directly connected to the first section of the connecting wire and overlaps the first signal line,
wherein the second section of the connecting wire extends in a second direction different from the first direction, and
wherein the second section of the connecting wire extends in a second direction different from the first direction,
wherein the first section of the connecting wire overlaps the third pixel, and
wherein the first section of the connecting wire overlaps a gate electrode of the transistor of the first pixel.
wherein the first section of the connecting wire overlaps a gate electrode of the transistor of the first pixel.
Pending Claim 19 of the Instant Application
Claim 39 of Patent 12,542,077
An electronic device comprising:
An electronic device comprising:
a display device;
a display device;
wherein the display device comprises:
wherein the display device comprises:
a first pixel and a second pixel in a display area of the display device, each of the first pixel and the second pixel including a transistor and a light emitting diode;
a first pixel, a second pixel and a third pixel in a display area of the display device, each of the first pixel and the second pixel including a transistor and a light emitting diode;
a first signal line electrically connected to the first pixel and extended in a first direction;
a first signal line electrically connected to the first pixel and extended in a first direction;
a second signal line electrically connected to the second pixel and spaced apart from the first signal line and extended in the first direction;
a second signal line electrically connected to the second pixel and spaced apart from the first signal line and extended in the first direction;
a first wire electrically connected to the first signal line;
a first wire electrically connected to the first signal line;
a second wire electrically connected to the second signal line and extended in the first direction; and
a second wire electrically connected to the second signal line and extended in the first direction; and
a connecting wire electrically connecting the second signal line to the second wire,
a connecting wire electrically connecting the second signal line to the second wire,
wherein the connecting wire comprises a first section and a second section,
wherein the connecting wire comprises a first section and a second section,
wherein the second section of the connecting wire is directly connected to the first section of the connecting wire and overlaps the first signal line,
wherein the second section of the connecting wire is directly connected to the first section of the connecting wire and overlaps the first signal line,
wherein the second section of the connecting wire extends in a second direction different from the first direction, and
wherein the second section of the connecting wire extends in a second direction different from the first direction,
wherein the first section of the connecting wire overlaps the third pixel, and
wherein the first section of the connecting wire overlaps a gate electrode of the transistor of the first pixel.
wherein the first section of the connecting wire overlaps a gate electrode of the transistor of the first pixel.
Additionally, claims 2-18, and 20 of the instant application are rejected as being recited similarly to claims 2-17, 19, and 40, respectively, of Patent 12,542,077.
Allowable Subject Matter
Claims 1-20 would be allowable if a terminal disclaimer were filed or the claims were rewritten or amended to overcome the double patenting rejection set forth in this Office action.
The following is an examiner’s statement of reasons for allowance:
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Regarding claim 1, Zhang et al. (US 2019/0237487) discloses (Fig. 8, 10, 11, 13, and 14, with Fig. 10 shown modified above) a display device comprising:
a first pixel (corresponding to element 4, labelled P1 in the modified Fig. 10 above, see also “4 corresponds to the reflection area of the opening of the sub-pixel” discussed in [0035]), a second pixel (P2), and a third pixel (P3) in a display area of the display device (the pixels themselves correspond to the display area), each of the first pixel and the second pixel including a transistor (18, seen in Fig. 14);
a first signal line (corresponding to the “data lines” of element 5, labelled S1 in the modified Fig. 10 above, see “the first signal line 5 includes a data line” discussed in [0031]) electrically connected to the first pixel (“driving signals are transmitted to the first signal lines 5 through the second signal lines 6, and are further transmitted to corresponding sub-pixels, so as to drive the sub-pixels to emit light” discussed in [0031], while Fig. 8 and 14 show that the pixels are connected to the data line disposed on the left hand side) and extended in a first direction (vertically);
a second signal line (S2) electrically connected to the second pixel (similarly to above, S2 will be the data line for the second pixel P2) and spaced apart from the first signal line and extended in the first direction (S2 is separated to the left of S1 and also runs vertically, as seen in Fig. 10);
a first wire (the portion 62 that supplies signals to S1 from 3, labelled W1 in the modified Fig. 10 above, corresponding only to the region outside the display area as seen in Fig. 13) electrically connected to the first signal line (as seen in Fig. 10);
a second wire (similarly, the portion 62 that supplies signals to S2, labelled W2) electrically connected to the second signal line (via CW) and extended in the first direction (62 extends upwards vertically from 3 towards the display area, see also [0032]); and
a connecting wire (the horizontal and vertical wire, labeled CW) electrically connecting the second signal line to the second wire (CW connects W2 on the bottom to S2 on the left),
wherein the connecting wire comprises a first section and a second section (seen in Fig. 11, corresponding to sections 61 and 64, respectively),
wherein the second section of the connecting wire (64) is directly connected to the first section of the connecting wire (61 and 64 are directly connected via a through-hole 15, similarly to as seen in Fig. 12) and overlaps the first signal line (as seen in Fig. 11, 64 overlaps the adjacent data line, corresponding to S1),
wherein the second section of the connecting wire extends in a second direction different from the first direction (64 extends in a horizontal direction as seen in Fig. 11), and
wherein the first section of the connecting wire overlaps the third pixel (seen in Fig. 10 and 11, 64 overlaps the third pixel P3 that is immediately to the right of the second pixel P2).
However, while Zhang teaches the active layer (182) of the transistor is overlapped with element 4 (seen in Fig. 14, 182 is directly below a portion of 4), and that the first section of the connecting wire also overlaps element 4 (for example, as seen in Fig. 11), element 4 is a “reflective layer portion (see [0032]) and so Zhang fails to teach or suggest specifically wherein the first section of the connecting wire overlaps a gate electrode of the transistor of the first pixel.
Zhang also fails to teach or suggest wherein each of the first pixel and the second pixel include a light emitting diode.
Lin et al. (US 2018/0204895) discloses (Fig. 2-4 and 31) a display device wherein a first section of a connecting wire (the vertical section of 170) is inside the pixel area of the display (“170 may be formed in the active area of display 14” as discussed in [0078]), but Lin fails to teach or suggest wherein the first section of the connecting wire specifically overlaps any elements of the pixels, including a gate electrode of a transistor (further, Fig. 4 and Fig. 6 both show wiring inside the display area that is routed around pixels in order to not overlap with them).
Dong et al. (US 2018/0108310) (Fig. 3), Fujikawa (US 2015/0356937) (Fig. 5 and 6), and Jung (US 2014/0117320) (Fig. 1 and 4) each disclose a display device with a signal line that has a signal wire and connecting wire, but still fail to teach or suggest wherein the connecting wires overlaps any elements of the pixels, including a gate electrode of a transistor.
Therefore, each of the currently cited references of record fails to teach or suggest “wherein the first section of the connecting wire overlaps a gate electrode of the transistor of the first pixel” when combined with each of the other claim limitations.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONATHAN M BLANCHA whose telephone number is (571)270-5890. The examiner can normally be reached Monday to Friday, 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached at 5712727772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JONATHAN M BLANCHA/Primary Examiner, Art Unit 2623
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