DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 8 and 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ikeda (USPGPUB 2013/0222440—hereinafter “Ikeda”).
As to Claim 1, Ikeda teaches an internal compensation pixel driving circuit (See Fig. 1), comprising: a light-emitting control subcircuit (Fig. 1 at Tr5), a compensation subcircuit (Tr4), a driving subcircuit (D-Tr), a reset subcircuit (Tr3), a first writing subcircuit (Tr1 + C1), a second writing subcircuit (Tr2) and a light-emitting component (EL);
wherein the compensation subcircuit (Tr4), the light-emitting control subcircuit (Fig. 1 at Tr5) and a first terminal of the driving subcircuit (D-Tr) are connected to a fourth node (node connecting Tr5, Tr4 and D-Tr),
the compensation subcircuit (Tr4), the first writing subcircuit (Tr1 + C1) and a gate of the driving subcircuit (D-Tr) are connected to a second node (node at Vg),
the reset subcircuit (Tr3), the light-emitting component (EL) and a second terminal of the driving subcircuit (D-Tr) are connected to a third node (node at Va), and
the second writing subcircuit (Tr2) and the first writing subcircuit (Tr1 + C1) are connected to a first node (node at left side of C1); and
the driving subcircuit provides a driving current for the light-emitting component (Pg. 2, ¶ 25), and the compensation subcircuit is used to eliminate an influence of a threshold voltage of the driving subcircuit on a light-emitting current provided by the light-emitting component (Pg. 1, ¶ 9, Pg. 2, ¶ 12, Pg. 4, ¶’s 54 and 56).
As to Claim 8, all of the claim limitations have been met with respect to claim 1 (see above) with the exception of a display panel comprising the internal compensation pixel driving circuit. Ikeda teaches a display panel comprising the internal compensation pixel driving circuit (Pg. 1, ¶ 2 and Fig. 7 at 13).
As to Claims 2 and 9, Ikeda teaches that the driving subcircuit is an oxide N-type thin film transistor (Pg. 5, claim 7).
Allowable Subject Matter
Claims 15-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: As to Claim 15, the prior art of record fails to teach or suggest, either alone or in combination, “A driving method of an internal compensation pixel driving circuit, wherein the internal compensation pixel driving circuit comprises: a light-emitting control subcircuit, a compensation subcircuit, a driving subcircuit, a reset subcircuit, a first writing subcircuit, a second writing subcircuit and a light-emitting component; wherein the compensation subcircuit, the light-emitting control subcircuit and a first terminal of the driving subcircuit are connected to a fourth node, the compensation subcircuit, the first writing subcircuit and a gate of the driving subcircuit are connected to a second node, the reset subcircuit, the light-emitting component and a second terminal of the driving subcircuit are connected to a third node, and the second writing subcircuit and the first writing subcircuit are connected to a first node; and the driving subcircuit provides a driving current for the light-emitting component, and the compensation subcircuit is used to eliminate an influence of a threshold voltage of the driving subcircuit on a light-emitting current provided by the light-emitting component; wherein the internal compensation pixel driving circuit further comprises: a data terminal connected to the first writing subcircuit; a first control terminal connected to a gate of the reset subcircuit; a second control terminal connected to a gate of the first writing subcircuit and a gate of the compensation subcircuit; a third control terminal connected to a gate of the second writing subcircuit; a fourth control terminal connected to a gate of the light-emitting control subcircuit, wherein the driving method comprises following stages: in a first stage, inputting a high-level signal to the first control terminal and the second control terminal, inputting a low-level signal to the third control terminal and the fourth control terminal, the compensation subcircuit and the first writing subcircuit being in a conducting state, and transmitting a data signal of the data terminal to the first node; in a second stage, inputting a high-level signal to the first control terminal and the third control terminal, inputting a low-level signal to the second control terminal and the fourth control terminal, the second writing subcircuit and the reset subcircuit being in a conducting state, and writing a data signal to the second node; and in a third stage, inputting a high-level signal to the third control terminal and the fourth control terminal, inputting a low-level signal to the first control terminal and the second control terminal, the second writing subcircuit and the light-emitting control circuit being in a conducting state, controlling a working state of the driving subcircuit by a data signal, and driving the light-emitting component to emit light.” (As claimed, emphasis added)
Claims 16-20 depend upon claim 15 and thus are also allowed.
Claims 3-7 and 10-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. As to Claims 3 and 10, the prior art of record fails to teach or suggest, either alone or in combination, “a data terminal connected to the first writing subcircuit; a first control terminal connected to a gate of the reset subcircuit; a second control terminal connected to a gate of the first writing subcircuit and a gate of the compensation subcircuit; a third control terminal connected to a gate of the second writing subcircuit; a fourth control terminal connected to a gate of the light-emitting control subcircuit.” (As claimed, emphasis added)
Claims 4-6 and 11-13 depend upon claims 3 and 10, respectively and thus are also objected.
As to Claims 7 and 14, the prior art of record fails to teach or suggest, either alone or in combination, “a reset circuit, wherein the reset circuit is connected to the fourth node.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Wang et al. USPGPUB 2012/0306843 (Figs. 2-7)
Liu et al. USPGPUB 2015/0294624 (Fig. 2)
Tseng et al. USPGPUB 2016/0217741 (Fig. 3)
Wang USPGPUB 2022/0310009 (Figs. 4A-4B)
Inquiries
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RODNEY AMADIZ whose telephone number is (571)272-7762. The examiner can normally be reached Mon - Thurs; 9AM - 5PM EST.
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/RODNEY AMADIZ/Primary Examiner, Art Unit 2622
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