1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
SUMMARY
2. The application filed on January 12, 2026, has been received and made of record. There are 1-21 claims in the application of which claims 1, 14, and 21 are independent claims. claims 2-13 and 15-20 are dependent claims. Therefore, claims 1-21 are pending for consideration.
Information Disclosure Statement
3. The information disclosure statement(IDS) submitted was filed along with the mailing date of the application on January 12, 2026. The IDS submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
6. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
6. Claims 1-6, 10, 14-17, 19, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over HAN(US 2016/0203759 A1) in view of Na(US 2016/0155379 A1).
Regarding claim 14, HAN teaches a display device(display apparatus 100, fig.1, Para-31) comprising:
a controller(control unit 140, fig.1) which receives an on-operation signal from a processor(obvious to receive image data and starting signal from external sources) and outputs a control signal based on the on-operation signal(control signals, Para-38);
a driving circuit(data driving unit 130, scan driving unit 120, fig.1) which receives the control signal(scan control signal SCS, data control signal DCS, Para-38) and comprises a plurality of stages(cascaded scan drivers are well-known in the art and it is obvious in the current display technology) that sequentially output scan signals(Para-52, 65);
at least one gate signal supply line(SCS, fig.1) which receives the control signal(SCS) and outputs at least one gate signal (S1, Sn, GW, GE, GR, fig.1, Para-52, 53, 56); and
a plurality of pixels(pixels P, fig.1, Para-32, 35),
wherein each of the plurality of pixels(P) comprises:
a first transistor(third transistor M3, fig.2, Para-47) comprising a gate(terminal connected to second node N2), a first terminal connected to a driving voltage line(first power ELVDD), and a second terminal(terminal connected to third node N3, Para-47);
a second transistor(fifth transistor M5, fig.2, Para-49) connected to a data line(data) and comprising a gate connected to a scan line(Sn, Para-49) to which a scan signal of the scan signals output by the driving circuit(120, Para-49) is input;
a third transistor(fourth transistor M4, fig.2, Para-48) connected to the second transistor(M5) and a first node(second node N2) to which the gate of the first transistor(M3) is connected, wherein the third transistor comprises a gate connected to a first gate line(write control signal GW, fig.2, Para-48) ;
a fourth transistor( first transistor M1, fig.2, Para-45) connected to the data line(data) and a second node(first node N1) and comprising a gate connected to a second gate line(reset control signal GR, fig.2, Para-45);
a fifth transistor(second transistor M2, fig.2, Para-46) connected to the first node(N2) and the second node(N1) and comprising a gate connected to a third gate line(emission control signal GE, fig.2, Para-46);
[a sixth transistor connected to a third node to which the second terminal of the first transistor is connected and a light-emitting element, wherein the sixth transistor comprises a gate connected to a fourth gate line;
a seventh transistor connected to the sixth transistor and an initialization voltage line and comprising a gate connected to a fifth gate line];
a first capacitor(first capacitor Cst, figs.2&4, Para-50) connected to the second node(N1) and the third node(third node N3, Para-50); and
a second capacitor(second capacitor Chold, fig.2&4, Para-50, 73) connected to a fourth node(forth node N4, figs.2&4, Para-50, 73) to which the second transistor(M5) and the third transistor (M4) are connected and the initialization voltage line (reference power source, Vref), and
wherein the at least one gate signal supply line(scan driving unit 120) supplies a gate signal to each of the first gate line, the second gate line, the third gate line, the fourth gate line, and the fifth gate line(S1, Sn, GW, GE, GR, fig.1, Para-52, 53, 56).
Nevertheless, HAN is not found to teach the display device, comprising: a sixth transistor connected to a third node to which the second terminal of the first transistor is connected and a light-emitting element, wherein the sixth transistor comprises a gate connected to a fourth gate line; a seventh transistor connected to the sixth transistor and an initialization voltage line and comprising a gate connected to a fifth gate line.
However, Na teaches an organic light emitting display device, comprising:
a controller(control unit 120, fig.1, Para-49) which receives an on-operation signal(control signal CS, fig.1, Para-52) from a processor(Para-52) and outputs a control signal based on the on-operation signal(control signals, Para-52);
a sixth transistor(seventh transistor TR7, figs.4&6-11, Para-69) connected to a third node(sixth node N6) to which the second terminal of the first transistor(second transistor TR2) is connected and a light-emitting element(organic light emitting element EL, fig.4, Para-66), wherein the sixth transistor(TR7) comprises a gate connected to a fourth gate line(light emission control signal EM, fig.4, Para-70); and
a seventh transistor(sixth transistor TR6, fig.4, Para-68) connected to the sixth transistor(TR7) and an initialization voltage line(initialization voltage Vinit, Para-65) and comprising a gate connected to a fifth gate line(first control signal C01, fig.4, Para-69).
The prior art, as embodied in the teachings of HAN and Na, included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference. One of ordinary skill in the art could have combined the elements as claimed by known methods and in that combination each element merely performs the same function as it does separately. Such combination is desirable as it provides a display device comprising organic light emitting diode having characteristics of sufficiently ensuring a compensating time and a demultiplexing time of a threshold voltage.
Regarding claim 15, HAN as modified by Na teaches the display device of claim 14, wherein:
a first terminal of the seventh transistor is connected to a fifth node(seventh node N7, fig.4, Para-68, Na), and a second terminal of the seventh transistor is connected to the initialization voltage line(initialization voltage Vinit, Para-65, Na), wherein the sixth transistor(TR7) and a pixel electrode(anode of EL) of the light-emitting element(EL) are connected to the fifth node(N7),
a first gate signal is input to the first gate line(write control signal GW, fig.2, Para-48, HAN),
a second gate signal is input to the second gate line(reset control signal GR, fig.2, Para-45, HAN) and the fifth gate line(first control signal C01, fig.4, Para-69, NA), and
a third gate signal is input to the third gate line(emission control signal GE, fig.2, Para-46, HAN) and the fourth gate line (light emission control signal EM, fig.4, Para-70, Na).
Regarding claim 16, HAN as modified by Na teaches the display device of claim 15, wherein:
during a first period(reset period, fig.3, HAN) of a frame:
the first gate signal(GW, fig.3, HAN) and the scan signal(Sn) have a gate-off voltage(logic low level),
the second gate signal(GR) and the third gate signal(GE, fig.3, HAN) have a gate-on voltage(logic high level),
the gate of the first transistor(M3) is initialized to a first voltage which is input to the data line(Para-53, HAN), and
a pixel electrode(anode) of the light-emitting element is initialized to an initialization voltage which is input to the initialization voltage line(Para-77, Na),
during a second period(threshold voltage compensation Vth, fig.3, HAN) subsequent to the first period(reset) of the frame:
the first gate signal(GW) and the second gate signal(GR) have a gate-on voltage(logic high level, fig.3, HAN),
the scan signal(Sn) and the third gate signal(GE) have a gate-off voltage(logic low level, fig.3, HAN),
a data voltage stored in the second capacitor(Chold) is provided to the gate of the first transistor(M3, fig.2, Para-57, HAN), and
a second voltage which is input to the data line is provided to the second node(N1, fig.3, Para-58, 59, HAN), and
during a third period(emission period) subsequent to the second period(Vth compensation) of the frame:
the first gate signal(GW) and the second gate signal(GR) have a gate-off voltage(logic low level, fig.3, HAN),
the third gate signal(GE) has a gate-on voltage(logic high level, fig.3, HAN), and
the light-emitting element emits light at brightness corresponding to the data voltage provided to the gate of the first transistor(Para-61, HAN),
wherein during a portion of the third period, the scan signal has a gate-on voltage(Sn is at high logic level, fig.3, HAN), and a data voltage(data) which is associated with a next frame and input to the data line is provided to the fourth node(N3, fig.3, HAN; Para-73, Na).
Regarding claim 17, HAN as modified by Na teaches the display device of claim 14, wherein:
a first terminal of the seventh transistor is connected to a fifth node(seventh node N7, fig.4, Para-68, Na), and a second terminal of the seventh transistor is connected to the initialization voltage line(initialization voltage Vinit, Para-65, Na),
a first gate signal is input to the first gate line(write control signal GW, fig.2, Para-48, HAN),
a second gate signal is input to the fifth gate line(reset control signal GR, fig.2, Para-45, HAN) and the fifth gate line(first control signal C01, fig.4, Para-69, NA),
a third gate signal is input to the third gate line(emission control signal GE, fig.2, Para-46, HAN) and the fourth gate line (light emission control signal EM, fig.4, Para-70, Na), and
a fourth gate line is input to the second gate line(light emission control signal EM, fig.4, Para-70, Na).
Regarding claim 19, HAN as modified by Na teaches the display device of claim 14, wherein:
a first terminal of the seventh transistor is connected to a fifth node(seventh node N7, fig.4, Para-68, Na), and a second terminal of the seventh transistor is connected to the initialization voltage line(initialization voltage Vinit, Para-65, Na), wherein the sixth transistor(TR7) and a pixel electrode(anode of EL) of the light-emitting element(EL) are connected to the fifth node(N7),
a first gate signal is input to the first gate line(write control signal GW, fig.2, Para-48, HAN),
a second gate signal is input to the second gate line(reset control signal GR, fig.2, Para-45, HAN) and the fifth gate line(first control signal C01, fig.4, Para-69, NA),
a third gate signal is input to the third gate line(emission control signal GE, fig.2, Para-46, HAN) and the fourth gate line (light emission control signal EM, fig.4, Para-70, Na), and
a fourth gate line is input to the second gate line(light emission control signal EM, fig.4, Para-70, Na).
Claim 21 is rejected for the same reason as mentioned in the rejection of claim 14, since both claims 14 and 21 recite identical claim limitations with minor change in wording and terminology in preamble.
Claim 1 is rejected for the same reason as mentioned in the rejection of claim 14, since both claims 1 and 14 recite identical claim limitations except broader limitations in claim 1.
Claim 2 is rejected for the same reason as mentioned in the rejection of claim 15, since both claims 2 and 15 recite identical claim limitations except different pre-amble.
Claims 3-5 are rejected for the same reason as mentioned in the rejection of claim 16, since claims 3-5 recite identical claim limitations, in combination, as recited in claim 16.
Claim 6 is rejected for the same reason as mentioned in the rejection of claim 17, since both claims 6 and 17 recite identical claim limitations except different pre-amble.
Claim 10 is rejected for the same reason as mentioned in the rejection of claim 19, since both claims 10 and 19 recite identical claim limitations except different pre-amble.
Allowable Subject Matter
7. Claims 7-9, 11-13, 18, and 20 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
8. The following is a statement of reasons for the indication of allowable subject matter:
Claims 7 and 11: None of the prior arts, on record, taken alone or in combination, provides a reasonable motivation and/or reasoning to fairly teach or suggest the applicant’s claimed invention, “----, wherein during a first period of a frame: the first gate signal and a scan signal which is input via the scan line have a gate-off voltage, the second gate signal, the third gate signal, and the fourth gate signal have a gate-on voltage, the gate of the first transistor is initialized to a first voltage which is input to the data line, and a pixel electrode of the light-emitting element is initialized to an initialization voltage which is input to the initialization voltage line”.
Claims 8, 9, 12 and 13 are objected to because of their dependency on the objected base claims respectively.
Claims 18 and 20 are objected to because of identical claim limitations, in combination, as recited in claims 7-9 and 11-13 respectively.
Examiner Note
9. The Examiner cites particular figures, paragraphs, columns and line numbers in the references, as applied to the claims above. Although the particular citations are representative teachings and are applied to specific limitations within the claims, other passages, internally cited references, and figures may also apply. In preparing a response, it is respectfully requested that the Applicant fully consider the references, in their entirety, as potentially disclosing or teaching all or part of the claimed invention, as well as fully consider the context of the passage as taught by the references or as disclosed by the Examiner.
Contact
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MD SAIFUL A SIDDIQUI whose telephone number is (571)270-1530. The examiner can normally be reached Mon-Fri: 9:00AM - 5:30PM.
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/MD SAIFUL A SIDDIQUI/Primary Examiner, Art Unit 2626
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