Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Alternatively, claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Independent claims 1 and 14 recite, inter alia:
a gate driver which provides a first gate signal and a second gate signal shifted by 1/3 horizontal time interval of the first gate signal
a second selection signal shifted by 1/3 horizontal time interval of the first selection signal
a third selection signal shifted by 1/3 horizontal time interval of the second selection signal
claims 8 and 19 recites, inter alia:
each of the first gate signal and the second gate signal has a pulse having a width corresponding to 2/3 horizontal time interval
claims 9 and 20 recites, inter alia:
each of the first selection signal, the second selection signal, and the third selection signal has a pulse having a width corresponding to 1/3 horizontal time interval
claim 10 recites; inter alia:
wherein the gate driver provides the first gate signal, the second gate signal, and a third gate signal shifted by 1/3 horizontal time interval of the second gate signal to the first gate line, the second gate line, and the third gate line, respectively.
claim 13 recites, inter alia:
wherein each of the first gate signal, the second gate signal, and the third gate signal has a pulse having a width corresponding to one horizontal time interval, and wherein the pulse of the first gate signal, the pulse of the second gate signal, and the pulse of the third gate signal partially overlap each other
It is noted that the use of term of horizontal time interval, with or without additional modifier (such as 1/3 horizontal time interval of first selection signal vs 1/3 horizontal time interval of first gate signal) throughout independent or dependent claims, are inconsistent, indefinite and lack clear written description from specification.
Reviewing originally filed specification, it appears that fig. 3 defines a specific horizontal time length as one horizontal time interval 1HP:
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It is noted that the time length defined as one horizontal time interval via drawings is not horizontal time interval of either gate line signal G or selection signal CL, instead, one horizontal time interval appear to be equal to 1.5 x horizontal time length of a gate signal, and one horizontal time interval appear to be equal to 3 x horizontal time length of a selection signal.
It is also noted from the figure, each gate signal is shifted from previous gate signal by 1/2 of horizontal time length of the first gate signal (instead of “1/3 horizontal time length of the first gate signal”), and each selection signal is shifted from previous selection by one horizontal time length of the second selection signal (instead of “1/3 horizontal time length of the second selection signal) .
Independent claims 1 and 14 instead, however, claim that gate signal is shifted for 1/3 horizontal time interval of the first gate signal, and selection signal is shifted for 1/3 horizontal time interval of the second selection signal, both of which are not supported by disclosure of pending specification. In addition, claims introduce various terms of “horizontal time interval” without clear definition of what constitute one horizontal time interval.
Furthermore, while “horizontal time interval” terms are introduced in independent with added modifiers, such as “1/3 horizontal time interval of the first gate signal” and “1/3 horizontal time interval of the second selection signal”. The term “horizontal time interval” are referenced in dependent claims without modifier, such as “2/3 horizontal time interval” without pointing to which horizontal time interval it refers to, further adding indefiniteness to claims.
Claims 1, 8-10, 14, 19, and 20 are therefore rejected for lacking written description, or are at least indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor regards as the invention. For the purpose of this office action, horizontal time interval, horizontal time interval of gate signal, as well as horizontal time interval of selection signal are broadly interpreted as any segment of a time length within driving period of display device.
Claims 2-7, 11-13, and 15-18 are rejected for dependency on rejected independent claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 9, 10, 12-14, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Tang et al., WO 2025255762 A1 (hereinafter “Tang”), in view of Ryu et al., US 20080055304 A1, and in further view of Oh et al., US 20120139892 A1 (hereinafter “Oh”).
Regarding claim 1, Tang discloses a display device comprising (Tang, pg. 6, ln. 28 – pg. 7, ln. 3, display device with display area 10, “the liquid crystal display includes an array substrate and a color filter substrate arranged opposite each other, with liquid crystal disposed between the array substrate and the color filter substrate. During display driving, gate lines provide scan signals, data lines provide data signals, and the intersection of the activated gate lines and data lines... Subpixels are charged, which drives the liquid crystal to deflect, allowing light to pass through or not through the backlight, thus achieving display”)
a display panel comprising a pixel row comprising pixels arranged in a first direction, and a first gate line and a second gate line connected to the pixel row, wherein each of the pixels comprises sub-pixels arranged in the first direction (Tang, embodiment in fig. 2, 3, 5, 6, 9, 11, 12, see example annotate figures below, pg. 7, ln. 8-17, “As shown in Figures 1-3, the array substrate in this embodiment mainly includes: Multiple pixel units arranged in an array, each pixel unit including at least three adjacent sub-pixels; Multiple grid line groups G, each corresponding to a row of pixel units, include multiple grid lines extending along the row direction. The number of grid lines in each grid line group is the same as the number of sub-pixels in the pixel unit. One grid line in a grid line group is connected to a sub-pixel in the same row that emits the same color light”, pg. 9, ln. 7-14, “Specifically, for the same gate line group, one gate line in the group can be connected to a sub-pixel located in a row that emits the same color light. For example, taking Figures 2 and 3 as examples, a gate line group includes three gate lines, with different gate lines connected to sub-pixels of different emitting colors in a row. It should be noted that the connection between the gate line and the sub-pixel can, in practice, refer to the connection between the gate line and the gate of the sub-pixel's thin-film transistor”);
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a gate driver which provides a first gate signal and a second gate signal to the first gate line and the second gate line; and a data driver which provides data voltages (Tang, pg. 7, ln. 22 – pg. 8, ln. 2: “The array substrate includes a display area 10 and a peripheral area 20 surrounding the display area. A data driver chip and a gate driver chip can be mounted in the bonding area, and gate leads and data leads can be arranged in the fan-out area. One data lead is connected to an output pin of the data driver chip, and multiple gate leads are connected to the gate driver chip. One data lead is connected to a data line in a data line group proposed in this disclosure, thereby transmitting the data signal output by the data driver chip to the data line group. According to the line group; the transfer area is used to transfer the leads of the fan-out area to the display area, and the load area is equipped with a gate drive circuit to drive the gate line scanning”).
Tang does not disclose in particular a demultiplexer which selectively provides the data voltages from the data driver to the sub-pixels of the pixels in response to a first selection signal, a second selection, and a third selection signal,
wherein the demultiplexer comprises: a first selection transistor comprising a gate connected to a first selection line; a second selection transistor comprising a gate connected to a second selection line which transmits the second selection signal; and a third selection transistor comprising a gate connected to a third selection line.
In similar field of endeavor of display drive, Ryu discloses the concept of using demultiplexer (fig. 1, demultiplexer 160) to selective provide data voltages from data driver (fig. 1, data driver 120) to sub-pixels of display device (fig. 1, sub-pixels 140), wherein the display device comprises (see Ryu, annotated figures below, paragraphs 32-36, 48-51):
a demultiplexer which selectively provides the data voltages from the data driver to the sub-pixels of the pixels in response to a first selection signal, a second selection, and a third selection signal,
wherein the demultiplexer comprises: a first selection transistor comprising a gate connected to a first selection line; a second selection transistor comprising a gate connected to a second selection line which transmits the second selection signal; and a third selection transistor comprising a gate connected to a third selection line.
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It would have been obvious to one of ordinary skill in the art at the time of filing to incorporate the concept demultiplexing data signals from data driver to different data lines using a demultiplexer, such as disclosed by Ryu, into the display device of Tang, to constitute a demultiplexer which selectively provides the data voltages from the data driver to the sub-pixels of the pixels in response to a first selection signal, a second selection, and a third selection signal, wherein the demultiplexer comprises: a first selection transistor comprising a gate connected to a first selection line; a second selection transistor comprising a gate connected to a second selection line which transmits the second selection signal; and a third selection transistor comprising a gate connected to a third selection line, such is incorporation of a known technique into a known device to yield predictable result, the result would have been predictable and would allow reduced number of data lines connected to data driver while data signal is selectively provided to sub-pixels via demultiplexer to display image.
Tang in view of Ryu does not disclose in particular that the first gate signal, second gate signal, the first selection signal, the second selection signal, and the third selection signal are shifted with respect to each other by a 1/3 of horizontal time interval.
In similar field of endeavor, Oh discloses display device (fig. 3, display panel 100 with matrix of pixel connected to data lines and gate lines, “TFT array substrate of the LCD panel 100 are formed the data lines 105, the gate lines 106, TFTs, pixel electrodes 1 of liquid crystal cells Clc, and storage capacitors Cst. The gate lines 106 cross the data lines 105”). Similar to display device of Tang, Oh discloses a pixel row comprising pixels with a first gate line, second gate line, and third gate line connected to the pixel row (Oh, fig. 4, 6, 8, each pixel row is selectively connected by three gate lines, e.g. gate lines G1, G2, G3 to first pixel row), similar to display device of Ryu, Oh discloses data lines is controlled by selection signal that selectively provide data voltage to data line connected to subpixels in a time-division manner (Oh, paragraphs 33, 35, 48: “subpixels RGB of one pixel share the same data line through which data voltages are supplied to the subpixels in a time-division manner and sequentially charged to the subpixels”; “to drive the subpixels of the first pixel in a time-division manner, gate pulses are sequentially applied to the first to third gate lines G1 to G3”; “subpixels RGB of one pixel share the same data line through which data voltages are supplied to the subpixels in a time-division manner and sequentially charged to the subpixels. As a consequence, the LCD according to the embodiments may decrease the number of the data lines 105 and the number of source drive ICs by ⅓ compared with the conventional LCD in which subpixels are connected to separate data lines, respectively”, as a single data line is configured to supply data voltage to three different subpixels in a time-division manner, it is required that data voltage a selectively supplied in a time sequence, hence the selection signal). Oh further discloses driving sequence wherein each gate selection signal and each data selection signal is shifted from one another by 1/3 of a horizontal time interval: see annotated fig. 7 below, paragraphs 41, 42, “Referring to FIGS. 6 and 7, a polarity control signal POL is inversed at one horizontal period. The one horizontal period refers to one line scanning time during which data are written in pixels of one display line in the LCD panel 100. Each data voltage is supplied to the data line during about 1/3 horizontal period. To compensate for a relatively insufficient pixel charging time, the gate driver 103 sequentially supplies gate pulses, each having a pulse width of substantially one horizontal period, to the gate lines G1 to G9. An nth gate pulse (n is a natural number) overlaps an n-1th gate pulse by about 2/3 pulse width, and the nth gate pulse overlaps an n+1th gate pulse by about 2/3 pulse width”).
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It would have been obvious to one of ordinary skill in the art at the time of filing to incorporate the concept sequentially driving gate selection signals and data selection signals of display device, wherein selection signals are shifted by 1/3 horizontal time interval from each other, such as disclosed by Oh, into the display device of Tang in view of Ryu wherein gate line signal is supplied by gate driver and data voltage signal is supplied by demultiplexer, to constitute a gate driver which provides a first gate signal and a second gate signal shifted by 1/3 horizontal time interval of the first gate signal to the first gate line and the second gate line, and a demultiplexer which selectively provides the data voltages from the data driver to the sub-pixels of the pixels in response to a first selection signal, a second selection signal shifted by 1/3 horizontal time interval of the first selection signal, and a third selection signal shifted by 1/3 horizontal time interval of the second selection signal, such is incorporation of a known technique into a known device to yield predictable result, the result would have been predictable and would allow sequentially scanning and driving of sub-pixels arranged in matrix in a time-division manner to provide image signal to display image.
Regarding claim 9, Tang in view of Ryu and Oh discloses the display device of claim 1, wherein each of the first selection signal, the second selection signal, and the third selection signal has a pulse having a width corresponding to 1/3 horizontal time interval, and wherein the pulse of the first selection signal, the pulse of the second selection signal, and the pulse of the third selection signal do not overlap each other.
(see Oh, fig. 4, each data line signal has pulse width of 1/3 horizontal time interval, and each data line signal does not overlap with each other)
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Regarding claim 10, Tang in view of Ryu and Oh discloses the display device of claim 1, wherein the display panel further comprises a third gate line connected to the pixel row (see Tang, fig. 3, each pixel row connected with a first, second and third gate line), and
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wherein the gate driver provides the first gate signal, the second gate signal, and a third gate signal shifted by 1/3 horizontal time interval of the second gate signal to the first gate line, the second gate line, and the third gate line, respectively (see Oh, fig. 7, each of first, second, third gate line signal is shifted by 1/3 horizontal time interval from previous gate line signal).
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Regarding claim 12, Tang in view of Ryu and Oh discloses the display device of claim 10, wherein the first gate line, the second gate line, and the third gate line are alternately connected to the pixel row on a sub-pixel by sub-pixel basis (see Tang, fig. 3, each of first , second, third gate line are alternately connected to the pixel row on a sub-pixel by sub-pixel basis, that is, a first subpixel is connected to the first gate line, a second sub-pixel is connected to the second gate line, and a third subpixel is connected to the third gate line, and so on).
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Regarding claim 13, Tang in view of Ryu and Oh discloses the display device of claim 10, wherein each of the first gate signal, the second gate signal, and the third gate signal has a pulse having a width corresponding to one horizontal time interval, and wherein the pulse of the first gate signal, the pulse of the second gate signal, and the pulse of the third gate signal partially overlap each other (see Oh, fig. 7, each of first, second, third gate line signal has a pulse width of 1H, and pulse of first, second third gate signal partially overlap each other).
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Regarding claim 14, this is an electronic device counterpart of display device claim 1, both reciting similar subject matter, with combination of Tang in view of Ryu and Oh as applied in claim 1 additionally disclosing the electronic device comprises a processor and a display device which receives input image data from the processor (see for example, Ryu, fig. 1, paragraph 33, timing control processor 150 “may generate a data driving signal DCS and a scan driving signal SCS corresponding to external synchronizing signals. The data driving signal DCS generated from the timing control unit 150 may be provided to the data driver 120, and the scan driving signal SCS may be provided to the scan driver 110. Further, the timing control unit 150 may provide externally supplied data DATA to the data driver 120”, Oh, fig. 1, paragraph 26, timing controller processor 101 “The timing controller 101 supplies digital video data for images input from the host system 104 to the data driver 102”). Hence claim 14 is rejected under same combination of Tang in view of Ryu and Oh as in rejection of claim 1 above.
Regarding claim 20, this is an electronic device counterpart of display device claim 9, both reciting similar subject matter, therefore, claim 20 is rejected for the same reasons as in rejection of claim 9.
Claims 11 is rejected under 35 U.S.C. 103 as being unpatentable over Tang in view of Ryu and Oh, as applied to claim 10 above, and further in view of Chen et al., WO 2026178897 A1 (hereinafter “Chen”).
Regarding claim 11, Tang in view of Ryu and Oh discloses the display device of claim 10.
Tang in view of Ryu and Oh does not disclose in particular wherein the first gate line, the second gate line, and the third gate line are alternately connected to the pixel row on a pixel-by-pixel basis.
In similar field of endeavor of display device (fig. 1, page 8, second paragraph, display 1000), Chen disclose similar display wherein each pixel row is connected by a first, second, and third gate line (, and wherein the first gate line, the second gate line, and the third gate line are alternately connected to the pixel row on a pixel-by-pixel basis (fig. 3, see annotated figure below, page 10, first and second paragraph, page 11, first paragraph, each pixel P comprises subpixels PX, each pixel P is connected to a gate line, each pixel row comprises at least a first, second and a third gate line alternately to pixel on a pixel-by-pixel basis, i.e. a first gate line is connected to the first pixel, a second gate line is connected to the second pixel, and a third gate line is connected to a third pixel).
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Both Tang in view of Ryu and Oh as well as Chen disclose pixel row connected to first, second, and third gate lines, Chen discloses the alternative connection scheme of gate lines on pixel-by-pixel basis instead of sub-pixel-by-sub-pixel basis. It would have been obvious to one of ordinary skill in the art at the time of filing to incorporate the concept connecting gate lines to pixel row on pixel-by-pixel basis, such as disclosed by Chen, into display device of Tang in view of Ryu and Oh, to constitute wherein the first gate line, the second gate line, and the third gate line are alternately connected to the pixel row on a pixel-by-pixel basis, such is replacement of a known technique by another known technique in a known device to yield predictable result, the result would have been predictable and the function of allowing pixel rows to be scanned by gate line signals would have been the same.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PEIJIE SHEN whose telephone number is (571)272-5522. The examiner can normally be reached Monday - Friday 10AM - 6PM.
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/PEIJIE SHEN/Examiner, Art Unit 2622
/PATRICK N EDOUARD/Supervisory Patent Examiner, Art Unit 2622
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