Technology area: Semiconductors, Circuits & Optics
1 pending office actions • 1 art units • 1 examiners • 0 of 1 (0%) have an AI response strategy ready
Hitachi Power Semiconductor Device, Ltd. operates in the Semiconductors, Circuits & Optics technology area. The company currently has 1 pending office action in its patent portfolio. This action is being handled within 1 distinct art unit, which points to a specific focus on a particular technical niche. The presence of a single pending action suggests a targeted approach to its current intellectual property development within the Semiconductors, Circuits & Optics sector.
The prosecution for the company involves 1 distinct examiner. JEFFERSON, QUOVAUNDA is the busiest examiner for the portfolio, currently managing 1 pending office action. This count is identical to the total number of pending actions for the entire company. For a practitioner, this means that the company's current interaction with the patent office is entirely concentrated under one examiner's review. This concentration allows for a focused prosecution strategy tailored to the specific requirements of this examiner and art unit.
Based on the USPTO statutory response window for each pending office action. 1 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.
Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.
| Bucket | Cases |
|---|---|
| Multi-statute (no §101) | 1 (100%) |
How the docket's pending cases split across USPTO tech-center bands.
Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.
| Examiner | Apps on this docket | Allow rate | Interview lift |
|---|---|---|---|
| JEFFERSON, QUOVAUNDA | 1 | 79.4% | +8.7% |
Multi-statute / §101-driven matters, or cases in front of an examiner with an allow rate under 30%. The top 1 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18570706 | PLATING DEFECTS ESTIMATING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD | JEFFERSON, QUOVAUNDA | 23d |
| Art Unit | Apps |
|---|---|
| 2899 | 1 |
| App # | Title | Examiner | Art Unit | Statutes | Status | Due in | AI | Filed |
|---|---|---|---|---|---|---|---|---|
| 18570706 | PLATING DEFECTS ESTIMATING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD | JEFFERSON, QUOVAUNDA | 2899 | §102§103 | Non-Final OA | 23d | Pending | Dec 15, 2023 |
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Start Free TrialHitachi Power Semiconductor Device, Ltd. has 1 pending office actions as of October 2026, spread across 1 art units and 1 examiners.
Quovaunda Jefferson has the most, with 1 of Hitachi Power Semiconductor Device, Ltd.'s pending office actions.
Mostly Semiconductors, Circuits & Optics (USPTO Tech Center 2800), based on where its pending office actions are examined.
