Prosecution Insights
Last updated: October 27, 2026

Quovaunda Jefferson, USPTO Patent Examiner

Listed by the USPTO as JEFFERSON, QUOVAUNDA

Tech Center 2800 • Art Units: 2823 2899

This examiner grants 79% of resolved cases

Analysis

JEFFERSON, QUOVAUNDA examines in tech center 2800 and art unit 2823. The record includes 913 resolved cases, an allowance rate of 79.4%, and a median of 1031 days to allowance. The 8.7% interview lift provides a limited but distinct indicator of interview-associated outcomes. Applicants can use the profile to set expectations about examination duration and to reserve interviews for issues that benefit from direct technical clarification.

The principal companies are Taiwan Semiconductor Manufacturing Company, Ltd., Intel Corporation, and Samsung Display Co., Ltd. The listed firms are Haynes and Boone, LLP (24061), Alliance IP, LLC - Intel, and Womble Bond Dickinson US LLP. Their prosecution histories provide useful material for semiconductor and display claim strategy in art unit 2823.

Written from this page's own data; every figure is computed from USPTO records and verified before publication.

Performance Statistics

79.4%
Allow Rate
+11.4% vs TC avg
956
Total Applications
+8.7%
Interview Lift
1031
Avg Prosecution Days
Based on 913 resolved cases, 2023–2026

Rejection Statute Breakdown

0.3%
§101 Eligibility
25.2%
§102 Novelty
60.0%
§103 Obviousness
9.4%
§112 Clarity

Currently Pending Office Actions

App #TitleStatusAssignee
18486047 PHOTOELECTRIC CONVERSION DEVICE AND EQUIPMENT Non-Final OA CANON KABUSHIKI KAISHA
18485823 Display Device and Tiling Display Device Including the Same Non-Final OA LG Display Co., Ltd.
18613953 DISPLAY DEVICE Final Rejection Samsung Display Co., Ltd.
18727256 SEMICONDUCTOR DEVICE AND IMAGING DEVICE Non-Final OA SONY SEMICONDUCTOR SOLUTIONS CORPORATION
18418505 PACKAGE SUBSTRATE WITH EMBEDDED CAPACITOR PACKAGE HAVING REDISTRIBUTION LAYER(S) (RDL(s)) FOR ALIGNING CAPACITOR TERMINALS CONNECTIONS TO SEMICONDUCTOR DIE IN AN INTEGRATED CIRCUIT (IC) PACKAGE, AND RELATED FABRICATION METHODS Final Rejection QUALCOMM Incorporated
18061083 POLYMER LAYERS FOR ADHESIVE PROMOTION AND STRESS MANAGEMENT IN GLASS LAYERS IN INTEGRATED CIRCUIT DEVICES Final Rejection Intel Corporation
18061126 POLYMERIC FILMS AS AN ADHESIVE PROMOTION/BUFFER LAYER AT GLASS-DIELECTRIC OR METAL-DIELECTRIC INTERFACES Final Rejection Intel Corporation
18090407 FLASH MEMORY CHIP WITH SELF ALIGNED ISOLATION FILL BETWEEN PILLARS Non-Final OA Intel NDTM US LLC
18759559 MAGNETIC MEMORY DEVICE USING SPIN PUMPING Non-Final OA Korea Advanced Institute of Science and Technology
18391011 SYSTEMS AND METHODS FOR THREE-DIMENSIONALLY STACKING SYSTEMS ON CHIP WITH FACE-TO-FACE HYBRID BONDING Non-Final OA Meta Platforms Technologies, LLC
18208710 ATOMIC LAYER DEPOSITION OF HIGH DIELECTRIC CONSTANT MATERIALS Non-Final OA Applied Materials, Inc.
17973927 OXIDATION ENHANCED DOPING Non-Final OA Applied Materials, Inc.
18761821 NON-VOLATILE MEMORY WITH COUNTER-DOPED IMPLANT AND METHOD OF MANUFACTURING SAME Non-Final OA STMICROELECTRONICS INTERNATIONAL N.V.
18787131 DEPOSITION WINDOW ENLARGEMENT Non-Final OA Taiwan Semiconductor Manufacturing Co., Ltd.
18787208 CONTACT PLUG Non-Final OA Taiwan Semiconductor Manufacturing Co., Ltd.
18782167 CONDUCTIVE CONTACT HAVING BARRIER LAYERS WITH DIFFERENT DEPTHS Non-Final OA Taiwan Semiconductor Manufacturing Co., Ltd.
18781455 Method for Reducing Line-End Space in Integrated Circuit Patterning Non-Final OA Taiwan Semiconductor Manufacturing Co., Ltd.
18756609 PLANAR AND NON-PLANAR FET-BASED ELECTROSTATIC DISCHARGE PROTECTION DEVICES Non-Final OA Taiwan Semiconductor Manufacturing Co., Ltd.
17590116 Methods And Systems For Accurate Measurement Of Deep Structures Having Distorted Geometry Final Rejection KLA Corporation

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Frequently Asked Questions

What is examiner Quovaunda Jefferson's allowance rate?

79.4% of resolved applications examined by Quovaunda Jefferson were allowed (913 resolved cases), compared with 46.2% across Art Unit 2823 over the last five years.

Does an interview help with examiner Quovaunda Jefferson?

This examiner's interview lift is +8.7 percentage points: the difference in allowance rate between resolved applications that had an examiner interview and those that did not.

How long does examiner Quovaunda Jefferson take to allow a patent?

Applications allowed by Quovaunda Jefferson took 1,031 days on average from filing to allowance.

Which art unit does examiner Quovaunda Jefferson work in?

Quovaunda Jefferson examines applications in Art Unit 2823 in Tech Center 2800 (Semiconductors, Circuits & Optics).

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