DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 9/30/2025 has been entered.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1, 3-7, and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Birner et al. (US 2017/0373187 A1) in view of Liao et al. (US 2018/0033866 A1).
Regarding claim 1, Birner discloses a semiconductor device (Fig. 11), comprising:
a substrate (111);
a gate stack (116 and unlabeled layer directly contacting the top surface of 116) and a first dielectric layer (unlabeled in Fig. 11, see annotated copy of Fig. 11, below) over the substrate, wherein the first dielectric layer is laterally aside and over the gate stack (see Fig. 11);
a source/drain (S/D) region (although not shown in Fig. 11, the source/drain region of Birner comprises 114, 115, 117, and 118 in Fig. 6 of Birner), located in the substrate on sides of the gate stack;
a contact (128 in Fig. 11), penetrating through the first dielectric layer to electrically connect to the S/D region; and
an active via (146), penetrating through a second dielectric layer (unlabeled in Fig. 11, see annotated copy below) to connect to the contact, wherein the active via comprises a conductive layer (¶ 0104), wherein the conductive layer is in physical contact with the contact, and
wherein the contact is laterally aside the gate stack (See Fig. 11).
Although not shown in Fig. 11, Birner further discloses that conductive layers may also have an adhesion promoter layer applied on sidewalls thereof, wherein the adhesion promoter layer comprises a conductive material (¶ 0084).
It would have been obvious to one having ordinary skill in the art before the Application’s effective filing date to apply an adhesion promoter layer to the sidewalls of the conductive layer cited above for the benefit of promoting adhesion.
Although not shown in Fig. 11, Birner further discloses that conductive layers such as the contact may also have a barrier layer applied on sidewalls thereof (¶ 0084).
There is a benefit to having such a barrier layer surrounding the contact in that it mitigates potentially damaging metal diffusion into the source/drain region.
It would have been obvious to one having ordinary skill in the art before the Application’s effective filing date to use a barrier layer along the sidewall of the contact for this benefit.
In the barrier layer formed as such, as the contact extends from a top surface of the first dielectric layer to a bottom surface of the first dielectric layer (see annotated copy of Fig. 11, below), the barrier layer will similarly continuously extend from a top surface of the first dielectric layer to a bottom surface of the first dielectric layer to electrically connect to the source/drain region.
Birner further discloses that the gate stack comprises a conductive electrode (116) but does not disclose that there is a spacer on a sidewall of the conductive electrode.
Liao, in the same field of endeavor, discloses that spacers may be formed on sidewalls of conductive electrodes (gate spacer comprising the right 32 and the right 50 in Fig. 23 of Liao).
There was a benefit to such spacers in that it insulates the gate electrode from cross talk from adjacent conductors.
It would have been obvious to one having ordinary skill in the art before the Application's effective filing date to form a spacer on a sidewall of the conductive electrode of Birner for this benefit.
In the device of the combination, a portion of the spacer (right 32 in Fig. 23 of Liao) is in direct contact with a portion of the source/drain (S/D) region (portion 117 in Fig. 6 of Birner), and the rest of the spacer (right 50 in Fig. 23 of Liao) is in direct contact with a portion of the substrate (portion 117 in Fig. 6 of Birner; Birner discloses that portion 117, which is part of the source/drain region, is also a portion of the substrate as that portion is formed by introducing dopants into the substrate ¶¶ 0086-0087 of Birner).
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Regarding claim 3, Birner in view of Liao discloses the device of claim 1, as discussed above.
Birner further discloses that the adhesion promoter layers may be applied only to the sidewalls of the conductive structures and not along the bottom surfaces (¶ 0084).
In forming the adhesion promoter layer as such, a bottom surface of the adhesion promoter layer will therefore be coplanar with a bottom surface of the conductive layer.
With regards to the bottom surface of the adhesion promoter layer being free from the barrier layer and the bottom surface of the conductive layer being in direct contact with the barrier layer, this limitation refers to the conductive layer being at least as wide as the span between the outermost sides of the barrier layer.
Birner does not explicitly disclose this feature.
However, Birner discloses that the conductive layer should be wider than the portion of the contact interior to the barrier layer (¶ 0105). Further, the width of the conductive layer also determines how closely cavities 144 and 145 in Fig. 11 may be spaced (¶ 0105); if the width of conductive layer is too large, the cavities of Birner are unnecessarily far apart which leads to an undesirably wider device footprint.
As such, setting the width of the conductive layer to be at least as wide as the span between the outermost sides of the barrier layer (which results in the bottom surface of the adhesion promoter layer being free from the barrier layer and the bottom surface of the conductive layer being in direct contact with the barrier layer) amounts to discovering the workable range of the width of the conductive layer by routine experimentation and, therefore, obvious to one having ordinary skill in the art before the Application’s effective filing date. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." (In re Aller, 105 USPQ 233 (C.C.P.A. 1955); MPEP § 2144.05(II)(A)).
Regarding claim 4, Birner in view of Liao discloses the device of claim 1, as discussed above.
Birner further discloses that the adhesion promoter layers may be applied only to the sidewalls of the conductive structures and not along the bottom surfaces (¶ 0084).
In forming the adhesion promoter layer as such, the adhesion promoter layer will contact the first dielectric layer but not cover the barrier layer as the conductive layer extends past the contact (which includes the barrier layer) in the width direction (see Fig. 11).
With regards to an interface between the conductive layer and the adhesion promoter layer being connected with an interface between the barrier layer and the first dielectric layer, this limitation refers to the conductive layer being as wide as the span between the outermost sides of the barrier layer.
Birner does not explicitly disclose this feature.
However, Birner discloses that the conductive layer should be wider than the portion of the contact interior to the barrier layer (¶ 0105). Further, the width of the conductive layer also determines how closely cavities 144 and 145 in Fig. 11 may be spaced (¶ 0105); if the width of conductive layer is too large, the cavities of Birner are unnecessarily far apart which leads to an undesirably wider device footprint.
As such, setting the width of the conductive layer to be as wide as the span between the outermost sides of the barrier layer (which results in an interface between the conductive layer and the adhesion promoter layer being connected with an interface between the barrier layer and the first dielectric) amounts to discovering the workable range of the width of the conductive layer by routine experimentation and, therefore, obvious to one having ordinary skill in the art before the Application’s effective filing date. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." (In re Aller, 105 USPQ 233 (C.C.P.A. 1955); MPEP § 2144.05(II)(A)).
Regarding claim 5, Birner in view of Liao discloses the device of claim 1, as discussed above.
Birner further discloses that the conductive layer has a top surface which is level with a top surface of the second dielectric layer (see Fig. 11).
Regarding claim 6, Birner in view of Liao discloses the device of claim 1, as discussed above.
Birner further discloses that the contact comprises the barrier layer (previously discussed) and a conductive feature (metal of 128) on the barrier layer. Birner further discloses that the barrier layer may be formed to surround the sidewalls as well as the bottom of the conductive feature (¶ 0084), wherein the conductive feature is free of interface (i.e., it is a single continuous piece) from a top surface of the condutive feature to a bottom surface of the conductive feature (see Fig. 11), and in the device of the combination the portion of the spacer and the rest of the spacer are both located between the gate stack and the contact (see Fig. 11 of Birner).
Regarding claim 7, Birner in view of Liao discloses the device of claim 6, as discussed above.
Birner further discloses using tungsten for the contact (¶ 0093) and copper for the via (¶ 0100) and, corresponding, teaches different materials for the adhesion promoter layer and barrier layer based on these different materials (¶ 0084).
Regarding claim 21, Birner in view of Liao discloses the device of claim 1, as discussed above.
Birner further discloses that the first dielectric layer comprises a first dielectric material (126 in Fig. 6) and a second dielectric material (124 in Fig. 6), and a top surface of the first dielectric material is level with a top surface of the gate stack (see Fig. 6).
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Birner et al. in view of Liao et al. as applied to claim 1 above, and further in view of Shin et al. (US 2019/0148439 A1).
Regarding claim 2, Birner in view of Liao discloses the device of claim 1, as discussed above.
Birner further discloses that the adhesion promoter layers may be applied only to the sidewalls of the conductive structures and not along the bottom surfaces (¶ 0084).
In forming the adhesion promoter layer as such, the adhesion promoter layer will be separated from the contact by the conductive layer as the conductive layer extends past the contact in the width direction (see Fig. 11).
Birner discloses that the adhesion promoter may comprise tantalum or titanium and that the conductive layer may comprise tungsten or copper (¶ 0084) but does not disclose that the conductive material of the adhesion promoter layer comprises a same metal as the conductive layer.
It would have been obvious to one having ordinary skill in the art before the Application’s effective filing date to form the conductive layers of Birner from TiW (which has a same metal as the conductive material of the adhesion promoter (i.e., tungsten)) as it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use. In re Leshin, 125 USPQ 416.
Birner differs from the claimed invention by the substitution of TiW with tungsten/copper. However, TiW and the corresponding function was known in the art (¶ 0044 of Shin). As such, it would have been obvious to one having ordinary skill in the art before the Application's effective filing date to have substituted the known compound of TiW as taught by Shin for compound of Birner and the results of the substitution would have been predictable. (see MPEP § 2143(I)(B)).
Claim(s) 9-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Birner et al. (US 2017/0373187 A1) in view of Liao et al. (US 2018/0033866 A1), Lin et al. (US 9,601,430 B2) and Su et al. (US 2014/0027822 A1).
Regarding claim 9, Birner discloses a semiconductor device (Fig. 11), comprising:
a substrate (111);
a gate stack (116 and unlabeled layer directly contacting the top surface of 116) and a first dielectric layer (unlabeled in Fig. 11, see annotated copy of Fig. 11, below) over the substrate, wherein the first dielectric layer is laterally aside and over the gate stack;
a source/drain (S/D) region (although not shown in Fig. 11, the source/drain region of Birner comprises 114, 115, 117, and 118 in Fig. 6 of Birner), located in the substrate on sides of the gate stack;
a contact (128), penetrating through the first dielectric layer to electrically connect to the substrate, wherein the contact comprises a first conductive layer (128).
Although not shown in Fig. 11, Birner further discloses that the first conductive layer may also have a barrier layer applied on sidewalls thereof (¶ 0084).
There is a benefit to having such a barrier layer surrounding the contact in that it mitigates potentially damaging metal diffusion into the source/drain region.
It would have been obvious to one having ordinary skill in the art before the Application’s effective filing date to use a barrier layer along the sidewall of the contact for this benefit.
Birner further discloses a second conductive layer (combination of 146 and 168), penetrating through a second dielectric layer (unlabeled in Fig. 11, see annotated copy below) to connect to the contact, wherein a bottom width of the second conductive layer is greater than a top width of first conductive layer of the contact (see Fig. 11).
Although not shown in Fig. 11, Birner further discloses that conductive layers may also have an adhesion promoter layer applied on sidewalls thereof (¶ 0084).
It would have been obvious to one having ordinary skill in the art before the Application’s effective filing date to apply an adhesion promoter layer to the sidewalls of the first conductive layer cited above for the benefit of promoting adhesion.
The adhesion layer thus formed will be laterally between the first conductive layer and the second dielectric layer and bottom surfaces of the adhesion promoter layer will be on two sides of the contact directly contacting the first dielectric layer (as the first conductive layer is wider than the contact).
With regards to the adhesion promoter layer being free from the barrier layer and the first conductive layer and the second conductive layer being in direct contact with the barrier layer and the first conductive layer, this limitation refers to the second conductive layer being at least as wide as the span between the outermost sides of the barrier layer.
Birner does not explicitly disclose this feature.
However, Birner discloses that the second conductive layer should be wider than first conductive layer (¶ 0105). Further, the width of the second conductive layer also determines how closely cavities 144 and 145 in Fig. 11 may be spaced (¶ 0105); if the width of second conductive layer is too large, the cavities of Birner are unnecessarily far apart which leads to an undesirably wider device footprint.
As such, setting the width of the second conductive layer to be at least as wide as the span between the outermost sides of the barrier layer (which results in the bottom surface of the adhesion promoter layer being free from the barrier layer and the bottom surface of the conductive layer being in direct contact with the barrier layer) amounts to discovering the workable range of the width of the second conductive layer by routine experimentation and, therefore, obvious to one having ordinary skill in the art before the Application’s effective filing date. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." (In re Aller, 105 USPQ 233 (C.C.P.A. 1955); MPEP § 2144.05(II)(A)).
Birner further discloses that the first dielectric layer comprises a first dielectric material (126 in Fig. 6) and a second dielectric material (124 in Fig. 6), and a top surface of the first dielectric material is level with a top surface of the gate stack (see Fig. 6).
Birner further discloses that the gate stack comprises a conductive electrode (116) but does not disclose that there is a spacer on a sidewall of the conductive electrode.
Liao, in the same field of endeavor, discloses that spacers may be formed directly on sidewalls of conductive electrodes (gate spacer comprising the right 32 and the right 50 in Fig. 23 of Liao).
There was a benefit to such spacers in that it insulates the gate electrode from cross talk from adjacent conductors.
It would have been obvious to one having ordinary skill in the art before the Application's effective filing date to form a spacer on a sidewall of the conductive electrode of Birner for this benefit.
wherein the spacer also directly contacts the contact to the source/drain region.
Birner does not disclose the inclusion of a silicide layer as claimed.
Lin, in the same field of endeavor, discloses that silicide layers may be formed between source/drain (S/D) regions and their corresponding contacts (“metal silicide regions 762” in Fig. 7A).
There was a benefit to including silicide layers in that in increases the conductivity of the connection between the source/drain (S/D) regions and their respective contacts.
It would have been obvious to one having ordinary skill in the art before the Application's effective filing date to form a silicide layer as taught by Lin on the source/drain (S/D) region in the device of the combination for this benefit.
The silicide layer of Lin is not shown as being in direct contact with a sidewall of the spacer.
Su, in the same field of endeavor, discloses that silicide layers (50 in Fig. 5) may be formed to extend above the top surface of the corresponding source/drain region (22 in Fig. 5). There was a benefit to such a configuration in that it further increases the amount of silicide, thereby increasing the conductivity between the contact and the source/drain. It would have been obvious to one having ordinary skill in the art before the Application's effective filing date to form the silicide layer in the device of the combination to extend above the surface of the source/drain regions for this benefit. In such a configuration, the silicide layer will be in direct contact with a sidewall of the spacer.
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Regarding claim 10, Birner in view of Lin and Su discloses the device of claim 9, as discussed above.
Birner further discloses an etching stop layer (unlabeled in Fig. 11, corresponding to 127 in Fig. 7) between the first dielectric layer and the second dielectric layer, wherein a bottom surface of the second conductive layer and the bottom surface of the adhesion promoter layer will be coplanar with a bottom surface of the etching stop layer (see Fig. 11), and wherein the spacer is in direct contact with the sidewall of the conductive electrode (see rejection of claim 9).
With regards to the second conductive layer being separated from the first dielectric layer by the contact and the adhesion promoter layer, this limitation refers to the second conductive layer being as wide as the span between the outermost sides of the barrier layer.
Birner does not explicitly disclose this feature.
However, Birner discloses that the second conductive layer should be wider than first conductive layer (¶ 0105). Further, the width of the second conductive layer also determines how closely cavities 144 and 145 in Fig. 11 may be spaced (¶ 0105); if the width of second conductive layer is too large, the cavities of Birner are unnecessarily far apart which leads to an undesirably wider device footprint.
As such, setting the width of the second conductive layer to be as wide as the span between the outermost sides of the barrier layer (which results in the second conductive layer being separated from the first dielectric layer by the contact and the adhesion promoter layer) amounts to discovering the workable range of the width of the second conductive layer by routine experimentation and, therefore, obvious to one having ordinary skill in the art before the Application’s effective filing date. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." (In re Aller, 105 USPQ 233 (C.C.P.A. 1955); MPEP § 2144.05(II)(A)).
Regarding claim 11, Birner in view of Lin and Su discloses the device of claim 9, as discussed above.
Further, in the device of the combination, the adhesion promoter layer (as discussed above, the adhesion promoter layer is applied to the sidewalls of the conductive layers (i.e., the sidewalls of 168 in Fig. 11 of Birner), ¶ 0084) will extend to cover (which Merriam Webster defines as to be over) a top surface of the second dielectric layer (as the wider portion of 168 is directly over the second dielectric layer which corresponds to 124 in Fig. 6).
Regarding claim 12, Birner in view of Lin and Su discloses the device of claim 9, as discussed above.
Birner further discloses forming the first and second dielectric layers with a material that has a hydrophilic property (silicon dioxide is a part of the first dielectric layer (¶ 0091) and second dielectric layer (¶ 0098) and, in its natural state, silicon dioxide is hydrophilic).
Regarding claim 13, Birner in view of Lin and Su discloses the device of claim 9, as discussed above.
Birner further discloses the second conductive layer (168 in Fig. 11) protrudes from a top surface of the second dielectric layer (the second dielectric layer corresponding to 124 in Fig. 6, protrusion shown in Fig. 11).
Response to Arguments
Applicant’s arguments with respect to the claims have been considered but are moot in view of the new mapping of the prior art provided in the rejections above.
Conclusion
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/CHRISTOPHER A CULBERT/Examiner, Art Unit 2815