DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114 was filed in this application after a decision by the Patent Trial and Appeal Board, but before the filing of a Notice of Appeal to the Court of Appeals for the Federal Circuit or the commencement of a civil action. Since this application is eligible for continued examination under 37 CFR 1.114 and the fee set forth in 37 CFR 1.17(e) has been timely paid, the appeal has been withdrawn pursuant to 37 CFR 1.114 and prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant’s submission filed on 4/6/2026 has been entered.
Claims 1, 21, 37-44, 46-48, and 50-56 are pending. Claims 2-20, 22-36, 45, and 49 have been canceled. Claims 38-43 have been withdrawn. Claims 21 and 37 have been amended.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 21, 37 and 50-54 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claims 21 and 37 reciting “the intermediate layer extends linearly along bottom surfaces of the plurality of metal layers” renders the claim indefinite. As best understood, separate strips of intermediate layers are formed under the plurality of metal layers. I.e. an intermediate layer is provided under each of the plurality of metal layers. It is unclear how would the plurality of metal layers be provided over a common intermediate layer. In the instance that “the intermediate layer” include a plurality of separate strips, it is unclear how is “a width” of “the intermediate layer” characterized. Is “a width” referring to the span of the entire collection of “intermediate layer” or is “a width” intended to refer to one of the strips of the intermediate layer.
Other claims are rejected for depending on a rejected claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 46, and 47 is/are rejected under 35 U.S.C. 103 as being unpatentable over Eun et al. US 2010/0203672 A1 (Eun) in view of Terai US 2017/0117328 A1 (Terai’328).
In re claim 1, Eun discloses (e.g. FIGs. 2-3) a memory device comprising:
a substrate 110;
a bottom electrode WL 130 disposed over the substrate 110 and extending in a first (x) direction in plan view;
an insulating layer 140+160+180 disposed over a top surface of the bottom electrode WL 130 (FIG. 3), the insulating layer 140+160+180 having a through hole 145+165+185 formed in the insulating layer 140+160+180, wherein the insulating layer 140+160+180 completely surrounds around the through holes 145+165+185;
a heater 170 (¶ 25) disposed in the through hole 145+165+185;
a phase change material layer 190 (¶ 23) disposed over the heater 170;
a selector layer 150 (¶ 26) disposed below the phase change material layer 190;
an intermediate layer 230 disposed over and contacting (electrically) the selector layer 150 and over the through hole 145+165+185; and
a metal layer BL 240 disposed over and contacting the intermediate layer 230, and extending in a second (y) direction perpendicular to the first (x) direction in plan view, wherein:
the intermediate layer 230 only extends linearly along a bottom surface of the metal layer 240 as seen in cross-sectional view (see FIG. 3),
the intermediate layer 230 has a first (bottom) surface that is in contact with the selector layer 150 (electrically contacted) and an uppermost surface of the insulating layer (230 contacts top surface of 180),
the uppermost surface of the insulating layer (top surface of 180) terminates at the first (bottom) surface of the intermediate layer 230,
the intermediate layer 230 has a second (top) surface opposite to the first (bottom) surface,
the second (top) surface is in contact with the metal layer 240,
the intermediate layer 230 has “a width” (width of respective strips of 230) wider than a width of the heater 170 in the through hole along the first (x) direction and has a same width as the metal layer 240 along the first (x) direction,
a first region of the first (bottom) surface of the intermediate layer 230 is in contact with the selector layer 150 (bottom surface of barrier layer 230 in region above the holes 145+165+185 in electrical contact with selector layer 150) and a second region of the first (bottom) surface of the intermediate layer 230 surrounding the first region is in contact with the uppermost surface of the insulating layer (top surface of 180 contacted by bottom of 230, see Y-Y cross-section in portion B of FIG. 3), and
an overlapped area of the bottom electrode WL 130 and the metal layer BL 240 is greater than an area of the heater 170, an area of the phase change material layer 190 and an area of the selector layer 150 in the through hole 145+165+185 in plan view (see FIGs. 2-3, heater170, PC layer 190 and selector 150 having an area corresponding to Rp as shown in FIG. 2).
Eun teaches the selector diode 150, heater 170, and PC layer 190 provided in this order inside the through hole 145+165+185. Eun does not explicitly teach the selector is disposed over the PC layer. However, Terai’328 teaches a memory device, wherein the arrangement order of the selector SW1 and PC memory layer 142 may be switched with either the selector above the PC layer 142 as shown in FIG. 3 or the PC layer 142 above the selector as shown in FIG. 7 (¶ 126).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Eun’s memory device by rearranging the components such that the selector diode 150 is above the PC layer 190 as taught by Terai’328 for being an obvious variation of the memory device structure.
In re claim 46, Eun discloses (e.g. FIGs. 2-4) wherein the selector layer 150 comprises a diode (¶ 25-26). Eun does not explicitly discloses the selector layer comprises a solid-electrolyte material containing one or more of Ge, Sb, S, Te or a chalcogenide.
Terai’328 discloses (e.g. FIGs. 2-4) a memory device having a selector layer SW1 comprises a solid-electrolyte material containing one or more of Ge, Sb, S, Te or a chalcogenide (¶ 91, 95). Terai’328 teaches OTS based selection device is preferred over diode to prevent damage to the phase change memory layers caused by processing of diodes (¶ 114-115).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Eun’s selection device 150 using a solid-electrolyte material containing one or more of Ge, Sb, S, Te or a chalcogenide as taught by Terai’328 to prevent damage caused by diode processing.
In re claim 47, Eun disclose (FIG. 3) wherein the intermediate layer 230 has a same width as the metal layer 240 and the second (top) surface is completely in contact with the metal layer 240.
Claim 44 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Eun and Terai’328 as applied to claim 1 above, and further in view of Lowrey US 2003/0047762 A1.
In re claim 44, Eun teaches the intermediate layer 230 is formed of, e.g. TiN, and is a metal barrier layer (¶ 24,29). Eun does not explicitly disclose the thickness of the intermediate layer is in a range from 1 nm to 50 nm.
However, Lowrey discloses a memory device comprising a barrier layer 26 between the memory cell and the top metal layer 28, wherein the barrier layer 26 may be TiN and has a thickness of 10 to 500 Å, i.e. 1 nm to 50 nm (¶ 29).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Eun’s intermediate layer 230 to have a thickness of 1 nm to 50 nm as taught by Lowrey for being suitable for a barrier layer that prevent diffusion and having the desired electrical characteristics in the memory device.
Claim 48 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Eun and Terai’328 as applied to claim 1 above, and further in view of Terai et al. US 2017/0237000 A1 (Terai’000).
In re claim 48, Eun teaches (FIGs. 3) the insulating layer 140+160+180 surrounding the heater 170, the phase change material layer 190, and the selector layer 150 in the through hole 145+165+185 is not in contact with the substrate 110 in the memory cell array region.
Terai’000 further teaches (FIG. 2B) a phase change memory comprising peripheral circuit PCR formed on the substrate 100 followed by stacking of memory cell structure MCR, where the peripheral circuits PCR provides control circuitries for the memory cells MCR in the memory device.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide peripheral circuits in the substrate under Terai’328’s memory cells to provide control circuitries for the memory device as taught by Terai’000. By arranging the peripheral circuit under the memory array structure, the device footprint can be reduced.
As such, additional circuit layers associated with the peripheral circuits including insulating layers 50,80 (see FIG. 2B of Terai’000”) would be provided between the substrate 100 and the insulating layer 230 that surrounds the memory cell pillars. It would be obvious to provide the insulating layers 50,80 to electrically isolate Eun’s memory cell pillars from underlying control circuits. Therefore, the insulating layer 140+160+180 surrounding the through hole 145+165+185 is not in contact with the substrate 110 due to the presence of additional insulating layers provided for electrical isolation between the memory cells and underlying peripheral circuits as taught by Terai’000.
Claims 55-56 are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Eun and Terai’328 as applied to claim 1 above, and further in view of Chen et al. US 2017/0236873 A1 (Chen).
In re claims 55-56, Eun teaches the phase change memory device comprising a selector layer 150 that comprises a diode (¶ 26).
Terai’328 teaches the phase change memory device comprising a selector layer SW1 that comprises ovonic threshold switching (OTS) material (¶ 89,90).
Eun does not explicitly disclose the selector layer 150 comprises a Schottky diode or a metal-insulator transition device.
However, Chen discloses a memory device comprising selector, wherein the selector may include be OTS, a metal-insulator transition device or a Schottky diode (¶ 67). Chen discloses these to be well-known two-terminal non-linear switches for memory devices with their known performance tradeoffs.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Eun’s selector using a Schottky diode or a metal-insulator transition device as taught by Chen to be obvious alternative selectors to be used in memory structures for their known deigns and performance advantages.
Claims 21, 37, and 50-53 is/are rejected under 35 U.S.C. 103 as being unpatentable over Eun et al. US 2010/0203672 A1 (Eun) in view of Sorada et al. US 2012/0199805 A1 (Sorada), Terai US 2017/0117328 A1 (Terai’328), and Jeong et al US 2017/0244031 A1 (Jeong).
In re claim 21, as best understood, Eun discloses (e.g. FIGs. 2-3) a memory device comprising:
a plurality of bottom electrodes WL 130, wherein longitudinal sides of the plurality of bottom electrodes WL 130 extend in a first (x) direction in plan view and the plurality of bottom electrodes WL 130 are arranged in parallel with each other in a second (y) direction perpendicular to the first (x) direction (see FIG. 2);
an insulating layer 140+160+180 disposed over a top surface of each of the plurality of bottom electrodes WL 130, the insulating layer 140+160+180 having a through hole 145+165+185 formed in the insulating layer 140+160+180, wherein the insulating layer 140+160+180 completely surrounds around the through holes 145+165+185;
a heater 170 (¶ 25) disposed in the through hole 145+165+185;
a phase change material layer 190 (¶ 23) disposed over the heater 170 in the through hole 145+165+185;
a selector layer 150 (¶ 26) disposed below the phase change material layer 190 in the through hole 145+165+185;
an intermediate layer 230 disposed over and contacting (electrically) the selector layer 150, made of carbon, tungsten, or titanium-tungsten (TiW, 230 is same material as 170, ¶ 40,57) and over the through hole 145+165+185, wherein the intermediate layer 230 extends beyond the through hole 145+165+185; and
a plurality of metal layer BL 240 disposed over and contacting the intermediate layer 230, wherein longitudinal sides of the plurality of metal layers BL 240 extend in the second (y) direction and the plurality of metal layers BL 240 are arranged in parallel with each other in the first (x) direction (see FIG. 2), wherein:
the intermediate layer 230 has a first (bottom) surface that is in contact with the selector layer 150 (electrically contacted) and an uppermost surface of the insulating layer (230 contacts top surface of 180),
“the intermediate layer 230 extends linearly along bottom surfaces of the plurality of metal layers 240, as seen in cross-sectional view (see FIG. 3)”,
the intermediate layer 230 has a second (top) surface opposite to the first (bottom) surface,
the uppermost surface of the insulating layer (top surface of 180) terminates at the first (bottom) surface of the intermediate layer 230,
the second (top) surface is in contact with the plurality of metal layer 240,
the first (bottom) surface of the intermediate layer 230 extends beyond the through hole,
a first region of the first (bottom) surface of the intermediate layer 230 is in contact with the selector layer 150 (bottom surface of barrier layer 230 in region above the holes 145+165+185 in electrical contact with selector layer 150) and a second region of the first (bottom) surface of the intermediate layer 230 surrounding the first region is in contact with the insulating layer (top surface of 180 contacted by bottom of 230, see Y-Y cross-section in portion B of FIG. 3), and
a width of the heater 170 in the through hole in the first (x) direction is smaller than a width of each of the plurality of plurality of metal layers 240 BL in the second (x) direction in plan view (see FIG. 2 & portion A of FIG. 3), and a width of the heater 170 and a width of the selector layer 150 in the through hole in the second (y) direction are smaller than a width of each of the plurality of bottom electrodes 130 WL in the second (y) direction in plan view (see FIG. 2 & portion B of FIG. 3).
Eun teaches an area of the memory element Rp (see FIG. 2) is smaller than an overlapped area of the bottom electrodes WL 130 and metal layers BL 240.
Although in the cross-sectional view along the X-X direction as shown in portion A of FIG. 3, Eun does not show the width of the selector layer 150 being smaller than a width of each metal layers BL 240 in the first (x) direction.
However, Sorada (FIGs. 1-2) a memory device comprising a plurality of parallel bottom electrodes 101 and a plurality of parallel metal layers 102, wherein the memory element 104 sandwiched between 101 and 102 has a width smaller than a width of the top metal layers 102 in the extension direction of the bottom electrodes 101, and a width smaller than a width of the bottom electrodes 101 in the extension direction of the top metal layers. Sorada teaches by setting the memory element dimension to be smaller than the overlap of the bottom metal lines and the top metal lines, the memory elements can be formed with higher accuracy without protruding outward and to achieve high integration memory array (¶ 87).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form the memory elements in Eun’s device with smaller dimension in both x and y directions than the overlap area of the intersecting top and bottom metal lines for higher integration density as taught by Sorada.
Eun teaches the selector diode 150, heater 170, and PC layer 190 provided in this order inside the through hole 145+165+185. Eun does not explicitly teach the selector is disposed over the PC layer. However, Terai’328 teaches a memory device, wherein the arrangement order of the selector SW1 and PC memory layer 142 may be switched with either the selector above the PC layer 142 as shown in FIG. 3 or the PC layer 142 above the selector as shown in FIG. 7 (¶ 126).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Eun’s memory device by rearranging the components such that the selector diode 150 is above the PC layer 190 as taught by Terai’328 for being an obvious variation of the memory device structure.
Eun teaches the heater 170 comprises TiN, TiAlN, TaN, WN, MoN, NbN, TiSiN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoAlN, TaSiN, TaAlN, TiW, TiAl, TiON, TiAlON, WON, and TaON (¶ 24-25,40-41). Eun does not explicitly disclose the heater comprises amorphous carbon.
However, Jeong teaches a phase change memory comprising a heater, wherein the heater is formed of the metal or nitride (TiN, TiSiN, TiAlN, TaSiN, TaAlN, TaN, WSi, WN, TiW, MoN, NbN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoAlN, TiAl, TiON, TiAlON, WON, TaON, ¶ 72), or is formed of carbon-based material, such as amorphous carbon (¶ 73). Jeong teaches the selection of material for the heater is based on the ability to generate sufficient heat to change the phase of the phase change material 137, but without reacting with the phase change material 137 (¶ 72).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Eun’s heater 170 using amorphous carbon instead of the metal/nitride as desirable heater material for sufficiently heating the phase change material while preventing reaction with the phase change material as taught by Jeong. The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See also In re Leshin, 277 F.2d 197, 125
In re claim 37, as best understood, Eun discloses (e.g. FIGs. 2-3) a memory device comprising:
a substrate 110;
a plurality of bottom electrodes WL 130 disposed over the substrate 110, wherein longitudinal sides of the plurality of bottom electrodes WL 130 extend in a first (x) direction in plan view and the plurality of bottom electrodes WL 130 are arranged in parallel with each other in a second (y) direction perpendicular to the first (x) direction (see FIG. 2);
a first insulating layer 140+160+180 disposed over a top surface of the plurality of bottom electrodes WL 130, the first insulating layer 140+160+180 having a through hole 145+165+185 formed in the first insulating layer 140+160+180, wherein the first insulating layer 140+160+180 completely surrounds around the through holes 145+165+185;
a first heater 170 (¶ 25) disposed in the through hole 145+165+185 over each of the plurality of bottom electrodes WL 130;
a first phase change material layer 190 (¶ 23) disposed in the through hole 145+165+185 over the first heater 170;
a first selector layer 150 (¶ 26) disposed below the phase change material layer 190;
an intermediate layer 230 disposed over and contacting (electrically) the first selector layer 150 and over the through hole 145+165+185; and
a plurality of metal layer BL 240 disposed over and contacting the intermediate layer 230, wherein longitudinal sides of the plurality of metal layers BL 240 extend in the second (y) direction and the plurality of metal layers BL 240 are arranged in parallel with each other in the first (x) direction (see FIG. 2), wherein:
“the intermediate layer 230 extends linearly along bottom surfaces of the plurality of metal layers 240, as seen in cross-sectional view (see FIG. 3)”,
the intermediate layer 230 has “a width” (width of respective strips of 230) in the first (x) direction greater than a width of the heater 170 in the through hole in the first (x) direction and has a first (bottom) surface that is in contact with the first selector layer 150 (electrically contacted) and the first insulating layer (230 contacts top surface of 180),
an uppermost surface of the first insulating layer (top surface of 180) terminates at the first (bottom) surface of the intermediate layer 230,
the intermediate layer 230 has a second (top) surface opposite to the first (bottom) surface,
the second (top) surface is in contact with the plurality of metal layer 240,
a first region of the first (bottom) surface of the intermediate layer 230 is in contact with the first selector layer 150 (bottom surface of barrier layer 230 in region above the holes 145+165+185 in electrical contact with selector layer 150) and a second region of the first (bottom) surface of the intermediate layer 230 surrounding the first region is in contact with the first insulating layer (top surface of 180 contacted by bottom of 230, see Y-Y cross-section in portion B of FIG. 3), and
the plurality of metal layers 240 disposed over and contacting the intermediate layer 230, and
a width of the first heater 170 in the through hole in the first (x) direction is smaller than a width of each of the plurality of plurality of metal layers 240 BL in the second (x) direction in plan view (see FIG. 2 & portion A of FIG. 3), and a width of the first phase change material layer 190, a width of the first heater 170 and a width of the first selector layer 150 in the through hole in the second (y) direction are smaller than a width of each of the plurality of bottom electrodes 130 WL in the second (y) direction in plan view (see FIG. 2 & portion B of FIG. 3).
Eun teaches an area of the memory element Rp (see FIG. 2) is smaller than an overlapped area of the bottom electrodes WL 130 and metal layers BL 240.
Although in the cross-sectional view along the X-X direction as shown in portion A of FIG. 3, Eun does not show the width of the first phase change material layer 190 and the first selector layer 150 being smaller than a width of each metal layers BL 240 in the first (x) direction.
However, Sorada (FIGs. 1-2) a memory device comprising a plurality of parallel bottom electrodes 101 and a plurality of parallel metal layers 102, wherein the memory element 104 sandwiched between 101 and 102 has a width smaller than a width of the top metal layers 102 in the extension direction of the bottom electrodes 101, and a width smaller than a width of the bottom electrodes 101 in the extension direction of the top metal layers. Sorada teaches by setting the memory element dimension to be smaller than the overlap of the bottom metal lines and the top metal lines, the memory elements can be formed with higher accuracy without protruding outward and to achieve high integration memory array (¶ 87).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form the memory elements in Eun’s device with smaller dimension in both x and y directions than the overlap area of the intersecting top and bottom metal lines for higher integration density as taught by Sorada.
Eun teaches first heater surrounded by sidewall spacer 172 and does not teach the first phase change material layer 190, the first heater 170 and the selector 150 having the same width.
However, Terai’328 teaches a memory device, comprising a heater HE1, a phase change material layer 142 and a selector layer SW1, wherein the heater HE1 may have the same width as the phase material layer 142 and selector layer SW1 in one embodiment as shown in FIG. 3. Terai’328 further teaches the heater HE1A may be surrounded by insulating sidewall spacer IL1 in another embodiment as shown in FIG. 8.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Eun’s first heater 170 to have a same width as the phase change material layer 190 and the selector 150 without the sidewall spacers as taught by Terai’328 to simply the manufacturing process. The presence of the sidewall spacers while beneficial in certain aspect are not needed for the function of the memory device. As such, the omission of sidewall spacers would be obvious as taught by Terai’328.
Eun teaches the first selector diode 150, first heater 170, and first PC layer 190 provided in this order inside the through hole 145+165+185. Eun does not explicitly teach the first selector is disposed over the first PC layer. However, Terai’328 teaches a memory device, wherein the arrangement order of the selector SW1 and PC memory layer 142 may be switched with either the selector above the PC layer 142 as shown in FIG. 3 or the PC layer 142 above the selector as shown in FIG. 7 (¶ 126).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Eun’s memory device by rearranging the components such that the first selector diode 150 is above the first PC layer 190 as taught by Terai’328 for being an obvious variation of the memory device structure.
Eun teaches the first heater 170 comprises TiN, TiAlN, TaN, WN, MoN, NbN, TiSiN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoAlN, TaSiN, TaAlN, TiW, TiAl, TiON, TiAlON, WON, and TaON (¶ 24-25,40-41). Eun does not explicitly disclose the first heater comprises amorphous carbon.
However, Jeong teaches a phase change memory comprising a heater, wherein the heater is formed of the metal or nitride (TiN, TiSiN, TiAlN, TaSiN, TaAlN, TaN, WSi, WN, TiW, MoN, NbN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoAlN, TiAl, TiON, TiAlON, WON, TaON, ¶ 72), or is formed of carbon-based material, such as amorphous carbon (¶ 73). Jeong teaches the selection of material for the heater is based on the ability to generate sufficient heat to change the phase of the phase change material 137, but without reacting with the phase change material 137 (¶ 72).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Eun’s first heater 170 using amorphous carbon instead of the metal/nitride as desirable heater material for sufficiently heating the phase change material while preventing reaction with the phase change material as taught by Jeong. The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See also In re Leshin, 277 F.2d 197, 125
In re claim 50, Eun discloses (FIGs. 2-4) the phase change material layer 190 comprises a chalcogenide alloy (¶ 23,43).
In re claim 51, Eun discloses (e.g. FIGs. 2-4) wherein the plurality of metal layers 240 and the plurality of bottom electrodes 130 are made of different material from each other (130 can be doped silicon, 240 may be Ti, W, etc. ¶ 34,57)
In re claim 52, Eun discloses (e.g. FIG. 3) wherein the selector layer 150 has a same width as the phase change material layer 190. Sorada discloses (e.g. FIG. 2) the layers of the memory cell structure 104 having the same width.
In re claim 53, Eun in view of Terai’328 teaches it would have been obvious to form the selector layer 150 above the phase change material layer 190. As such, Eun as modified in view of Terai’328 teaches the first (bottom) surface of the intermediate layer 230 is only in contact with the selector layer 150 (when rearranged to be above 190) and the insulating layer 140+160+180.
Claim 54 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Eun, Sorada, Terai’328, and Jeong as applied to claim 21 above, and further in view of Jo US 2015/0263069 A1.
In re claim 54, Eun teaches the phase change memory device comprising a selector layer 150 that comprises diode (¶ 25).
Jeong teaches the heater is made of amorphous carbon (¶ 72-73). The claimed resistivity of not less than 0.0035ohm-cm is an inherent property of amorphous carbon. “[T]he discovery of a previously unappreciated property of a prior art composition, or of a scientific explanation for the prior art’s functioning, does not render the old composition patentably new to the discoverer.” Atlas Powder Co. v. Ireco Inc., 190 F.3d 1342, 1347, 51 USPQ2d 1943, 1947 (Fed. Cir. 1999). Thus, the claiming of a new use, new function or unknown property which is inherently present in the prior art does not necessarily make the claim patentable. In re Best, 562 F.2d 1252, 1254, 195 USPQ 430, 433 (CCPA 1977). >In In re Crish, 393 F.3d 1253, 1258, 73 USPQ2d 1364, 1368 (Fed. Cir. 2004), the court held that the claimed promoter sequence obtained by sequencing a prior art plasmid that was not previously sequenced was anticipated by the prior art plasmid which necessarily possessed the same DNA sequence as the claimed oligonucleotides. The court stated that “just as the discovery of properties of a known material does not make it novel, the identification and characterization of a prior art material also does not make it novel.”
Eun does not explicitly disclose the selector layer 150 comprises TixNyOz, where x, y, and z are non-stoichiometric values.
However, Jo teaches (e.g. FIG. 1) a two-terminal selector device comprising a selector layer 104 that includes TixNyOz, where x, y, and z are non-stoichiometric (¶ 49). Jo teaches the selector allows reduced leakage current and lower power consumption (¶ 45).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Eun’s selector to include non-stoichiometric TixNyOz instead of a diode to form the selector device that would improve the device performance by reducing leakage current and lower consumption as taught by Jo.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 21, 37, 44, 46-48, and 50-56 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU CHEN whose telephone number is (571)270-7881. The examiner can normally be reached on Monday-Friday: 9AM-5PM ET.
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/YU CHEN/Primary Examiner, Art Unit 2815
Prosecution Insights