DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after 16 March 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Applicant
This Office Action is in response to Applicant’s reply filed on 31 August 2026.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 31 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 31 recites “the non-filament supervia is lined along a sidewall thereof by a barrier layer.” Applicant’s originally filed specification does not disclose a non-filament supervia that is lined by a barrier layer.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 28-33 and 40-47 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 28, in line 11, recites “the metal routing layers respectively comprising a plurality of metal lines…” The recitation “the metal routing layers” lack antecedent basis. Further it is unclear and indefinite as to which metal routing layers the recitation is referring to. For example, does the recitation refer to the first, second and third metal routing layers, the first and second metal routing layers, or the second and third metal routing layers? The recitation is interpreted as “each metal routing layer respectively comprising a plurality of metal lines…”
Claims 29-33, which depends either directly or indirectly from independent claim 28, do not remedy the issues of claim 28 and therefore are also rejected.
Claim 30 recites “a non-filament supervia extending through more than one dielectric layer.” It is unclear and indefinite as to whether the “more than one dielectric layer” refers back to any one of the first dielectric layer, the first filament dielectric layer, the second dielectric layer, the second filament dielectric layer or the third dielectric layer of claim 28, or if the recitation is another dielectric layer that is not in claim 28. The recitation is interpreted as “a non-filament supervia extending through at least one of the second filament dielectric layer and third dielectric layer,” as consistent with Applicant’s specification.
Claims 31-33, which depends either directly or indirectly from claim 30, do not remedy the issues of claim 30 and therefore are also rejected.
Claim 40 recites “the first filament via and the second filament via comprising conductive metal filaments of clusters of metal dots abutting the filament dielectric layer.” Claim 40 also requires the filament dielectric layer to be over and abutting the lower metal routing layer, the upper metal routing layer over the filament dielectric layer, the first filament via is disposed through the filament dielectric layer and electrically connecting the lower metal routing layer and the upper metal routing layer, and the second filament via between the upper metal routing layer and the third metal routing layer, which is stacked over the upper metal routing layer. So it appears that the first filament via is below the second filament via. Therefore, it is unclear and indefinite as to how the second filament via abuts the filament dielectric layer. For compact prosecution, it will be interpreted as only the first filament via is abutting the first filament dielectric layer so that the claim recites “the first filament via comprising conductive metal filaments of clusters of metal dots abutting the filament dielectric layer and abutting the metal lines that the first filament via connect.”
Claims 41-47, which depends either directly or indirectly from independent claim 40, do not remedy the issues of claim 28 and therefore are also rejected.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 34, 35 and 37-39 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baek et al. (U.S. Pub. 2006/0054950) in view of Haimoto et al. (U.S. Pub. 2012/0211719) in view of Wang et al. (U.S. Pub. 2014/0353566) in view of Hall et al. (U.S. Pub. 2003/0143800).
Claim 34: Baek et al. discloses an integrated chip, in Fig. 1, comprising:
a stack of metal routing layers (25, 29 and 37; paragraphs 27 and 37) of an interconnect structure separated by interlayer dielectric layers (27 and 33; paragraphs 27, 31 and 36) and respectively comprising a plurality of metal routing lines (25 and 29);
a first filament via (conductive filament; paragraphs 39 and 40) disposed through a first interlayer dielectric layer (27) of the interlayer dielectric layers (27 and 33) and connecting a first metal routing layer (25) of the stack of metal routing layers (25, 29 and 37) and a second metal routing layer (29) of the stack of metal routing layers (25, 29 and 37); and
a non-filament via (35a; paragraph 37) disposed through a second interlayer dielectric layer (33) of the interlayer dielectric layers (27 and 33) and connecting the second metal routing layer (29) and a third metal routing layer (37) of the stack of metal routing layers (25, 29 and 37).
Baek et al. appears not to explicitly disclose the first filament via comprising a conductive metal filament of a cluster of metal dots abutting the first interlayer dielectric layer, and abutting metal routing lines of the first and second metal routing layers that the first filament via connects.
Haimoto et al., however, in Figs. 3C (orientation is inverted), 19A and 19B, the first filament via (17; paragraph 67) comprising a conductive metal filament (conductive filament; paragraph 70) of a cluster of metal dots (metal ions; paragraph 70) abutting the first interlayer dielectric layer (14; paragraph 52), and abutting routing lines (13 and 15; paragraphs 47 and 49) of the first and second routing layers (13 and 15) that the first filament via (conductive filament) connects.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Baek et al. with the disclosure of Haimoto et al. to have made the first filament via comprising a conductive metal filament of a cluster of metal dots abutting the first interlayer dielectric layer, and abutting routing lines of the first and second routing layers that the first filament via connects in order to increase tolerance of the resistance value of the device (paragraph 57 of Haimoto et al.).
Since Baek et al. discloses metal routing lines of the first and second metal routing layers, Baek et al. in view of Haimoto et al. would disclose the first filament via abutting metal routing lines of the first and second metal routing layers that the first filament via connects.
Baek et al. also appears not to explicitly disclose the interlayer dielectric layers comprising a low-k dielectric material.
Wang et al., however, in Fig. 3A, discloses the first interlayer dielectric layer (322; paragraphs 41 and 42) is a low-k dielectric material (low-k dielectric layer).
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Baek et al. with the disclosure Wang et al. to have made the first interlayer dielectric layer a low-k material in order to use less power to set and reset (paragraph 41 of Wang et al.).
Also, Hall et al., in Fig. 3 and in paragraph 43, discloses a low-k dielectric material (low-k polymer) is suitable for the second interlayer dielectric layer (134).
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Baek et al. with the disclosure Hall et al. to have made the second interlayer dielectric layer a low-k dielectric material because the selection of a known material based on its suitability for its intended purpose is obvious (see, for example, M.P.E.P. § 2144.07, and precedents cited therein).
Baek et al. in view of Wang et al. in view of Hall et al. would therefore disclose the interlayer dielectric layers comprising a low-k dielectric material.
Claim 35: Baek et al. in view of Haimoto et al. in view of Wang et al. in view of Hall et al. discloses the integrated chip according to claim 34.
Baek et al. in view of Haimoto et al. in view of Wang et al. in view of Hall et al., as applied to claim 34, appears to not explicitly disclose further comprising:
a second filament via disposed through a third interlayer dielectric layer of the interlayer dielectric layers and connecting the first metal routing layer and an additional metal routing layer of the stack of metal routing layers, the additional metal routing layer being disposed on an opposite side of the first metal routing layer from the second metal routing layer, the second filament via comprising a conductive metal filament of a cluster of metal dots abutting the third interlayer dielectric layer,
wherein the first filament via and the second filament via are vertically stacked at opposite sides of the first metal routing layer
Haimoto et al., however, in Figs. 3C (orientation is inverted), 19A and 19B, further discloses a second filament via (16; paragraph 67) disposed through a third interlayer dielectric layer (12; paragraph 52) of the interlayer dielectric layers (12 in Fig. 19B and 12 in adjacent cell in Fig. 19B) and connecting the first routing layer (13; paragraph 47) and an additional metal routing layer (11; paragraph 49) of the stack of routing layers (11 and 13), the additional metal routing layer (11) being disposed on an opposite side (lower side) of the first metal routing layer (13) from the second metal routing layer (15; paragraph 49), the second filament via (16) comprising a conductive metal filament (conductive filament; paragraph 61) of a cluster of metal dots (metal ions; paragraph 61) abutting the third interlayer dielectric layer (12),
wherein the first filament via (17; paragraph 67) and the second filament via (16) are vertically stacked at opposite sides (upper and lower sides) of the first metal routing layer (13).
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It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Baek et al. in view of Haimoto et al. in view of Wang et al. in view of Hall et al., as applied to claim 34, with the further disclosure of Haimoto et al. to have made a second filament via disposed through a third interlayer dielectric layer of the interlayer dielectric layers and connecting the first routing layer and an additional metal routing layer of the stack of routing layers, the additional metal routing layer being disposed on an opposite side of the first metal routing layer from the second metal routing layer, the second filament via comprising a conductive metal filament of a cluster of metal dots abutting the third interlayer dielectric layer,
wherein the first filament via and the second filament via are vertically stacked at opposite sides of the first metal routing layer in order to increase tolerance of the resistance value of the device (paragraph 57 of Haimoto et al.).
Since Baek et al. discloses the first metal routing layer, Baek et al. in view of Haimoto et al. would disclose a second filament via disposed through a third interlayer dielectric layer of the interlayer dielectric layers and connecting the first metal routing layer and an additional metal routing layer of the stack of metal routing layers, the additional metal routing layer being disposed on an opposite side of the first metal routing layer from the second metal routing layer, the second filament via comprising a conductive metal filament of a cluster of metal dots abutting the third interlayer dielectric layer
Claim 37: Baek et al. in view of Haimoto et al. in view of Wang et al. in view of Hall et al. discloses the integrated chip according to claim 34, and Baek et al. further discloses wherein the non-filament via (35a) comprises a continuous unitary body
Baek et al. in view of Haimoto et al. in view of Wang et al. in view of Hall et al., as applied to claim 34, appears not to explicitly disclose the non-filament via comprises a continuous unitary metal body separated from the second interlayer dielectric layer by a barrier layer.
Hall et al., however, in Fig. 3, further discloses the non-filament via (left 136 and left 138; paragraph 44) comprises a continuous unitary metal body (left 136) separated from the second interlayer dielectric layer (134; paragraph 43) by a barrier layer (left 138).
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Baek et al. in view of Haimoto et al. in view of Wang et al. in view of Hall et al., as applied to claim 34, with the further disclosure of Hall et al. to have made the non-filament via comprises a continuous unitary metal body separated from the second interlayer dielectric layer by a barrier layer in order to have good conductivity while protecting the surrounding elements.
Claim 38: Baek et al. in view of Haimoto et al. in view of Wang et al. in view of Hall et al. discloses the integrated chip according to claim 34, and Baek et al., in Fig. 4 and in paragraphs 39 and 40, further discloses wherein adjacent ones of the metal routing lines (adjacent 25) within a given one of the metal routing layers (25, 29 and 37) are spaced apart from one another by a lithographic pitch (distance between adjacent 25), and a width (width of conductive filament) of the first filament via (conductive filament) is a sub-lithographic width (difference between the distance between adjacent 25 and the width of conductive filament) smaller than a minimum feature size (distance between adjacent 25) corresponding to the lithographic pitch (distance between adjacent 25).
Claim 39: Baek et al. in view of Haimoto et al. in view of Wang et al. in view of Hall et al. discloses the integrated chip according to claim 34, and Baek et al., in Fig. 4 and in paragraphs 39 and 40, further discloses wherein the first filament via (conductive filament) interfaces with a first metal routing line (left 25) of the first metal routing layer (25) and a second metal routing line (left 29) of the second metal routing layer (29) without an intervening electrode layer between the first filament via (conductive filament) and either of the first and second metal routing lines (left 25 and left 29).
Claim(s) 40-42 and 45-47 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baek et al. (U.S. Pub. 2006/0054950) in view of Haimoto et al. (U.S. Pub. 2012/0211719) in view of Jeong et al. (U.S. Pub. 2009/0020745) in view of Wang et al. (U.S. Pub. 2014/0353566) in view of Hall et al. (U.S. Pub. 2003/0143800).
Claim 40: Baek et al. discloses an integrated chip, in Fig. 1, comprising:
a first metal line (left 25; paragraph 27) and a second metal line (right 25; paragraph 27) of an upper metal routing layer (25; paragraph 27) surrounded by an upper dielectric layer (31; paragraph 36);
a second filament via (conductive filament; paragraphs 39 and 40) disposed between and electrically connecting the second metal line (right 25) of the upper metal routing layer (25) and a third metal routing layer (right 29; paragraph 27) stacked over the upper metal routing layer (25); and
a non-filament metal via (35b; paragraph 37) surrounded by an inter-level dielectric (ILD) layer (33; paragraph 36) and disposed over the third metal routing layer (right 29), the non-filament metal via (35b) being a continuous unitary body devoid of discrete conductive metal filaments.
Baek et al. appears not to explicitly disclose
a first metal line and a second metal line of a lower metal routing layer disposed over a substrate;
a filament dielectric layer of a low-k dielectric material disposed over and abutting the lower metal routing layer;
the first metal line and the second metal line of the upper metal routing layer disposed over the filament dielectric layer;
a first filament via disposed through the filament dielectric layer and electrically connecting the first metal line of the lower metal routing layer and the first metal line of the upper metal routing layer, and
the first filament via comprising conductive metal filaments of clusters of metal dots abutting the filament dielectric layer and abutting the metal lines that the first filament via connect, the first filament via having a first width and the second filament via having a second width different from the first width.
Haimoto et al., however, in Figs. 3C (orientation is inverted), 19A and 19B, discloses
a first metal line (11 in Fig. 19B; paragraph 49) and a second metal line (11 in adjacent cell in Fig. 19B; paragraph 49) of a lower metal routing layer (11; paragraph 49) disposed over a substrate (61; paragraph 209);
a filament dielectric layer (12; paragraph 52) disposed over and abutting the lower metal routing layer (11);
the first line (13 in Fig. 19B; paragraph 47) and the second line (13 in adjacent cell in Fig. 19B; paragraph 47) of the upper routing layer (13) disposed over the filament dielectric layer (12); and
a first filament via (16; paragraph 67) disposed through the filament dielectric layer (12) and electrically connecting the first metal line (11 in Fig. 19B) of the lower metal routing layer (11) and the first line (13 in Fig. 19B) of the upper metal routing layer (13).
the first filament via (16) comprising conductive metal filaments (conducive filament; paragraph 61) of clusters of metal dots (metal ions; paragraph 61) abutting the filament dielectric layer (12) and abutting the metal lines (11 in Fig. 19B and 13 in Fig. 19B) that the first filament via (16) connect, the first filament via (16) having a first width (width of 16 adjacent to 11) and the second filament via (17; paragraph 67) having a second width (width adjacent to 13) different from the first width.
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It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Baek et al. with the disclosure of Haimoto et al. to have made a first metal line and a second metal line of a lower metal routing layer disposed over a substrate;
a filament dielectric layer of a low-k dielectric material disposed over and abutting the lower metal routing layer;
the first line and the second line of the upper routing layer disposed over the filament dielectric layer; and
a first filament via disposed through the filament dielectric layer and electrically connecting the first metal line of the lower metal routing layer and the first line of the upper routing layer, and
the first filament via comprising conductive metal filaments of clusters of metal dots abutting the filament dielectric layer and abutting the metal lines that the first filament via connect, the first filament via having a first width and the second filament via having a second width different from the first width in order to increase tolerance of the resistance value of the device (paragraph 57 of Haimoto et al.).
Since Baek et al. discloses the first metal line and the second metal line of the upper metal routing layer, Baek et al. in view of Haimoto et al. would disclose the first metal line and the second metal line of the upper metal routing layer disposed over the filament dielectric layer; and
a first filament via disposed through the filament dielectric layer and electrically connecting the first metal line of the lower metal routing layer and the first metal line of the upper metal routing layer.
Baek et al. in view of Haimoto et al. appears not to explicitly disclose the first metal line and the second metal line of the lower metal routing layer surrounded by a lower dielectric layer.
Jeong et al., however, in Fig. 10, discloses the first metal line (left 61’; paragraph 60) and the second metal line (right 61’; paragraph 60) of the lower metal routing layer (61’; paragraph 60) surrounded by a lower dielectric layer (79; paragraph 78)
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Baek et al. in view of Haimoto et al. with the disclosure of Jeong et al. to have made the first metal line and the second metal line of the lower metal routing layer surrounded by a lower dielectric layer in order to protect the surrounding elements.
Baek et al. in view of Haimoto et al. in view of Jeong et al. also appears not to explicitly disclose the filament dielectric layer of a low-k dielectric material.
Wang et al., however, in Fig. 3A, discloses the filament dielectric layer (322; paragraphs 41 and 42) is a low-k dielectric material (low-k dielectric layer).
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Baek et al. in view of Haimoto et al. in view of Jeong et al. with the disclosure Wang et al. to have made the filament dielectric layer a low-k material in order to use less power to set and reset (paragraph 41 of Wang et al.).
Baek et al. appears not to explicitly disclose the non-filament metal via being a continuous unitary metal body.
Hall et al., however, in Fig. 3, discloses the non-filament metal via (left 136; paragraph 44) being a continuous unitary metal body (left 136).
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Baek et al. with the disclosure of Hall et al. to have made the non-filament metal via a continuous unitary metal body in order to have good conductivity.
Claim 41: Baek et al. in view of Haimoto et al. in view of Jeong et al. in view of Wang et al. in view of Hall et al. discloses the integrated chip according to claim 40.
Baek et al. in view of Haimoto et al. in view of Jeong et al. in view of Wang et al. in view of Hall et al., as applied to claim 40, appears not to explicitly disclose wherein the non-filament metal via is lined along a sidewall thereof by a barrier layer that separates the non-filament metal via from the ILD layer.
Hall et al., however, in Fig. 3, further discloses the non-filament metal via (left 136; paragraph 44) is lined along a sidewall (sidewall of left 136) thereof by a barrier layer (left 138; paragraph 44) that separates the non-filament metal via (left 136) from the ILD layer (134; paragraph 43).
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Baek et al. in view of Haimoto et al. in view of Jeong et al. in view of Wang et al. in view of Hall et al., as applied to claim 40, with the further disclosure of Hall et al. to have made the non-filament metal via is lined along a sidewall thereof by a barrier layer that separates the non-filament metal via from the ILD layer in order to protect the surrounding elements.
Claim 42: Baek et al. in view of Haimoto et al. in view of Jeong et al. in view of Wang et al. in view of Hall et al. discloses the integrated chip according to claim 40.
Baek et al. in view of Haimoto et al. in view of Jeong et al. in view of Wang et al. in view of Hall et al., as applied to claim 40, appears not to explicitly disclose wherein the non-filament metal via is a supervia extending through more than one dielectric layer so as to span multiple metal routing layers of an interconnect structure.
Hall et al., however, in Fig. 3, further discloses the non-filament metal via (second from left 136; paragraph 44) is a supervia (second from left 136) extending through more than one dielectric layer (126 and 134; paragraphs 43 and 47) so as to span multiple metal routing layers (124 and 128; paragraph 47) of an interconnect structure (structure shown in Fig. 3).
Accordingly, it would have been obvious to one of ordinary skill in the art to substitute the further disclosure of Hall et al. that is in the same field of endeavor with Baek et al. in view of Haimoto et al. in view of Jeong et al. in view of Wang et al. in view of Hall et al., as applied to claim 40, before the effective filing date of the claimed invention in order to substitute the non-filament metal via is a supervia extending through more than one dielectric layer so as to span multiple metal routing layers of an interconnect structure as further disclosed by Hall et al. for the non-filament metal via disclosed by Baek et al. in view of Haimoto et al. in view of Jeong et al. in view of Wang et al. in view of Hall et al., as applied to claim 40. The substituted components were known in the art, one of ordinary skill could have substituted the elements, and the simple substitution of the non-filament metal via is a supervia extending through more than one dielectric layer so as to span multiple metal routing layers of an interconnect structure further disclosed by Hall et al. for the non-filament via disclosed by Baek et al. in view of Haimoto et al. in view of Jeong et al. in view of Wang et al. in view of Hall et al., as applied to claim 40, would have yielded predictable results, namely providing a suitable electrical connection within the structure. (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Claim 45: Baek et al. in view of Haimoto et al. in view of Jeong et al. in view of Wang et al. in view of Hall et al. discloses the integrated chip according to claim 40.
Baek et al. in view of Haimoto et al. in view of Jeong et al. in view of Wang et al. in view of Hall et al., as applied to claim 40, appears not to explicitly disclose further comprising a third filament via disposed through the filament dielectric layer and electrically connecting the second metal line of the lower metal routing layer and the second metal line of the upper metal routing layer, the third filament via comprising a conductive metal filament of a cluster of metal dots abutting the filament dielectric layer.
Haimoto et al., however, in Figs. 3C (orientation is inverted), 19A and 19B, further discloses a third filament via (16 in adjacent cell in Fig. 19B) disposed through the filament dielectric layer (12; paragraph 52) and electrically connecting the second metal line (11 in adjacent cell in Fig. 19B; paragraph 49) of the lower metal routing layer (11; paragraph 49) and the second metal line (13 in adjacent cell in Fig. 19B; paragraph 47) of the upper metal routing layer (13; paragraph 47), the third filament via (16) comprising a conductive metal filament (conductive filament; paragraph 61) of a cluster of metal dots (metal ions; paragraph 61) abutting the filament dielectric layer (12).
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It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Baek et al. in view of Haimoto et al. in view of Jeong et al. in view of Wang et al. in view of Hall et al., as applied to claim 40, with the further disclosure of Haimoto et al. to have made a third filament via disposed through the filament dielectric layer and electrically connecting the second metal line of the lower metal routing layer and the second metal line of the upper metal routing layer, the third filament via comprising a conductive metal filament of a cluster of metal dots abutting the filament dielectric layer in order to increase tolerance of the resistance value of the device (paragraph 57 of Haimoto et al.).
Claim 46: Baek et al. in view of Haimoto et al. in view of Jeong et al. in view of Wang et al. in view of Hall et al. discloses the integrated chip according to claim 40, and Baek et al., in Fig. 4 and in paragraphs 39 and 40, further discloses wherein the first width (width of conductive filament) of the first filament via (conducive filament) is a sub-lithographic width (difference between the distance between adjacent 25 and the width of conductive filament) smaller than a minimum feature size (distance between adjacent 25) defined by a lithographic pitch (distance between adjacent 25) of an interconnect structure (structure in Fig. 4).
Claim 47: Baek et al. in view of Haimoto et al. in view of Jeong et al. in view of Wang et al. in view of Hall et al. discloses the integrated chip according to claim 40,
Baek et al. in view of Haimoto et al. in view of Jeong et al. in view of Wang et al. in view of Hall et al., as applied to claim 40, appears not to explicitly disclose wherein the first filament via interfaces with the first metal line of the lower metal routing layer and the first metal line of the upper metal routing layer without an intervening electrode layer between the first filament via and either of the first metal lines.
Haimoto et al., however, in Figs. 3C (orientation is inverted), 19A and 19B, further discloses the first filament via (16; paragraph 67) interfaces with the first metal line (11 in Fig. 19B; paragraph 49) of the lower metal routing layer (11; paragraph 49) and the first metal line (13 in Fig. 19B; paragraph 47) of the upper metal routing layer (13; paragraph 47) without an intervening electrode layer between the first filament via (16) and either of the first metal lines (11 in Fig. 19B and 13 in Fig. 19B).
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Baek et al. in view of Haimoto et al. in view of Jeong et al. in view of Wang et al. in view of Hall et al., as applied to claim 40, with the further disclosure of Haimoto et al. to have made the first filament via interfaces with the first metal line of the lower metal routing layer and the first metal line of the upper metal routing layer without an intervening electrode layer between the first filament via and either of the first metal lines in order to increase tolerance of the resistance value of the device (paragraph 57 of Haimoto et al.).
Allowable Subject Matter
Claim 36 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art of record, either singularly or in combination, does not suggest, in combination with the other claim limitations, a supervia extending through more than one of the interlayer dielectric layers and connecting a metal routing line of the first metal routing layer and a metal routing line of the third metal routing layer so as to span the second metal routing layer therebetween, the supervia being laterally spaced apart from the first filament via and the non-filament via, and vertically stacked over the third filament via, as required by claim 36.
Claims 28-33, 43 and 44 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
The prior art of record, either singularly or in combination, does not suggest, in combination with the other claim limitations, a first filament dielectric layer of a low-k dielectric material disposed over and abutting the first metal routing layer;
a second metal routing layer disposed over and abutting the first filament dielectric layer and surrounded by a second dielectric layer; and
a second filament dielectric layer of the low-k dielectric material disposed over and abutting the second metal routing layer, as required by claim 28.
Claims 29-33 depends either directly or indirectly from independent claim 28, and would be allowable for the same reason.
The prior art of record, either singularly or in combination, does not suggest, in combination with the other claim limitations, the supervia abuts the first metal line of the upper metal routing layer and a metal line of an additional metal routing layer disposed above the third metal routing layer, as required by claim 43.
Claim 44 depends from claim 43, and would be allowable for the same reason.
Response to Arguments
Applicant’s arguments with respect to claim(s) 34, 35, 37-42 and 45-47 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant’s arguments with respect to claim(s) 28-33 and 36 have been considered but are moot because they rejected under 35 USC § 112.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN LIN whose telephone number is (571)270-1274. The examiner can normally be reached Monday-Friday 10am-6pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/J.L/ Examiner, Art Unit 2815
/JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815
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