DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Species 2, as shown in FIGs. 13-14 has been elected.
Amendment filed July 06, 2026 is acknowledged. New claims 23-25 have been added. Claims 8, 18 and 21 have been cancelled. Claims 1, 10 and 20 have been amended. Claims 1-6, 9-16, 19-20 and 22-25 are pending.
Action on merits of claims 1-6, 9-16, 19-20 and 22-25 follows.
Drawings
The drawings were received on July 06, 2026. These drawings are acceptable.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim 1-4, 6, 9-13, 15-16, 19, 22 and 24-25 are rejected under 35 U.S.C. 103 as obvious over PARK et al. (US. Patent No. 9,991,257) in view of BRUECK et al. (US Patent No. 9,142,400) and MEADA et al. (US. Pub. No. 2014/0203370) all of record.
With respect to claim 1, As best understood by the Examiner, PARK teaches a semiconductor device substantially as claimed including:
an isolation insulating layer (135) disposed over a substrate (101);
a first fin structure (120) and a second fin structure (120), both disposed over the substrate, the first and second fin structures (120) extending in a first direction (X);
a gate structure (140) disposed over parts of the first and second fin structures (120), the gate structure extending in a second direction (Y) crossing the first direction (X);
a source/drain structure including a first part (127b) disposed on the first fin structure (120) and a second part (127b) disposed on the second fin structure (120), the first part (127b) contacting the second part (127b);
a dielectric layer (150f) disposed on and fully covering an entire upper surface of the isolation insulating layer (135);
a void (AG) enclosed by the source/drain structure and the dielectric layer (151F);
a silicide layer (191) formed over and surrounding the source/drain structure; and
an interlayer dielectric layer (160) disposed over the silicide layer (191), wherein:
the first and second fin structures (120) not covered by the gate structure (140) are recessed below a top of the dielectric layer (150f),
the source/drain structure is formed over the recessed first and second fin structures (120),
the dielectric layer (151F) includes a middle portion that is a single continuous layer formed by a first portion, a second portion and a center portion, the first portion is formed directly on a bottom of the source/drain structure disposed over the first fin structure (120), the second portion is formed directly on a bottom of the source/drain structure disposed over the second fin structure (120) and the center portion is formed directly on an upper surface of the isolation insulating layer (130) between the first fin structure (120) and the second fin structure (120) and connecting the first portion and the second portion,
the first portion and the second portion protrude from the center portion in a third direction (Z) crossing the first (X) and second (Y) directions, and the source/drain structure is disposed over and in contact with an entire uppermost surface of the first portion and the second portion of the dielectric layer (151F) along the second direction (Y),
the uppermost surface of the first portion and second portion of the dielectric layer (151F) extends on the substrate along the second direction (Y),
the source/drain structure includes an upper part disposed on a lower part, and the upper part and the lower part form a first angle and a second angle where the upper part and lower part meet at opposing sides of the source/drain structure along the second direction (Y),
the silicide layer (191) is formed on the upper part of the source/drain structure, and
a height of the void (AG) extending along the third direction (Z) from an uppermost surface of the center portion (151F) of the dielectric layer to the source/drain structure (127b). (See FIGs. 1-3A).
Thus, PARK is shown to teach all the features of the claim with the exception of explicitly disclosing the height of the void ranging from 20 nm to 35 nm; the uppermost surface of the first portion and second portion of the dielectric layer extends parallel to the substrate along the second direction; an etching stop layer disposed between and in contact with the silicide layer and the interlayer dielectric layer; the upper part and the lower part of the source/drain structure forms an obtuse angle; the silicide layer is formed on both the upper part and the lower part of the source/drain structure.
Note that, the claimed height of the void of 20 nm to 35 nm do not appear to be critical.
Although PARK does not explicitly disclosing the height of the void (AG) being in a range from 20 nm to 35 nm, however, PARK teaches that the height h1 of the dielectric layer (151F) disposed on the isolation insulating layer (135) is 30 nm or less.
Since the height of the void (AG) is directly related to the height (h1) of the dielectric layer (151F) on the sides of the fin structure during the epitaxially grow of the source/drain structure, thus, the height of the void (AG) in the range of 20 nm to 35 nm is more probable than not being formed.
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the void of PARK having the height in the range 20 nm to 35 nm due to the present of the sidewalls dielectric layer.
Moreover, it is well settled that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40 ºC and 80 ºC and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100 ºC and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages.").
Therefore, the height of the void (AG) can be easily optimized by the thickness h1 of the dielectric layer and the epitaxial layer via routine experimentation.
Further, BRUECK teaches a semiconductor device including:
a dielectric layer (14) disposed on and fully covering an entire upper surface of the underlayer (10), the dielectric layer (14) includes a middle portion that is a single continuous layer formed by a first portion (18 left), a second portion (18 right) and a center portion (middle), the first portion (18 left) is formed directly on a bottom of source/drain structure (20) disposed over the first fin structure (12, left), the second portion (18 right) is formed directly on a bottom of the source/drain structure (20) disposed over the second fin structure (12, right) and the center portion (middle) is formed directly on an upper surface of substrate between the first fin structure (12 left) and the second fin structure (12 right) and connecting the first portion (18 left) and the second portion (18 right), and
the uppermost surface of the first portion (18 left) and second portion (18 right) of the dielectric layer (14) extends parallel to the substrate along the second direction (L-R),
source/drain structure (20) includes an upper part disposed on a lower part, and the upper part and the lower part form a first obtuse angle (left) and a second obtuse angle (right) where the upper part and lower part meet at opposing sides of the source/drain structure along the second direction (L-R). (See FIG. 1E).
Therefore, it would have been obvious to one having ordinary skill in the art before the filling date of the claimed invention to form the dielectric layer of PARK having the uppermost surface of the first and second portions of the dielectric layer extends parallel to the substrate along the second direction as taught by BRUECK for the same intended purpose of blocking defects such as stacking faults, without departing from the scope of either.
Regarding the claimed “obtuse angle”, there is no teaching of the “obtuse angle” of the epitaxial layer in the instant application. The so call “obtuse angle” is based on drawings, which are not drawn to scale.
PROPORTIONS OF FEATURES IN A DRAWING ARE NOT EVIDENCE OF ACTUAL PROPORTIONS WHEN DRAWINGARE NOT TO SCALE.
“ When the reference, in this case the application, does not disclose that the drawings are to scale and is silent as to dimensions, argument based on measurement of the drawing features are of little value. See Hockerson-Halberstadt, Inc. v. Avia Group Int’l, 222 F.3d 951, 956, 55 USPQ2d 1487, 1491 (Fed Cir. 2000).
Further, MEADA teaches a semiconductor device including:
a silicide layer (262) formed over and surrounding a source/drain structure (261);
an interlayer dielectric layer (271) disposed over the silicide layer (262); and
an etching stop layer (265) disposed over an uppermost part of the source/drain structure (261) and between and in contact with the silicide layer (262) and the interlayer dielectric layer (271), wherein
the source/drain structure (261) includes an upper part disposed on a lower part, and the upper part and the lower part form a first obtuse angle (left) and a second obtuse angle (right) where the upper part and lower part meet at opposing sides of the source/drain structure (262) along the second direction (x),
the silicide layer (262) is formed on both the upper part and the lower part of the source/drain structure (261), and
the etching stop layer (265) is disposed over both the upper part and the lower part of the source/drain structure. (See FIGs. 11, 14).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the semiconductor device of PARK having the silicide layer being formed on both the upper part and the lower part of the source/drain structure; and the etch stop layer being formed between the interlayer dielectric layer and the silicide layer and over both the upper part and the lower part of the source/drain structure as taught by MEADA to protect the silicide layer.
With respect to claim 10, As best understood by the Examiner, PARK teaches a semiconductor device substantially as claimed including:
an isolation insulating layer (130) disposed over a substrate (101);
a first fin structure (120, left), a second fin structure (120, middle) and a third fin structure (120, right), which are disposed over the substrate (101), the first, second and third fin structures (120) extending in a first direction (X);
a source/drain structure (127) disposed over the first, second and third fin structures (120);
a dielectric layer (150F) comprising a first part (151F left) disposed on an upper surface of the isolation insulating layer (130) between the first fin structure (120, left) and the second fin structure (120, middle) and contacting a first face of the first fin structure (120, left) and a first face of the second fin structure (120, right), a second part (151F right) disposed on the upper surface of the isolation insulating layer (130) between the second fin structure (120, middle) and the third fin structure (120, right) and contacting a second face of the second fin structure (120, middle) opposite to the first face of the second fin structure (120, middle) and a first face of the third fin structure (120, right), a third part (153F left) covering an upper surface of the isolation insulating layer (130) and contacting a second face of the first fin structure (120, left) opposite to the first face of the first fin structure (120, left), and a fourth part (153F right) covering an upper surface of the isolation insulating layer (130) and contacting a second face of the third fin structure (120, right) opposite to the first face of the third fin structure (120, right);
a first void (AG) is formed between the source/drain structure (127) and the first part (151F left) of the dielectric layer (150F);
a second void (AG) is formed between the source/drain structure (127) and the second part (151F right) of the dielectric layer (150F); and
a silicide layer (191) formed over and surrounding the source/drain structure (127); and
an interlayer dielectric layer (165) disposed over a gate structure (140) and the source/drain structure (127), wherein:
the first part (151F) of the dielectric layer is a single continuous layer formed by a first portion, a second portion and a first center portion, the first portion (151F) is formed directly on a bottom of the source/drain structure (127) disposed over the first fin structure (120, left), the second portion is formed directly on a bottom of the source/drain structure disposed over the second fin structure (120, middle) and the first center portion is formed directly on an upper surface of the isolation insulating layer (130) between the first fin structure (120, left) and the second fin structure (120, middle) and connecting the first portion and the second portion,
the first portion and the second portion extend from the first center portion in a direction (Z) away from the substrate (101),
the second part (151F) of the dielectric layer is a single continuous layer formed by a third portion, a fourth portion and a second center portion, the third portion is formed directly on a bottom of the source/drain structure (127) disposed over the second fin structure (120, middle), the fourth portion is formed directly on a bottom of the source/drain structure disposed over the third fin structure (120, left) and the second center portion disposed directly on an upper surface of the isolation insulating layer (130) between the second fin structure (120, middle) and the third fin structure (120, left) and connecting the third portion and the fourth portion,
the third portion and the fourth portion extend from the second center portion in a direction (Z) away from the substrate (101),
the source/drain structure (127) is disposed over and in contact with an entire uppermost surface of the first portion, the second portion, third portion, and the fourth portion as seen in cross section,
the source/drain structure (127) includes an upper part disposed on a lower part, and the upper part and the lower part form a first angle (left) and a second angle (right) where the upper part and lower part meet at opposing sides of the source/drain structure along the second direction (Y),
the silicide layer (191) is formed on the upper part of the source/drain structure, and
a largest width of the source/drain structure along a second direction (Y) and parallel to a surface of the substrate (101) is located at a level below a level of a highest portion of the first, second and third fin structures (120),
a height of the first void (AG) extending along the direction (z) away from substrate (101) from an uppermost surface of the first center portion (151F) of the dielectric layer (150) to the source/drain structure (127), and
a height of the second void (AG) extending along the direction (z) away from substrate (101) from an uppermost surface of the second center portion (151F) of the dielectric layer (150) to the source/drain structure (261). (See FIGs. 1-3A).
Thus, PARK is shown to teach all the features of the claim with the exception of explicitly disclosing the height of the first and second voids being in a range of 20 nm to 35nm; an etching stop layer disposed directly between and in contact with the silicide layer and the interlayer dielectric layer and over both the upper part and the lower part of the source/drain structure; the upper part and the lower part of the source/drain structure forms an obtuse angle; and the silicide layer is formed on both the upper part and the lower part of the source/drain structure.
Note that, the claimed height of the voids of 20 nm to 35 nm do not appear to be critical.
Although PARK does not explicitly disclosing the height of the voids (AG) being in a range from 20 nm to 35 nm, however, PARK teaches that the height h1 of the dielectric layer (151F) disposed on the isolation insulating layer (135) is 30 nm or less. Since the height of the void (AG) is directly related to the height (h1) of the dielectric layer (151F) on the sides of the fin structure during the epitaxially grow of the source/drain structure, thus, the height of the voids (AG) in the range of 20 nm to 35 nm is more probable than not being formed.
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the void of PARK having the height in the range 20 nm to 35 nm due to the present of the sidewalls dielectric layer.
Moreover, it is well settled that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40 ºC and 80 ºC and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100 ºC and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages.").
Therefore, the height of the void (AG) can be easily optimized by the thickness h1 of the dielectric layer and the epitaxial layer via routine experimentation.
Further, BRUECK teaches a semiconductor device including:
a source/drain structure (20) includes an upper part disposed on a lower part, and the upper part and the lower part form a first obtuse angle (left) and a second obtuse angle (right) where the upper part and lower part meet at opposing sides of the source/drain structure (20) along the second direction (L-R). (See FIG. 1E).
Therefore, it would have been obvious to one having ordinary skill in the art before the filling date of the claimed invention to form the source/drain structure of PARK having the upper part and the lower part forming the first and second obtuse angles along the second direction as taught by BRUECK for the same intended purpose providing the source/drain structure.
Regarding the “obtuse angle”, there is no teaching of the “obtuse angle” of the epitaxial layer. The so call “obtuse angle” is based on drawings, which are not drawn to scale.
PROPORTIONS OF FEATURES IN A DRAWING ARE NOT EVIDENCE OF ACTUAL PROPORTIONS WHEN DRAWINGARE NOT TO SCALE.
“ When the reference, in this case the application, does not disclose that the drawings are to scale and is silent as to dimensions, argument based on measurement of the drawing features are of little value. See Hockerson-Halberstadt, Inc. v. Avia Group Int’l, 222 F.3d 951, 956, 55 USPQ2d 1487, 1491 (Fed Cir. 2000).
Further, MEADA teaches a semiconductor device including:
a silicide layer (262) formed over and surrounding a source/drain structure (261);
an interlayer dielectric layer (271) disposed over the silicide layer (262); and
an etching stop layer (265) disposed directly between and in contact with the silicide layer (262) and the interlayer dielectric layer (271), wherein
the source/drain structure (261) includes an upper part disposed on a lower part, and the upper part and the lower part form a first obtuse angle (left) and a second obtuse angle (right) where the upper part and lower part meet at opposing sides of the source/drain structure (262) along the second direction (x2),
the silicide layer (262) is formed on both the upper part and the lower part of the source/drain structure (261). (See FIGs. 11, 14).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the semiconductor device of PARK having the silicide layer being formed on both the upper part and the lower part of the source/drain structure; and the etch stop layer being formed between the interlayer dielectric layer and the silicide layer and over both the upper part and the lower part of the source/drain structure as taught by MEADA to protect the silicide layer.
With respect to claims 2 and 11, the dielectric layer (151F) of PARK is formed of silicon nitride.
With respect to claim 3, the dielectric layer (151F) of PARK, or 14 of BRUECK, comprises a sleeve shape that covers the bottom of the source/drain structure disposed over the first fin structure (120 left).
With respect to claims 4 and 13, the source/drain structure (127) of PARK includes an epitaxial semiconductor layer and a part of the epitaxial semiconductor layer is disposed in the sleeve shape.
With respect to claim 6, the semiconductor device of PARK further comprises:
an interlayer dielectric layer (170) disposed over first gate structure (140) and the source/drain structure; and
a contact plug (190) formed in the interlayer dielectric layer (170) and connected to the silicide layer (191).
With respect to claim 9, the dielectric layer (150F) of PARK (or 14 of BRUECK) is in contact with the first (left) and second (right) fin structures.
With respect to claim 12, each of the first part (151F left) and the second part (151F right) of the dielectric layer (151F) of PARK comprises a sleeve shape.
With respect to claim 15, the semiconductor device of PARK further comprises a gate structure (140) disposed over channel regions of the first, second and third fin structures (120).
With respect to claim 16, the semiconductor device of PARK further comprises
a contact plug (190) formed in the interlayer dielectric layer (165) and connected to the silicide layer (191).
With respect to claim 19, the first part (151F left) of the dielectric layer of PARK is in contact with the first and second fin structures (120), and the second part (151F right) of the dielectric layer is in contact with the second and third fin structures (120).
With respect to claim 22, the largest width of the source/drain structure (127) along a second direction of PARK is at a level vertices of the first obtuse angle and the second obtuse angle, in view of BRUECK. (See the “obtuse angle” above”).
Claims 5 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over PARK ‘257, BRUECK ‘400 and MEADA ‘370 as applied to claims 1 and 10 above, and further in view of LEE et al. (US. Patent No. 7,074,662) of record.
PARK, in view of BRUECK and MEADA, teaches the semiconductor device as described in claims 1 and 10 above including the center portion of the dielectric layer (150) has a thickness of 8 nm to 15 nm.
Thus, PARK, BRUECK and MEADA are shown to teach all the features of the claim with the exception of explicitly disclosing the center portion having a thickness of 30 nm to 70 nm.
However, LEE ‘662 teaches a semiconductor device including:
a dielectric layer (24a) includes a middle portion that is a single continuous layer formed by a first portion (spacer), a second portion (spacer) and a center portion (horizontal portion), wherein the center portion has a thickness in a range from 10 nm to 40 nm, thus, overlaps the claimed range of 30 to 70 nm. (See FIG. 13D).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the center portion of the dielectric layer of PARK having the thickness as taught by LEE for the same intended purpose of protecting the isolation insulation layer from etching.
It is well settled that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40 ºC and 80 ºC and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100 ºC and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages.").
Therefore, the thickness of the center portion of PARK, in view of LEE, can be easily optimize through a routine experimentation.
Claims 24-25 are rejected under 35 U.S.C. 103 as being unpatentable over PARK ‘257, BRUECK ‘400 and MEADA ‘370 as applied to claims 1 and 10 above, and further in view of YU et al. (US. Patent No. 9,324,713) of record.
PARK, in view of BRUECK and MEADA, teaches the semiconductor device as described in claims 1 and 10 above including a height of the first (151F left) and second (151F right) portions of the dielectric layer (151F) from an upper surface of the center portion (horizontal portion).
Thus, PARK, BRUECK and MEADA are shown to teach all the features of the claim with the exception of explicitly disclosing the heights are in a range from 1 nm to 10 nm.
However, YU ‘713 teaches a semiconductor device including:
a dielectric layer (1401) formed by a first portion (sleeve), a second portion (sleeve) and a center portion, wherein a height of the first and second portions of the dielectric layer (1401) from an upper surface of the center portion is in a range from 5 nm to 20 nm, thus overlapping the range of 1 nm to 10 nm. (See FIG. 13, Col. 2, 65-67).
Therefore, it would have been obvious to one having ordinary skill in the art before the filling date of the claimed invention to form the first and second portions of the dielectric layer of PARK having the height as taught by YU so that the epitaxial layer can easily merged.
It is well settled that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40 ºC and 80 ºC and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100 ºC and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages.").
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over PARK ‘081 in view of BRUECK ‘400, MEADA 370 and YU ‘713, all of record.
With respect to claim 20, As best understood by the Examiner, PARK teaches a semiconductor device substantially as claimed including:
an isolation insulating layer (130) disposed over a substrate (101);
a first fin structure (120) and a second fin structure (120), both disposed over the substrate (101), the first and second fin structures (120) extending in a first direction (X);
a gate structure (140) disposed over parts of the first and second fin structures (120), the gate structure (140) extending in a second direction (Y) crossing the first direction (X);
a first source/drain epitaxial layer (127b) disposed over the first fin structure (120);
a second source/drain epitaxial layer (127b) disposed over the second fin structure (120);
a dielectric layer (151F) comprising a first portion, a second portion and a third portion made of a same material as the first portion and the second portion,
a silicide layer (191) surrounding the first source/drain epitaxial layer (127b) and the second source/drain epitaxial layer (127b); and
an interlayer dielectric layer (165) disposed over the source/drain epitaxial layer, wherein:
the first portion of the dielectric layer has a first sleeve shape and covers a bottom of the first source/drain epitaxial layer (127b),
the second portion of the dielectric layer has a second sleeve shape and covers a bottom of the second source/drain epitaxial layer (127b),
the third portion of the dielectric layer is disposed on an upper surface of the isolation insulating layer (130) between the first fin structure (120) and the second fin structure (120) and directly connecting the first portion and the second portion,
parts of the first and second fin structures (120) are recessed,
the first source/drain epitaxial layer (127b) merges with the second source/drain epitaxial layer (127b), thereby forming a merged source/drain structure,
the first source/drain epitaxial layer (127b) is formed over the recessed part of the first fin structure (120) and the second source/drain epitaxial layer (127b) is formed over the recessed part of the second fin structure (120),
a height of the first and second sleeve shape from an upper surface of the third portion,
the merged source/drain structure (127) is in direct contact with an entire uppermost surface (UL) of the first and second sleeve shape,
the uppermost surface (UL) of the first and second sleeve shape extends on the substrate along the second direction (Y),
a top of the merged source/drain epitaxial layer (127b) is located at a level between a top of the gate structure (140) and a top of the first and second fin structure (120) under the gate structure (140),
a largest width of the merged source/drain epitaxial layer (127b) is located at a level below a level of the top of the first and second fin structure (120) under the gate structure (140);
a void (AG) is enclosed by the merged source/drain structure and the dielectric layer,
the merged source/drain epitaxial layer includes an upper part disposed on a lower part, and the upper part and the lower part form a first angle (left) and a second angle (right) where the upper part and lower part meet at opposing sides of the merged source/drain epitaxial layer along the second direction (Y), and
the silicide layer (191) is formed on the upper part of the source/drain epitaxial layer, and
a height of the void (AG) extending along a third direction (Z) crossing the first direction (X) and the second direction (Y) from an uppermost surface of the third portion (151F) of the dielectric layer (150) to the merged source/drain structure (261). (See FIG. 1-3A).
Thus, PARK is shown to teach all the features of the claim with the exception of explicitly disclosing the height of the void being in a range of 20 nm and 35 nm; an etching stop layer disposed directly between and in contact with the silicide layer and the interlayer dielectric layer; the height of the first and second sleeve shape from an upper surface of the third portion is in a range from 1 nm to 10 nm; the uppermost surface of the first and second sleeve shape extends parallel to the substrate along the second direction; the upper part and the lower part of the source/drain structure forms an obtuse angle; and the silicide layer is formed on both the upper part and the lower part of the source/drain structure.
Note that, the claimed height of the void of 20 nm to 35 nm do not appear to be critical.
Although PARK does not explicitly disclosing the height of the void (AG) being in a range from 20 nm to 35 nm, however, PARK teaches that the height h1 of the dielectric layer (151F) disposed on the isolation insulating layer (135) is 30 nm or less. Since the height of the void (AG) is directly related to the height (h1) of the dielectric layer (151F) on the sides of the fin structure during the epitaxially grow of the source/drain structure, thus, the height of the voids (AG) in the range of 20 nm to 35 nm is more probable than not being formed.
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the void of PARK having the height in the range 20 nm to 35 nm due to the present of the sidewalls dielectric layer.
Moreover, it is well settled that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40 ºC and 80 ºC and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100 ºC and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages.").
Therefore, the height of the void (AG) can be easily optimized by the thickness h1 of the dielectric layer and the epitaxial layer via routine experimentation.
Further, BRUECK teaches a semiconductor device including:
a dielectric layer (18) comprising a first portion, a second portion and a third portion made of a same material as the first portion and the second portion, wherein:
the first portion of the dielectric layer (18) has a first sleeve shape and covers a bottom of the first source/drain epitaxial layer (20),
the second portion of the dielectric layer (18) has a second sleeve shape and covers a bottom of the second source/drain epitaxial layer (20),
the source/drain structure (20) is in direct contact with an entire uppermost surface of the first and second sleeve shape,
the uppermost surface of the first and second sleeve shape extends parallel to the substrate along the second direction (L-R),
the source/drain epitaxial layer (20) includes an upper part disposed on a lower part, and the upper part and the lower part form a first obtuse angle (left) and a second obtuse angle (right) where the upper part and lower part meet at opposing sides of the source/drain epitaxial layer along the second direction (L-R). (See FIG. 1E).
Therefore, it would have been obvious to one having ordinary skill in the art before the filling date of the claimed invention to form the dielectric layer of PARK having the uppermost surface of the first and second sleeve shape of the dielectric layer extends parallel to the substrate along the second direction as taught by BRUECK for the same intended purpose of blocking defects such as stacking faults, without departing from the scope of either.
Regarding the “obtuse angle”, there is no teaching of the “obtuse angle” of the epitaxial layer. The so call “obtuse angle” is based on drawings, which are not drawn to scale.
PROPORTIONS OF FEATURES IN A DRAWING ARE NOT EVIDENCE OF ACTUAL PROPORTIONS WHEN DRAWINGARE NOT TO SCALE.
“ When the reference, in this case the application, does not disclose that the drawings are to scale and is silent as to dimensions, argument based on measurement of the drawing features are of little value. See Hockerson-Halberstadt, Inc. v. Avia Group Int’l, 222 F.3d 951, 956, 55 USPQ2d 1487, 1491 (Fed Cir. 2000).
Further, MEADA teaches a semiconductor device including:
a silicide layer (262) formed over and surrounding a source/drain structure (261);
an interlayer dielectric layer (271) disposed over the silicide layer (262); and
an etching stop layer (265) disposed directly between and in contact with the silicide layer (262) and the interlayer dielectric layer (271), and
a source/drain epitaxial layer (261) includes an upper part disposed on a lower part, and the upper part and the lower part form a first obtuse angle (left) and a second obtuse angle (right) where the upper part and lower part meet at opposing sides of the source/drain structure (262) along the second direction (x2),
the silicide layer (262) is formed on both the upper part and the lower part of the source/drain epitaxial layer (261). (See FIGs. 11, 14).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the semiconductor device of PARK having the silicide layer being formed on both the upper part and the lower part of the source/drain structure; and the etch stop layer being formed between the interlayer dielectric layer and the silicide layer and over both the upper part and the lower part of the source/drain structure as taught by MEADA to protect the silicide layer.
Furthermore, YU teaches a semiconductor device including: a height of the first and second sleeve shape (1401) from an upper surface of the third portion is in a range from 5 nm to 20 nm, thus overlapping the range of 1 nm to 10 nm. (See FIG. 13, Col. 2, 65-67).
Therefore, it would have been obvious to one having ordinary skill in the art before the filling date of the claimed invention to form the sleeve shape of PARK having the height as taught by YU so that the epitaxial layer can easily merged.
It is well settled that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40 ºC and 80 ºC and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100 ºC and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages.").
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over PARK ‘257, BRUECK ‘400 and MEADA ‘370 and YU ‘713 as applied to claim 20 above, and further in view of LEE ‘662.
PARK, in view of BRUECK, MEADA and YU, teaches the semiconductor device as described in claim 20 above including the center portion of the dielectric layer (150) has a thickness of 8 nm to 15 nm.
Thus, PARK, BRUECK, MEADA and YU are shown to teach all the features of the claim with the exception of explicitly disclosing the center portion having a thickness of 30 nm to 70 nm.
However, LEE ‘662 teaches a semiconductor device including:
a dielectric layer (24a) includes a middle portion that is a single continuous layer formed by a first portion (spacer), a second portion (spacer) and a center portion (horizontal portion), wherein the center portion has a thickness in a range from 10 nm to 40 nm, thus, overlaps the claimed range of 30 to 70 nm. (See FIG. 13D).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the center portion of the dielectric layer of PARK having the thickness as taught by LEE for the same intended purpose of protecting the isolation insulation layer from etching.
It is well settled that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40 ºC and 80 ºC and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100 ºC and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages.").
Therefore, the thickness of the center portion of PARK, in view of LEE, can be easily optimize through a routine experimentation.
Response to Arguments
Applicant’s arguments with respect to amended and new claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ANH D MAI/Primary Examiner, Art Unit 2893
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