DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on August 19, 2025 has been entered.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
Claim 11 recites the limitation “the first dielectric layer has a first hardness after the FCVD process that corresponds with a first amount of scratch defects during the CMP process; and the treating the first dielectric layer with the aqueous oxidizer provides the treated portion of the first dielectric layer with a second hardness that is higher than the first hardness, wherein the second hardness corresponds with a second amount of scratch defects during the CMP process that is less than the first amount of scratch defects during the CMP process” in the claim language. There is no written support in Applicant’s original specification for this language.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 9-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claims 9, 15, and 20. Claim 9 recites the limitation “further comprising tuning parameters of the hardening of the portion of the first dielectric layer to increase the first hardness to the second hardness, wherein the second hardness is a given hardness that reduces scratch defects during the CMP process” in the claim language. Applicant does not written support in the originally filed specifications for further comprising tuning parameters of the hardening of the portion of the first dielectric layer to increase the first hardness to the second hardness.
Claims 15 and 20 are rejected for the same analogous reasons as claim 9 above.
Regarding claims 10 and 14. Claim 10 recites the limitation “an oxide liner of the isolation structure” in the third paragraph of the claim language.
Applicant does not have support in the originally filed specifications that the oxide liner is encompassed in the isolation structure. Applicant’s originally filed specifications in [0028] states, the substrate 202, the fins 204, and the isolation structure 206 may be similar to the substrate 102, the fins 106, and the dielectric layer 114 in FIG. 2G
Applicant’s does not have support in the originally filed specifications that the oxide liner is part of the isolation structure, i.e. the dielectric layer 114.
Claim 14 is rejected for the same analogous reasons as claim 10 above.
Claims 11-13, 15-20 are rejected for dependence upon a 112(a) rejected instance claim.
Regarding claims 11. Claim 11 recites the limitation “the first dielectric layer has a first hardness after the FCVD process that corresponds with a first amount of scratch defects during the CMP process; and the treating the first dielectric layer with the aqueous oxidizer provides the treated portion of the first dielectric layer with a second hardness that is higher than the first hardness, wherein the second hardness corresponds with a second amount of scratch defects during the CMP process that is less than the first amount of scratch defects during the CMP process” in the claim language.
Applicant does not written support in the originally filed specifications for the first dielectric layer has a first hardness after the FCVD process that corresponds with a first amount of scratch defects during the CMP process, a second amount of scratch defects during the CMP process that is less than the first amount of scratch defects during the CMP process.
Regarding claims 16. Claim 16 recites the limitation “the second dielectric layer is deposited by a second FCVD process and the second dielectric layer has a third hardness after the second FCVD process, wherein the third hardness is about 1.1 to about 1.5 times greater than the first hardness of the first dielectric layer after the first FCVD process” in the last paragraph of the claim language.
Applicant does not written support in the originally filed specifications for the second dielectric layer is deposited by a second FCVD process and the second dielectric layer has a third hardness after the second FCVD process, wherein the third hardness is about 1.1 to about 1.5 times greater than the first hardness of the first dielectric layer after the first FCVD process.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-6, 8-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1. Claim 1 recites the limitation "after the hardening of the first dielectric layer" in line 17 of claim 1. There is insufficient antecedent basis for this limitation in the claim.
Claims 2-6, 8, 21 are rejected for dependence on claim 1.
Regarding claim 2. Claim 2 recites the limitation "the hardening of the first dielectric layer" in claim 2. There is insufficient antecedent basis for this limitation in the claim.
Regarding claims 9, 15, and 20. Claim 9 recites the limitation “further comprising tuning parameters of the hardening of the portion of the first dielectric layer to increase the first hardness to the second hardness, wherein the second hardness is a given hardness that reduces scratch defects during the CMP process” in the claim language. It is unclear to the examiner as to what is encompassed by the limitation comprising tuning parameters of the hardening of the portion of the first dielectric layer. Applicant’s disclosure does not disclose tuning parameters nor what those tuning parameters are.
Claims 15 and 20 are rejected for the same analogous reasons as claim 9 above.
Regarding claims 10, 11 and 14. Claim 10 recites the limitation “performing a flowable chemical vapor deposition (FCVD) process” in the claim language.
It is unclear to the examiner as to what procedures are encompassed in the process of performing a flowable chemical vapor deposition (FCVD) process.
Claim 11 is rejected for the same analogous reason as claim 10 above.
Claim 14 is rejected for the same analogous reason as claim 10 above.
Claims 11-13, and 15-20 are rejected for dependence upon a 112(b) rejected instance claim.
Regarding claims 11. Claim 11 recites the limitation “the first dielectric layer has a first hardness after the FCVD process that corresponds with a first amount of scratch defects during the CMP process; and the treating the first dielectric layer with the aqueous oxidizer provides the treated portion of the first dielectric layer with a second hardness that is higher than the first hardness, wherein the second hardness corresponds with a second amount of scratch defects during the CMP process that is less than the first amount of scratch defects during the CMP process” in the claim language.
It is unclear how the first dielectric layer has a first hardness after the FCVD process that corresponds with a first amount of scratch defects during the CMP process when the untreated first dielectric has a first amount of defects during the CMP process when the untreated first dielectric is not touched by the chemical mechanical planarization process.
Regarding claim 14. Claim 14 recites the limitation "the hard masks disposed on the fins" at the end of the first paragraph of claim 14. There is insufficient antecedent basis for this limitation in the claim. Claim 14 also recites the limitation "the hard masks" in line 17 of the claim language. There is insufficient antecedent basis for this limitation in the claim.
Claims 15-20 are rejected for dependence upon a 112(b) rejected instance claim.
Regarding claims 16. Claim 16 recites the limitation “the second dielectric layer is deposited by a second FCVD process and the second dielectric layer has a third hardness after the second FCVD process, wherein the third hardness is about 1.1 to about 1.5 times greater than the first hardness of the first dielectric layer after the first FCVD process” in the last paragraph of the claim language.
It is unclear to the examiner has to how a first FCVD process will give you a first hardness and a third hardness after the second FCVD process wherein the third hardness is about 1.1 to about 1.5 times greater than the first hardness when applicant does not disclose the parameters of a first FCVD process will give you a first hardness and the parameters of a second FCVD process with give you a third hardness wherein the first hardness is different from the second hardness when the parameters for a FCVD process is the same for both.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 5, 9 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Peng et al (U.S. 2014/0231919), Tong et al (U.S. 2014/0353795), Pal et al (U.S. 2013/0115773), Zhao et al (U.S. 2015/0287611), and Wang et al (U.S. 2006/0252267).
Regarding claim 1. Peng et al discloses a method of forming a semiconductor device (FIG. 2-8), the method comprising:
providing a substrate (FIG. 2, item 20) and fins (FIG. 2, item 30B) over the substrate (FIG. 2, item 20), the fins (FIG. 2, item 30B) being interposed by trenches (FIG. 2, item 32A) and each of the fins (FIG. 2, item 30B) being capped by a hard mask layer (FIG. 2, item 24);
conformally depositing ([0011]) a oxide liner (FIG. 3, item 34; [0011], i.e. liner oxide 34 may be a thermal oxide (such as silicon dioxide)) over sidewalls of the fins (FIG. 2, item 30B)
forming a first dielectric layer (FIG. 4, item 36) over the oxide liner (FIG. 3, item 34) to fill the trenches (FIG. 5, item 32A), wherein the forming of the first dielectric layer (FIG. 4, item 36) includes a deposition step (FIG. 4, item 36) and an annealing step ([0014], an anneal step), wherein the first dielectric layer having a first hardness ([0012], i.e. Dielectric region 36 substantially fully fills trenches 32A; i.e. The filling methods may be selected from spin-on);
after the forming of the first dielectric layer (FIG. 4, item 36) including the deposition step (FIG. 4, item 36) and the annealing step ([0014]) and before performing a chemical mechanical planarization (CMP) (FIG. 7, [0017]) process on the first dielectric layer (FIG. 4, item 36),
hardening a portion ([0014], i.e. dielectric material 36 is solidified by a curing process separate from the anneal) of the first dielectric layer (FIG. 5, item 36) that is disposed over top surfaces (FIG. 5, top surfaces of item 30B) of the fins (FIG. 5, item 30B), resulting in a hardened portion ([0014], i.e. dielectric material 36 is solidified by a curing process) of the first dielectric layer ([0014], i.e. Referring to FIG. 5, an anneal step (represented by arrows 37) is performed on wafer 100. Dielectric material 36 is solidified as a result of the anneal)
wherein the hardened portion (FIG. 5, item 36) of the first dielectric layer (FIG. 5, item 36) has a second hardness higher ([0014], i.e. dielectric material 36 is solidified by a curing process separate from the anneal) than the first hardness (FIG. 4, item 36; [0012], i.e. Dielectric region 36 may include highly-flowable materials) and the non-hardened portion (FIG. 4, item 36; [0012], i.e. Dielectric region 36 may include highly-flowable materials) of the first dielectric layer (FIG. 4, item 36) has the first hardness (FIG. 4, item 36; [0012])
after the hardening of the first dielectric layer (FIG. 5, item 36), depositing a second dielectric layer (FIG. 6, item 38) over the hardened portion (FIG. 6, item 36) of the first dielectric layer (FIG. 6, item 36), wherein the second dielectric layer (FIG. 6, item 38) has a third hardness ([0016], i.e. In the deposition of dielectric region 38, the respective process gases may include tetraethylorthosilicate (TEOS)) higher ([0016], i.e. Dielectric regions 36 and 38, after being annealed) than the first hardness ([0012], i.e. Dielectric region 36 substantially fully fills trenches 32A; i.e. The filling methods may be selected from spin-on)
The prior art discloses the same materials, same flowable properties and same annealing range of the first dielectric layer as what disclosed by Applicant. The prior art discloses the same materials of the second dielectric layer as what disclosed by Applicant. See Applicant’s [0012]-[0014], [0023] and [0030]
The prior art discloses the same materials, same flowable properties and same annealing range of as Applicant.
As such, applicant’s claimed wherein the second dielectric has a third hardness higher than the first hardness is inherent in the materials and the process used as in Peng et al.
“[T]he discovery of a previously unappreciated property of a prior art composition, or of a scientific explanation for the prior art’s functioning, does not render the old composition patentably new to the discoverer.” Atlas Powder Co. v. Ireco Inc., 190 F.3d 1342, 1347, 51 USPQ2d 1943, 1947 (Fed. Cir. 1999). Thus the claiming of a new use, new function or unknown property which is inherently present in the prior art does not necessarily make the claim patentable. In re Best, 562 F.2d 1252, 1254, 195 USPQ 430, 433 (CCPA 1977). >In In re Crish, 393 F.3d 1253, 1258, 73 USPQ2d 1364, 1368 (Fed. Cir. 2004), the court held that the claimed promoter sequence obtained by sequencing a prior art plasmid that was not previously sequenced was anticipated by the prior art plasmid which necessarily possessed the same DNA sequence as the claimed oligonucleotides. The court stated that “just as the discovery of properties of a known material does not make it novel, the identification and characterization of a prior art material also does not make it novel.” MPEP 2112 section I; and
performing CMP process to both the first dielectric layer and the second dielectric layer ([0017] A planarization such as Chemical Mechanical Polish (CMP) is then performed, as shown in FIG. 7, and hence STI regions 40 are formed. STI regions 40 comprise the remaining portions of liner oxide 34, dielectric layer 36, and dielectric region 38) to completely remove the second dielectric layer and partially remove the hardened portion of the first dielectric layer (FIG. 7, item 36 in item 31B, item 38 is completely removed from item 31B),
wherein CMP process ([0017] A planarization such as Chemical Mechanical Polish (CMP) comprises a first stage ([0017] A planarization such as Chemical Mechanical Polish (CMP) is then performed, as shown in FIG. 7, and hence STI regions 40 are formed. STI regions 40 comprise the remaining portions of liner oxide 34, dielectric layer 36, and dielectric region 38), wherein the first stage ([0017]) completely removes the second dielectric layer (FIG. 7, item 38 is completely removed from item 31B) and removes a portion (FIG. 6, item 36 above item 24 is removed in FIG. 7) of the hardened portion of the first dielectric layer (FIG. 7, item 36 in item 31B)
Peng et al fails to explicitly disclose
forming a liner a top surface of the hard mask layer, over a non-hardened portion of the first dielectric,
wherein the CMP process comprises a first stage having a first down force and a second stage having a second down force, wherein the second down force is smaller than the first down force, wherein the second stage applies to a remaining portion of the hardened portion of the first dielectric layer.
However, Tong et al teaches forming a liner (FIG. 3, item 58) over a top surface ([0019] i.e. An STI liner 58 is formed overlying the fins 42 and the nitride caps 54) of the hard mask layer (FIG. 5, item 54).
Since Both Peng et al and Tong et al teach liner and a hard mask, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method of forming a semiconductor device as disclosed in Peng et al with the forming a dielectric liner a top surface of the hard mask layer as disclosed by Chen et al. The use of a liner oxide layer deposited over the substrate and the conducting structures in Chen et al provides the STI liner helps protect the upper portions of the fins and the nitride caps during subsequent processing (Tong et al, [0019]).
Peng et al and Tong et al fail to explicitly disclose over a non-hardened portion of the first dielectric, wherein the CMP process comprises a first stage having a first down force and a second stage having a second down force, wherein the second down force is smaller than the first down force, wherein the second stage applies to a remaining portion of the hardened portion of the first dielectric layer.
However, Pal et al teaches hardening (FIG. 2i, item 207b; [0051]) the first dielectric layer (FIG. 2i, item 220), resulting in a hardened portion (FIG. 2i, item 227) of the first dielectric layer over a non-hardened portion (FIG. 2i, item 222) of the first dielectric (FIG. 2i, item 220)
Since Peng et al, Tong et al and Pal et al teach dielectric layers, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the a method of forming a semiconductor device as disclosed to modify Peng et al and Tong et al with the teachings of over a non-hardened portion of the first dielectric as disclosed by Pal et al. The use of a process sequence including a planarization process and a surface modification process is repeated at least once upon performing a replacement gate approach in Pal et al provides for increasing flexibility and enhancing overall process conditions (Pal et al, [0051]).
Peng et al, Tong et al and Pal et al fail to explicitly disclose
wherein the CMP process comprises a first stage having a first down force and a second stage having a second down force, wherein the second down force is smaller than the first down force, wherein the second stage applies to a remaining portion of the hardened portion of the first dielectric layer.
However, Zhao et al teaches the CMP process with a first stage (FIG. 11, item S104) and a second stage (FIG. 11, item S105) wherein the second stage ([0055], i.e. Returning to FIG. 11, after performing the first polishing process to form the first polishing surface P1, a second polishing process may be performed (S105). FIG. 6 illustrates a corresponding semiconductor structure) applies to a remaining portion of the hardened portion of the first dielectric layer ([0056], i.e. As shown in FIG. 6, a second polishing surface is formed by performing a second polishing process P2 to planarize the first polishing surface P1 until the surface of the stop layer 203 on the top surface of the device structures 201 is exposed)
Since Peng et al, Tong et al, Pal et al and Zhao et al teach a first dielectric layer and second dielectric layer, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method of forming a semiconductor device as disclosed to modify Peng et, Tong et al, and Pal et al with the teachings of the CMP process with a first stage and a second stage wherein the second stage applies to a remaining portion of the hardened portion of the first dielectric layer as disclosed by Zhao et al. The use of after performing the first polishing process to form the first polishing surface, a second polishing process may be performed in Zhao et al provides for a CMP process using fixed abrasive and a polishing chemical to perform a more precise polishing process (Zhao et al, [0058]).
Peng et al, Tong et al, Pal et al, and Zhao et al fail to explicitly disclose wherein the CMP process comprises a first stage having a first down force and a second stage having a second down force, wherein the second down force is smaller than the first down force.
However, Wang et al teaches wherein the CMP process comprises a first stage having a first down force (FIG. 3, item 304) and a second stage having a second down force (FIG. 3, item 310),
Wherein the second down force is smaller than the first down force ([0021], i.e. a multi-step CMP process is described wherein a relatively high force, low topology selectivity CMP process is performed first to remove protrusions, and then a relatively low force, high topology selectivity CMP process is performed)
Since Peng et al, Tong et al, Pal et al, Zhao et al and Wang et al teach a CMP process, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method of forming a semiconductor device as disclosed in Peng et al with the wherein the CMP process comprises a first stage having a first down force and a second stage having a second down force, wherein the second down force is smaller than the first down force as disclosed by Wang et al. The use of a multi-step CMP process is described wherein a relatively high force, low topology selectivity CMP process is performed first to remove protrusions, and then a relatively low force, high topology selectivity CMP process is performed in Wang et al provides for the low topology selectivity CMP primarily removes protrusions, while the high topology selectivity CMP is used to achieve a high degree of WIW (With In Wafer) uniformity (Wang et al, [0021]).
Regarding claim 5. Peng et al, Tong et al, Pal et al, Zhao et al, and Wang et al disclose all the limitations of the method of claim 1 above.
Wang et al further discloses wherein the CMP process uses cerium oxide (CeO2) based slurry ([0028], i.e. Both the undiluted and diluted slurry can include a ceria-based abrasive, such as a CeO2 based abrasive.)
Regarding claim 9. Peng et al, Tong et al, Pal et al, Zhao et al, and Wang et al and discloses all the limitations of the method of claim 1 above.
Peng et al further discloses further comprising tuning parameters of the hardening of the portion ([0014], i.e. dielectric material 36 is solidified by a curing process separate from the anneal) of the first dielectric layer (FIG. 4, item 36) to increase the first hardness (FIG. 4, item 36) to the second hardness (FIG. 6, item 36).
Zhao et al discloses wherein the second hardness is a given hardness that reduces scratch defects during the CMP process ([0018], i.e. . Because the second dielectric layer much harder than the first dielectric layer, the second polishing process may not scratch the surface of the first dielectric layer in the peripheral region)
Regarding claim 21. Peng et al, Tong et al, Pal et al, Zhao et al, and Wang et al discloses all the limitations of the method of claim 1 above.
Tong et al further discloses wherein after the CMP process ([0020], i.e.the eHARP oxide fill 64 is planarized with portions of the STI liner 58 overlying the nitride caps 54 by removing any excess eHARP oxide material using a CMP process), portion of the oxide liner (FIG. 4, item 58) over the top surface ([0019]) of the hard mask layer (FIG. 4, item 54) is exposed ([0019]-[0020]).
Peng et al discloses where the oxide liner comprises silicon oxide ([0011], i.e. liner oxide 34 may be a thermal oxide (such as silicon dioxide)).
Claims 2 – 4, 6, and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Peng et al (U.S. 2014/0231919), Tong et al (U.S. 2014/0353795), Pal et al (U.S. 2013/0115773), Zhao et al (U.S. 2015/0287611), and Wang et al (U.S. 2006/0252267) as applied to claim 1 above, and further in view of Tong et al (“Low-temperature bonding of silicon-oxide-covered wafers using diluted HF etching”, 2004) referred to as Tong et al ‘2004.
Regarding claim 2. Peng et al, Tong et al ‘795, Pal et al, Zhao et al, and Wang et al discloses all the limitations of the method of claim 1 above.
Peng et al discloses hardening of the first dielectric layer ([0014], i.e. Referring to FIG. 5, an anneal step (represented by arrows 37) is performed on wafer 100. Dielectric material 36 is solidified as a result of the anneal)
Peng et al fails to explicitly disclose comprises treating the first dielectric layer with a fluorine-containing oxidizer.
However, Tong et al ‘2004 teaches wherein the hardening of the first dielectric layer (Tong et al, Page 2764, Second Column, last paragraph, i.e. The number of Si–O–Si covalent bonds at the bonding interface appears to be significantly increased by the formation of fluorinated silicon oxide (SiOF) that absorbs water effectively which is the by-product of the polymerization reaction at the bonding interface) comprises treating the first dielectric layer with an fluorine containing oxidizer (Tong, Page 2762, Second Column, second paragraph, i.e. All wafers were cleaned in standard RCA1 solution for 15 min at 70–80°C. After rinsing in de-ionized (DI) water, they were dipped in a diluted (0.02%–0.5%) HF aqueous solution (DHF) for 1–2 min. Without DI water rinsing after DHF dip, the wafers were spin dried and bonded spontaneously in air at room temperature).
Since Peng et al and Tong et al teach silicon oxide covered wafers, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method of forming a semiconductor device as disclosed in Peng et al with the wherein the hardening of the first dielectric layer comprises treating the first dielectric layer with an oxidizer as disclosed by Tong et al. The use of the after rinsing in de-ionized (DI) water, they were dipped in a diluted (0.02%–0.5%) HF aqueous solution in Tong et al provides for Achieving a strong bond at low temperatures is critical for bonding of thermally mismatched or thermally sensitive wafers including processed device wafers (Tong et al, Page 2762, first column, second paragraph).
Regarding claim 3. Peng et al, Tong et al ‘795, Pal et al, Zhao et al, and Wang et al, and Tong et al ‘2004 discloses all the limitations of the method of claim 2 above.
Tong et al ‘2004 further discloses wherein the treating of the first dielectric layer is performed at a temperature ranging from 15 0C to 90 0C the fluorine-containing oxidizer is dilute hydrofluoric acid (DHF) and a concentration of hydrofluoric acid in the fluorine-containing oxidizer ranges from 0.005% to 0.1%. (Tong, Page 2762, Second Column, second paragraph, i.e. All wafers were cleaned in standard RCA1 solution for 15 min at 70–80°C. After rinsing in de-ionized (DI) water, they were dipped in a diluted (0.02%–0.5%) HF aqueous solution (DHF) for 1–2 min. Without DI water rinsing after DHF dip, the wafers were spin dried and bonded spontaneously in air at room temperature.).
“[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See MPEP 2144.05 II. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); Smith v. Nichols, 88 U.S. 112, 118-19 (1874); In re Williams, 36 F.2d 436, 438 (CCPA 1929). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
Regarding claim 4. Peng et al, Tong et al ‘795, Pal et al, Zhao et al, and Wang et al, and Tong et al ‘2004 discloses all the limitations of the method of claim 2 above.
Tong et al ‘2004 further discloses, wherein the treating of the first dielectric layer is performed at room temperature (Tong, Page 2762, Second Column, second paragraph, i.e. without DI water rinsing after DHF dip, the wafers were spin dried and bonded spontaneously in air at room temperature).
Regarding claim 5. Peng et al, Tong et al ‘795, Pal et al, Zhao et al, and Wang et al, and Tong et al ‘2004 discloses all the limitations of the method of claim 2 above.
Tong et al ‘2004 further discloses wherein the oxidizer is aqueous (Tong, Page 2762, Second Column, second paragraph, i.e. All wafers were cleaned in standard RCA1 solution for 15 min at 70–80°C. After rinsing in de-ionized (DI) water, they were dipped in a diluted (0.02%–0.5%) HF aqueous solution (DHF) for 1–2 min. Without DI water rinsing after DHF dip, the wafers were spin dried and bonded spontaneously in air at room temperature).
Regarding claim 6. Peng et al, Tong et al ‘795, Pal et al, Zhao et al, and Wang et al, and Tong et al ‘2004 discloses all the limitations of the method of claim 2 above.
Tong et al ‘2004 further discloses wherein the hardening of the first dielectric layer further comprises, after the treating of the first dielectric layer, treating the first dielectric layer with deionized water (DIW) (Tong, Page 2762, Second Column, second paragraph, i.e. All wafers were cleaned in standard RCA1 solution for 15 min at 70–80°C. After rinsing in de-ionized (DI) water, they were dipped in a diluted (0.02%–0.5%) HF aqueous solution (DHF) for 1–2 min. Without DI water rinsing after DHF dip, the wafers were spin dried and bonded spontaneously in air at room temperature).
Regarding claim 8. Peng et al, Tong et al ‘795, Pal et al, Zhao et al, and Wang et al disclose all the limitations of the method of claim 1 above.
Peng et al discloses wherein the annealing step is performed at a first temperature and the hardening of the portion of the first dielectric layer
Peng et al fails to explicitly disclose is performed at a second temperature less than the first temperature, wherein the second temperature is less than 100°C.
However, Tong et al (‘2004) teaches hardening of the portion of the first dielectric layer (Tong et al, Page 2764, Second Column, last paragraph, i.e. The number of Si–O–Si covalent bonds at the bonding interface appears to be significantly increased by the formation of fluorinated silicon oxide (SiOF) that absorbs water effectively which is the by-product of the polymerization reaction at the bonding interface) is performed at a second temperature less than the first temperature, wherein the second temperature is less than 100°C (Tong, Page 2762, Second Column, second paragraph, i.e. All wafers were cleaned in standard RCA1 solution for 15 min at 70–80°C. After rinsing in de-ionized (DI) water, they were dipped in a diluted (0.02%–0.5%) HF aqueous solution (DHF) for 1–2 min. Without DI water rinsing after DHF dip, the wafers were spin dried and bonded spontaneously in air at room temperature).
Peng et al in combination with Tong et al (‘2004) discloses a second temperature (Peng et al )less than the first temperature (Tong et al, Page 2764, Second Column, last paragraph)
Since Peng et al and Tong et al (‘2004) teach silicon oxide covered wafers, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method of forming a semiconductor device as disclosed to modify Peng et al with the teachings of the hardening of the portion of the first dielectric layer is performed at a second temperature less than the first temperature, wherein the second temperature is less than 100°C as disclosed by Tong et al. The use of the number of Si–O–Si covalent bonds at the bonding interface appears to be significantly increased by the formation of fluorinated silicon oxide (SiOF) that absorbs water effectively which is the by-product of the polymerization reaction at the bonding interface and all wafers were cleaned in standard RCA1 solution for 15 min at 70–80°C, after rinsing in de-ionized (DI) water, they were dipped in a diluted (0.02%–0.5%) HF aqueous solution (DHF) for 1–2 min. Without DI water rinsing after DHF dip, the wafers were spin dried and bonded spontaneously in air at room temperature in Tong et al provides for Achieving a strong bond at low temperatures is critical for bonding of thermally mismatched or thermally sensitive wafers including processed device wafers (Tong et al, Page 2762, first column, second paragraph).
"Products of identical chemical composition cannot have mutually exclusive properties." See MPEP 2112.01 II
Claims 10-13 are rejected under 35 U.S.C. 103 as being unpatentable over Peng et al (U.S. 2014/0231919), Lou (U.S. 6,020,265), Pal et al (U.S. 2013/0115773), Wang et al (U.S. 2006/0252267) and Tong et al (“Low-temperature bonding of silicon-oxide-covered wafers using diluted HF etching”, 2004).
Regarding claim 10. Peng et al discloses a method of forming a semiconductor device, the method comprising:
providing a substrate (FIG. 2, item 20) and semiconductor fins (FIG. 2, item 30B; [0010], i.e. semiconductor strips 30B) over the substrate (FIG. 2, item 20), the semiconductor fins (FIG. 2, item 30B) being interposed by trenches (FIG. 2, item 32A) and each of the semiconductor fins (FIG. 2, item 30B) being capped by a hard mask layer (FIG.2, item 24); and
forming isolation structures (FIG. 4, item 36) in the trenches (FIG. 3/4, item 32A) interposing the semiconductor fins (FIG. 3, item 30B), wherein the forming of the isolation structures (FIG. 4, item 36) includes:
conformally depositing ([0011]) a oxide liner (FIG. 2, item 34) of the isolation structures (FIG. 4, item 36) to partially fill the trenches (FIG. 3/4, item 32A), wherein the oxide liner (FIG. 2, item 34) is over sidewalls of the fins (FIG. 2, item 30B)
performing a flowable chemical vapor deposition (FCVD) process ([0012], i.e. Flowable Chemical Vapor Deposition (FCVD)) to form ([0012]) a first dielectric layer (FIG. 4, item 36) of the isolation structure (FIG. 4, item 36) over ([0011]) the oxide liner (FIG. 2, item 34) that fills remainders ([0012]) of the trenches (FIG. 4, item 32A), wherein the first dielectric layer (FIG. 4, item 36) containing silicon and oxygen ([0016]) and the first dielectric layer (FIG. 4, item 36) has a first content of silicon-oxygen bonds ([0016], i.e. Dielectric region 38 may include silicon dioxide; Dielectric regions 36 and 38, after being annealed, may be formed of a same material);
after (FIG. 5 is after FIG. 4) performing the FCVD process (FIG. 4, item 36) and before (FIG. 5 is before FIG. 7) performing a chemical mechanical planarization (CMP) process (FIG. 7; [0017]) on the first dielectric layer (FIG. 4, item 36) of the isolation structures (FIG. 4, item 36)
treating the first dielectric layer ([0014], i.e. Referring to FIG. 5, an anneal step (represented by arrows 37) is performed on wafer 100. Dielectric material 36 is solidified as a result of the anneal.) of the isolation structures (FIG. 5, item 36)
the treated portion of the first dielectric layer having a second content of silicon-oxygen bonds ([0014], i.e. Referring to FIG. 5, an anneal step (represented by arrows 37) is performed on wafer 100. Dielectric material 36 is solidified as a result of the anneal.) the first content of silicon-oxygen bonds (FIG. 4, item 36);
depositing a second dielectric layer (FIG. 6, item 38) over the treated portion of the first dielectric layer (FIG. 6, item 36); and
performing the CMP process ([0017] A planarization such as Chemical Mechanical Polish (CMP) is then performed, as shown in FIG. 7, and hence STI regions 40 are formed. STI regions 40 comprise the remaining portions of liner oxide 34, dielectric layer 36, and dielectric region 38) to the second dielectric layer (FIG. 7, item 38 is completely removed from item 31B) and the treated portion of the first dielectric layer (FIG. 7, item 36 in item 31B, item 38 is completely removed from item 31B).
wherein the first stage ([0017]) completely removes the second dielectric layer (FIG. 7, item 38 is completely removed from item 31B) and removes a portion (FIG. 6, item 36 above item 24 is removed in FIG. 7) of the treated portion of the first dielectric layer (FIG. 7, item 36 in item 31B)
Peng et al fails to explicitly disclose
forming the oxide liner over a top surface of the hard mask layer, treating the first dielectric layer with an aqueous oxidizer, resulting in a treated portion of the first dielectric layer above an untreated portion of the first dielectric layer, wherein, after the performing of the CMP process, a top surface of the hard mask layer remains covered by the oxide liner, wherein the CMP process comprises a first stage having a first down force and a second stage having a second down force, wherein the second down force is smaller than the first down force, wherein the second stage applies to a remaining portion of the treated portion of the first dielectric layer such that a portion of the oxide liner over the top surface of the hard mask layer is exposed.
However, Lou teaches forming a oxide liner (FIG. 1, item 106) over a top surface (FIG. 1, item 106 is over item 104; Col 2, lines 28-30, i.e. a liner oxide layer 106 is deposited over the substrate 100 and the conducting structures 102. The liner oxide layer 106 is preferably silicon dioxide) of the hard mask layer (FIG. 1, item 106), wherein, after the CMP process (Col 2, lines 63-65; i.e. Turning to FIG. 2, an oxide CMP is performed and controlled to stop at the surface of the first low dielectric material layer 108), a top surface of the hard mask layer (FIG. 2, item 104) remains covered by the oxide liner (FIG. 2, item 106).
Since Both Peng et al and Lou et al teach a oxide liner and a hard mask, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method of forming a semiconductor device as disclosed to modify Peng et al with teachings of the forming a dielectric liner a top surface of the hard mask layer, wherein, after the performing of the CMP process, a top surface of the hard mask layer remains covered by the oxide liner as disclosed by Lou. The use of a liner oxide layer deposited over the substrate and the conducting structures and an oxide CMP is performed and controlled to stop at the surface of the first low dielectric material layer in Lou provides for a high quality insulator directly over and in immediate contact with conducting structures (Lou, Col 2, lines 35-37).
Peng et al and Lou fail to explicitly disclose
treating the first dielectric layer with an aqueous oxidizer, resulting in a treated portion of the first dielectric layer above an untreated portion of the first dielectric layer, wherein the CMP process comprises a first stage having a first down force and a second stage having a second down force, wherein the second down force is smaller than the first down force, wherein the second stage applies to a remaining portion of the treated portion of the first dielectric layer such that a portion of the oxide liner over the top surface of the hard mask layer is exposed.
However, Pal et al teaches
Treating (FIG. 2i, item 207b; [0051]) the first dielectric layer (FIG. 2i, item 220), resulting in a treated portion (FIG. 2i, item 227) of the first dielectric layer (FIG. 2i, item 220) above an untreated portion (FIG. 2i, item 222) of the first dielectric layer (FIG. 2i, item 220), wherein the CMP process ([0052])] comprises a second stage (FIG. 2j, item 208a), wherein the second stage applies (FIG. 2j, item 208a) to a remaining portion (FIG. 2j, item 228) of the treated portion (FIG. 2j, item 228) of the first dielectric layer (FIG. 2j, item 220) such that a portion (FIG. 2j, item 266t) of the oxide liner (FIG. 2j, item 221; [0039]) over the top surface of the hard mask layer (FIG. 2j, item 264) is exposed ([0052]).
Since Peng et al, Lou and Pal et al teach dielectric layers, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the a method of forming a semiconductor device as disclosed to modify Peng et al and Lou with the teachings of treating the first dielectric layer, resulting in a treated portion of the first dielectric layer above an untreated portion of the first dielectric layer, wherein the CMP process comprises a second stage, wherein the second stage applies to a remaining portion of the treated portion of the first dielectric layer such that a portion of the oxide liner over the top surface of the hard mask layer is exposed as disclosed by Pal et al. The use of a process sequence including a planarization process and a surface modification process is repeated at least once upon performing a replacement gate approach in Pal et al provides for increasing flexibility and enhancing overall process conditions (Pal et al, [0051]).
Peng et al, Lou and Pal et al fail to explicitly disclose
treating the first dielectric layer with an aqueous oxidizer, wherein the CMP process comprises a first stage having a first down force and a second stage having a second down force, wherein the second down force is smaller than the first down force.
However, Wang et al teaches wherein the CMP process comprises a first stage having a first down force (FIG. 3, item 304) and a second stage having a second down force (FIG. 3, item 310),
Wherein the second down force is smaller than the first down force ([0021], i.e. a multi-step CMP process is described wherein a relatively high force, low topology selectivity CMP process is performed first to remove protrusions, and then a relatively low force, high topology selectivity CMP process is performed)
Since Peng et al, Lou, Pal et al and Wang et al teach a CMP process, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method of forming a semiconductor device as disclosed to modify Peng et al, Lou, Pal et al with teachings of the wherein the CMP process comprises a first stage having a first down force and a second stage having a second down force, wherein the second down force is smaller than the first down force as disclosed by Wang et al. The use of a multi-step CMP process is described wherein a relatively high force, low topology selectivity CMP process is performed first to remove protrusions, and then a relatively low force, high topology selectivity CMP process is performed in Wang et al provides for the low topology selectivity CMP primarily removes protrusions, while the high topology selectivity CMP is used to achieve a high degree of WIW (With In Wafer) uniformity (Wang et al, [0021]).
Peng et al, Lou, Pal et al and Wang et al fail to explicitly disclose treating the first dielectric layer with an aqueous oxidizer.
However, Tong et al teaches treating the first dielectric layer with an aqueous oxidizer (Tong, Page 2762, Second Column, second paragraph, i.e. All wafers were cleaned in standard RCA1 solution for 15 min at 70–80°C. After rinsing in de-ionized (DI) water, they were dipped in a diluted (0.02%–0.5%) HF aqueous solution (DHF) for 1–2 min. Without DI water rinsing after DHF dip, the wafers were spin dried and bonded spontaneously in air at room temperature), resulting in a treated portion of the first dielectric layer above an untreated portion of the first dielectric layer (Tong et al, Page 2764, Second Column, last paragraph, i.e. The number of Si–O–Si covalent bonds at the bonding interface appears to be significantly increased by the formation of fluorinated silicon oxide (SiOF) that absorbs water effectively which is the by-product of the polymerization reaction at the bonding interface).
Since Peng et al, Lou, Pal et al, Wang et al and Tong et al disclose silicon oxide covered wafers, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method of forming a semiconductor device as disclosed to modify Peng et al, Lou, Pal et al and Wang et al with the teachings of treating the first dielectric layer with an aqueous oxidizer, resulting in a treated portion of the first dielectric layer above an untreated portion of the first dielectric layer as disclosed by Tong et al. The use of the after rinsing in de-ionized (DI) water, they were dipped in a diluted (0.02%–0.5%) HF aqueous solution and the number of Si–O–Si covalent bonds at the bonding interface appears to be significantly increased by the formation of fluorinated silicon oxide (SiOF) that absorbs water effectively in Tong et al provides for Achieving a strong bond at low temperatures is critical for bonding of thermally mismatched or thermally sensitive wafers including processed device wafers (Tong et al, Page 2762, first column, second paragraph).
Regarding claim 11. Peng et al, Lou, Pal et al, Wang et al and Tong et al discloses all the limitations of the method of claim 10 above.
Peng et al discloses the first dielectric layer (FIG. 4, item 36) has a first hardness after (FIG. 5 is after FIG. 4) the FCVD process (FIG. 4, item 36; [0012], i.e. Flowable Chemical Vapor Deposition (FCVD)) that corresponds with a first amount of scratch defects during the CMP process(FIG. 7; [0017]) (as best understood by the 112(b) above. [0012], i.e. Flowable Chemical Vapor Deposition (FCVD), examiner makes notes that a first amount of scratch defect during the CMP process since applicant has only claimed a FCVD process without claiming any actual process steps in the FCVD process);
Tong et al discloses the treating the first dielectric layer with the aqueous oxidizer provides the treated portion of the first dielectric layer (Tong, Page 2762, Second Column, second paragraph) with a second hardness wherein the second hardness corresponds with a second amount of scratch defects during the CMP process (Examiner makes note that since applicant states the aqueous oxidizer provides the second hardness, Tong treated first dielectric by the aqueous oxidizer inherently provides the
Since Peng Discloses the FCVD process (FIG. 4, item 36; [0012], i.e. Flowable Chemical Vapor Deposition (FCVD)) that corresponds with a first amount of scratch defects during the CMP process(FIG. 7; [0017]),
And Tong et al discloses the treating the first dielectric layer with the aqueous oxidizer provides the treated portion of the first dielectric layer (Tong, Page 2762, Second Column, second paragraph) that is higher than the first hardness (FIG. 4, item 36),
Peng et al in combination with Tong et al inherently discloses wherein the second hardness corresponds with