Prosecution Insights
Last updated: April 19, 2026
Application No. 16/877,197

SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

Final Rejection §102§103
Filed
May 18, 2020
Examiner
BOYLE, ABBIGALE A
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Advanced Semiconductor Engineering Inc.
OA Round
4 (Final)
61%
Grant Probability
Moderate
5-6
OA Rounds
3y 4m
To Grant
74%
With Interview

Examiner Intelligence

Grants 61% of resolved cases
61%
Career Allow Rate
213 granted / 350 resolved
-7.1% vs TC avg
Moderate +13% lift
Without
With
+13.2%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
39 currently pending
Career history
389
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
49.8%
+9.8% vs TC avg
§102
29.1%
-10.9% vs TC avg
§112
20.1%
-19.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 350 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1, 43-44, and 47-50 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kwon et al. (U.S. 2019/0295944). Regarding Claim 1, Kwon et al. (Figures 3, 6, and 13) discloses a semiconductor package structure, comprising: a semiconductor die having an active surface, a backside surface and a lateral surface, wherein an active layer of the semiconductor die is adjacent to the active surface, the backside surface is opposite to the active surface, and the lateral surface is connected to the active surface and the backside surface (die 200); a light absorbing layer covering the backside surface and the lateral surface of the semiconductor die, wherein the light absorbing layer has an outer lateral surface covering and spaced apart from the lateral surface of the semiconductor die, and wherein the outer lateral surface has a first edge nonparallel to the lateral surface of the semiconductor die, a second edge nonparallel to the lateral surface of the semiconductor die, and a third edge extending between the first edge and the second edge (light absorbing layer 300, first edge 104/320, second edge 103, third edge 105 or 105/310/104 or 105/310/104/103, [0126]). Regarding Claim 43, Kwon et al. (Figures 3, 6, and 13) further discloses the semiconductor package structure of claim 1, wherein the light absorbing layer is configured to absorb a light incident to the semiconductor die ([0126]-[0128]). Regarding Claim 44, Kwon et al. (Figures 3, 6, and 13) further discloses the semiconductor package structure of claim 43, wherein the light absorbing layer is configured to absorb a light with a wavelength of 390nm to 1000nm ([0126]-[0128]). Regarding Claim 47, Kwon et al. (Figures 3, 6, and 13) further discloses the semiconductor package structure of claim 1, wherein the third edge is parallel to the lateral surface of the semiconductor die (light absorbing layer 300, third edge 105 in between end portions of 103 and 104 runs parallel to the lateral surface of die 200, [0092] and [100]). Regarding Claim 48, Kwon et al. (Figures 3, 6, and 13) further discloses the semiconductor package structure of claim 1, wherein the first edge defines a first protruded portion, the second edge defines a second protruded portion, and the third edge defines an indented portion of the light absorbing layer (light absorbing layer 300, first protruded portion 104/320, second protruded portion 103, indented portion 105 or 105/310/104 or 105/310/104/103). Regarding Claim 49, Kwon et al. (Figures 3, 6, and 13) further discloses the semiconductor package structure of claim 48, further comprising a passivation layer below the active surface of the semiconductor die, wherein a bottom surface of the light absorbing layer is aligned with a bottom surface of the passivation layer (light absorbing layer 300, passivation layer 410). Regarding Claim 50, Kwon et al. (Figures 3, 6, and 13) further discloses the semiconductor package structure of claim 48, wherein the first protruded portion and the second protruded portion are tapered toward each other (first protruded portion 104/320, second protruded portion 103/310, and the indented portion of the light absorbing layer has a uniform thickness (indented portion 105, [0092] and [0100]). Regarding Claim 51, Kwon et al. (Figures 3, 6, and 13) further discloses the semiconductor package structure of claim 48, wherein the light absorbing layer has a first thickness over the backside surface (light absorbing layer 300), and a second thickness of the indented portion of the light absorbing layer is less than the first thickness (indented portion 105). Claim(s) 21, 55, and 56 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Strothmann et al. (U.S. 2015/0243575). Regarding Claim 21, Strothmann et al. (Figures 3h and 3i) discloses a semiconductor package structure, comprising: a semiconductor die having an active surface, a backside surface and a lateral surface, wherein an active layer of the semiconductor die is adjacent to the active surface, the backside surface is opposite to the active surface, and the lateral surface is connected to the active surface and the backside surface (die 124); and a light absorbing layer covering the backside surface and the lateral surface of the semiconductor die, wherein the light absorbing layer has an outer lateral surface facing away and laterally overlapping the lateral surface of the semiconductor die and a bottom surface covering a portion of the active surface of the semiconductor die, and the bottom surface is slanted with respect to the outer lateral surface of the light absorbing layer and to the active surface of the semiconductor die (light absorbing layer 158/170, slanted portions by vias 172, [0055] and [0058]). Regarding Claim 55, Strothmann et al. (Figures 3h and 3i) further discloses the semiconductor package structure of claim 21, further comprising a passivation layer covering the active surface of the semiconductor die, wherein the bottom surface of the light absorbing layer is slanted with respect to a bottom surface, spaced apart from the active surface, of the passivation layer (passivation layer 134) Regarding Claim 56, Strothmann et al. (Figures 3h and 3i) further discloses the semiconductor package structure of claim 55, further comprising a solder ball below the passivation layer, wherein the light absorbing layer contacts the bottom surface of the passivation layer and is spaced apart from the solder ball (solder ball 175). Claim(s) 38 and 59 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Matsuura et al. (U.S. 2021/0125959). Regarding Claim 38, Matsuura et al. (Figure 2a) discloses a semiconductor package structure, comprising: a semiconductor die having an active surface, a backside surface opposite to the active surface, and a lateral surface extending between the active surface and the backside surface (die 202); and a polymer layer covering the backside surface and the lateral surface, wherein the polymer layer has an outer lateral surface laterally overlapping the lateral surface of the semiconductor die, the outer lateral surface has a first edge and a second edge defining a step structure, and the first edge is orthogonal to the second edge (polymer layer 210, [0029]). Regarding Claim 59, Matsuura et al. (Figure 2a) further discloses the semiconductor package structure of claim 38, wherein the polymer layer has an indented portion and a protruded portion connected to the indented portion, and each of a thickness of the indented portion and a thickness of the protruded portion is uniform (polymer layer 210). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 45 and 46 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al. (U.S. 2019/0295944) as applied to claim 44 above, and further in view of Koduri et al. (U.S. 6,734,532). Regarding Claim 45, Kwon et al. discloses that the semiconductor package structure of claim 44, but does not explicitly disclose wherein an incident light, incident to the semiconductor die, is absorbed by the light absorbing layer, and a remained light to the active layer is decreased to 0.01%. In the same field of endeavor, Koduri et al. discloses a device wherein a light absorbing layer comprising black carbon absorbs an incident light, incident to the semiconductor die, and a remained light to the active layer is decreased to about 0.01% (Koduri et al., light absorbing layer 106, Figures 1 and 3, Column 4, Lines 47-67) and disclose that this material is suitable for use as a light absorbing protective film (Koduri et al., Column 4, lines 28-38). Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to form the light absorbing layer to absorb an incident light, incident to the semiconductor die, and a remained light to the active layer is decreased to about 0.01% in Kwon et al. in view of Koduri et al. in order to prevent electrical noise from incident light (Koduri et al., Column 1, Lines 58-65) and to choose a suitable material for light absorption, stress neutralization, and moisture protection (Koduri et al., Column 2, Lines 15-25 and Column 4, Lines 28-38). Regarding Claim 46, Kwon et al. discloses that the semiconductor package structure of claim 44, but does not explicitly disclose wherein an incident light, incident to the semiconductor die, is absorbed by the light absorbing layer, and a remained light to the active layer is less than 0.01% with respect to the incident light. In the same field of endeavor, Koduri et al. discloses a device wherein a light absorbing layer comprising black carbon absorbs an incident light, incident to the semiconductor die, and a remained light to the active layer is less than 0.01% with respect to the incident light (Koduri et al., light absorbing layer 106, Figures 1 and 3, Column 4, Lines 47-67) and disclose that this material is suitable for use as a light absorbing protective film (Koduri et al., Column 4, lines 28-38). Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to form the light absorbing layer to absorb an incident light, incident to the semiconductor die, and a remained light to the active layer is less than 0.01% with respect to the incident light in Kwon et al. in view of Koduri et al. in order to prevent electrical noise from incident light (Koduri et al., Column 1, Lines 58-65) and to choose a suitable material for light absorption, stress neutralization, and moisture protection (Koduri et al., Column 2, Lines 15-25 and Column 4, Lines 28-38). Response to Arguments Applicant's arguments filed 13 June 2025 have been fully considered but they are not persuasive. Regarding Claim 1, Applicant's arguments fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references. Therefore the arguments are not persuasive. Applicant’s arguments with respect to claim(s) 21 and 38 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action. Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Abbigale Boyle whose telephone number is 571-270-7919. The Examiner can normally be reached from 11 A.M to 7 P.M., Monday through Friday. If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, Zandra Smith, can be reached at 571-272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance form a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. Abbigale Boyle Examiner, Art Unit 2899 /ABBIGALE A BOYLE/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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Prosecution Timeline

May 18, 2020
Application Filed
Oct 07, 2023
Non-Final Rejection — §102, §103
Jan 12, 2024
Response Filed
Jun 15, 2024
Final Rejection — §102, §103
Oct 22, 2024
Request for Continued Examination
Oct 26, 2024
Response after Non-Final Action
Mar 08, 2025
Non-Final Rejection — §102, §103
Jun 13, 2025
Response Filed
Oct 30, 2025
Final Rejection — §102, §103
Jan 09, 2026
Interview Requested

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

5-6
Expected OA Rounds
61%
Grant Probability
74%
With Interview (+13.2%)
3y 4m
Median Time to Grant
High
PTA Risk
Based on 350 resolved cases by this examiner. Grant probability derived from career allow rate.

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