DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after 16 March 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant’s reply filed on 28 January 2026.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 7, 8 and 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (U.S. Pub. 2019/0148427) in view of Huang et al. (U.S. Pub. 2018/0151759) in view of U.S. Pub. 2019/0096947, hereinafter referred to as Lee ‘947, Endo et al. (U.S. Pub. 2018/0114808).
Claim 1: Lee discloses a semiconductor arrangement, in annotated Fig. 2 below and in paragraphs 17-21, comprising:
a first component (PD2 on the left) in a substrate (1), wherein the substrate (1) overlies the first component (PD2 on the left) and underlies the first component (PD2 on the left);
a second component (PD1) in the substrate (1); and
a gap fill layer (25), wherein:
a first portion of the gap fill layer overlies the first component (PD2 on the left);
the first portion of the gap fill layer has a tapered sidewall; and
a first portion (portion of 1 that surrounds PD2 on the left) of the substrate (1) separates the first portion of the gap fill layer from the first component (PD2 on the left);
the substrate (1) has a first sidewall and a second sidewall that define a trench (second from left trench) between the first component (PD2 on the left) and the second component (PD1); and
a second portion of the gap fill layer is disposed in the trench (second from left trench) and fills the trench (second from left trench) such that there is no material that is in the trench (second from left trench) and overlies the second portion of the gap fill layer.
the gap fill layer overlying the first component (PD2 on the left).
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Lee appears not to explicitly disclose a distance from a top of the substrate to a bottom of the first portion of the gap fill layer overlying the first component is 5001 to 10,000 angstroms.
Huang et al., however, in Figs. 8 and 10 and in paragraphs 20, 29, 35 and 42, a distance from a top (top of 902) of the substrate (902) to a bottom (bottom of 117 and/or 817) of the first portion (117 and/or 817) of the gap fill layer (264) overlying the first component (104a) is 5001 to 10000 angstrom (from 200 nm to 1000 nm, that is 2000 to 10000 angstroms) in order to increase absorption by the light sensing elements.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify Lee with the disclosure of Huang et al. to have made a distance between a top of the substrate to a bottom of the first portion of the gap fill layer overlying the first component is 5001 to 10,000 angstroms in order to increase the probability of the incident light being absorbed (paragraph 35 of Huang et al.). Also, in the case where the claimed ranges overlap or lie inside ranges disclosed by the prior art a prima facie case of obviousness exists (M.P.E.P. § 2144.05).
Lee also appears not to explicitly disclose the gap fill layer comprises a metal overlying the first component.
Lee ‘947, however, in Fig. 9 and in paragraphs 34 and 41, the dielectric material (104a and 302) comprising a metal is a suitable material for the gap fill layer (104a and 302) over lying the first component (PD1).
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Lee with the disclosure of Lee ‘947 to have made the gap fill layer comprises a metal overlying the first component because the selection of a known material based on its suitability for its intended purpose is obvious (see, for example, M.P.E.P. § 2144.07, and precedents cited therein).
Lee also appears not to explicitly disclose a gate structure under the substrate, wherein the gate structure underlies the first component;
a first source/drain region underlying the first component and under the gate structure;
a shallow trench isolation region underlying the first component; and
a second source/drain region underlying the first component, wherein the shallow trench isolation region is between the first source/drain region and the second source/drain region.
Endo et al., however, in Fig. 1 and in paragraphs 29 and 34-36, discloses a gate structure (126 on the left) under the substrate (104), wherein the gate structure (126 on the left) underlies the first component (112 on the left);
a first source/drain region (second from left 125) underlying the first component (126 on the left) and under the gate structure (126 on the left);
a shallow trench isolation region (middle 127) underlying the first component (112 on the left); and
a second source/drain region (second from the right 125) underlying the first component (112 on the left), wherein the shallow trench isolation region (middle 127) is between the first source/drain region (second from the left 125) and the second source/drain region (second from the right 125) in order to increase the area of the first component and to increase sensitivity.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify Lee with the disclosure of Endo et al. to have made a gate structure under the substrate, wherein the gate structure underlies the first component; a first source/drain region underlying the first component and under the gate structure; a shallow trench isolation region underlying the first component; and a second source/drain region underlying the first component, wherein the shallow trench isolation region is between the first source/drain region and the second source/drain region in order to increase the area of the first component and to increase sensitivity (paragraph 29 of Endo et al.).
Claim 2: Lee in view of Huang et al. in view of Lee ‘947 in view of Endo et al. discloses the semiconductor arrangement of claim 1, and Lee, in Fig. 2, further discloses wherein the first portion (portion of 1 that surrounds PD2 on the left) of the substrate (1) has a first tapered sidewall with which the tapered sidewall of the first portion of the gap fill layer aligns.
Claim 3: Lee in view of Huang et al. in view of Lee ‘947 in view of Endo et al. discloses the semiconductor arrangement of claim 2, and Lee, in Fig. 2, further discloses wherein:
a third portion of the gap fill layer overlies the first component (PD2 on the left);
the third portion of the gap fill layer has a tapered sidewall; and
the first portion (portion of 1 that surrounds PD2 on the left) of the substrate (1) has a second tapered sidewall with which the tapered sidewall of the third portion of the gap fill layer aligns.
Claim 4: Lee in view of Huang et al. in view of Lee ‘947 in view of Endo et al. discloses the semiconductor arrangement of claim 3, and Lee, in Fig. 2, further discloses wherein:
the first tapered sidewall of the first portion of the substrate has a first slope (slope of the first tapered sidewall of the first portion of the substrate);
the second tapered sidewall of the first portion of the substrate has a second slope (slope of the second tapered sidewall of the first portion of the substrate); and
the second slope is opposite in polarity relative to the first slope.
Claim 5: Lee in view of Huang et al. in view of Lee ‘947 in view of Endo et al. discloses the semiconductor arrangement of claim 1.
Further, Endo et al. teaches in Fig. 1 and in paragraphs 29 and 36, further discloses
a first doped well region (left 124) underlying the first component (112 on the left); and
a second doped well region (right 124) underlying the first component (112 on the left) and underlying the second component (112 on the right), wherein:
the first source/drain region (second from left 125) is disposed in the first doped well region (left 124);
the second source/drain region (second from right 125) is disposed in the second doped well region (right 124); and
the shallow trench isolation region (middle 127) is between the first doped well region (left 124) and the second doped well region (right 124) in order to be able to form the transistors of the first and second components and to increase the area of the first and second components to increase sensitivity.
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It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify Lee in view of Huang et al. in view of Lee ‘947 in view of Endo et al., as applied to claim 1, with the further disclosure of Endo et al. to have made a first doped well region underlying the first component; and a second doped well region underlying the first component and underlying the second component, wherein: the first source/drain region is disposed in the first doped well region; the second source/drain region is disposed in the second doped well region; and the shallow trench isolation region is between the first doped well region and the second doped well region in order to be able to form the transistors of the first and second components and to increase the area of the first and second components to increase sensitivity (paragraph 29 of Endo et al.).
Claim 7: Lee in view of Huang et al. in view of Lee ‘947 in view of Endo et al. discloses the semiconductor arrangement of claim 1, and Lee, in paragraph 2, further discloses wherein at least one of:
the first component (PD2 on the left) is a first photodiode; or
the second component (PD1) is a second photodiode.
Claim 8: Lee in view of Huang et al. in view of Lee ‘947 in view of Endo et al. discloses the semiconductor arrangement of claim 1, and Lee, in Fig. 2, further discloses comprising:
a buffer layer (23) between the first portion of the substrate and the first portion of the gap fill layer.
Claim 27: Lee in view of Huang et al. in view of Lee ‘947 in view of Endo et al. discloses the semiconductor arrangement of claim 1, and Lee, in Fig. 2, further discloses wherein the gap fill layer (25) extends continuously between the first portion of the gap fill layer and a third portion (portion of 25 above PD1) of the gap fill layer (25) overlying the second component (PD1).
Claim(s) 9, 11, 14, 15, 26 and 31 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (U.S. Pub. 2019/0148427) in view of U.S. Pub. 2019/0096947, hereinafter referred to as Lee ‘947, in view of Cheng et al. (U.S. Pub. 2019/0096951) in view of Endo et al. (U.S. Pub. 2018/0114808).
Claim 9: Lee discloses a semiconductor arrangement, in annotated Fig. 2 below and in paragraphs 17-21 and 36, comprising:
a first component (PD2 on the left) in a substrate (1);
a second component (PD1) in the substrate (1);
a buffer layer (23) overlying the first component (PD2 on the left)
a gap fill layer (25) overlying the buffer layer (23), wherein:
a first portion of the gap fill layer (25) overlies the first component (PD2 on the left);
a second portion of the gap fill layer (25) is disposed laterally between the first component (PD2 on the left) and the second component (PD1);
a first portion of the substrate (1) separates the second portion of the gap fill layer from the first component (PD2 on the left); and
a third portion of the gap fill layer (25);
a passivation layer (41); and
a connection structure (39) extending through the substrate (1) and in contact with the gap fill layer (25).
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Lee appears not to explicitly disclose the gap fill layer comprises a metal,
wherein the metal of the gap fill layer is between the passivation layer and the first component.
Lee ‘947, however, in Fig. 9 and in paragraphs 34, 41 and 45, the dielectric material (104a and 302) comprising a metal is a suitable material for the gap fill layer (104a and 302) that is between the passivation layer (306) and the first component (PD1).
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Lee with the disclosure of Lee ‘947 to have made the gap fill layer comprises a metal, wherein the metal of the gap fill layer is between the passivation layer and the first component because the selection of a known material based on its suitability for its intended purpose is obvious (see, for example, M.P.E.P. § 2144.07, and precedents cited therein).
Lee also appears not to explicitly disclose a first grid structure overlying the second portion of the gap fill layer and a second grid structure overlying the third portion of the gap fill layer, wherein the first grid structure is separated from the second grid structure by the passivation layer and the passivation layer overlies the first grid structure.
Cheng et al., however, in Fig. 9 and in paragraph 40 and 41, discloses a first grid structure (the two left 906) overlying the second portion (portion of 902 between 106A and 106B) of the gap fill layer (902) and a second grid structure (the two right 906) overlying the third portion (portion of 902 over and to the right of 106B) of the gap fill layer (902), wherein the first grid structure (the two left 906) is separated from the second grid structure (the two right 906) by the passivation layer (908) and the passivation layer (908) overlies the first grid structure (the two left 906) in order to reduce crosstalk between pixels.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify Lee with the disclosure of Cheng et al. to have made a first grid structure overlying the second portion of the gap fill layer and a second grid structure overlying the third portion of the gap fill layer, wherein the first grid structure is separated from the second grid structure by the passivation layer and the passivation layer overlies the first grid structure in order to reduce crosstalk between pixels (paragraph 40 of Cheng et al.).
Lee also appears not to explicitly disclose an interconnect layer under the substrate;
a transistor under the interconnect layer, wherein the transistor is separated from the substrate by the interconnect layer and the transistor underlies the first component; and
a doped well region underlying the transistor, wherein the doped well region underlies the first gird structure and underlies the first component.
Endo et al., however, in Fig. 1 and in paragraphs 29 and 34-36, discloses
an interconnect layer (107) under the substrate (104);
a transistor (left transistor with gate 126) under the interconnect layer (107), wherein the transistor (left transistor with gate 126) is separated from the substrate (104) by the interconnect layer (104) and the transistor (left transistor with gate 126) underlies the first component (left 112); and
a doped well region (124) underlying the transistor (left transistor with gate 126), wherein the doped well region (left 124) underlies the first gird structure (119) and underlies the first component (left 112) in order to increase the area of the first component and to increase sensitivity.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify Lee with the disclosure of Endo et al. to have made an interconnect layer under the substrate; a transistor under the interconnect layer, wherein the transistor is separated from the substrate by the interconnect layer and the transistor underlies the first component; and a doped well region underlying the transistor, wherein the doped well region underlies the first gird structure and underlies the first component in order to increase the area of the first component and to increase sensitivity (paragraph 29 of Endo et al.).
Claim 11: Lee in view of Lee ‘947 in view of Cheng et al. in view of Endo et al. discloses the semiconductor arrangement of claim 9, and Lee, in Fig. 2, further discloses wherein a second portion (portion of 1 to the right of PD1) of the substrate (1) separates the second portion of the gap fill layer from the second component (PD1).
Claim 14: Lee in view of Lee ‘947 in view of Cheng et al. in view of Endo et al. discloses the semiconductor arrangement of claim 9, and Lee, in annotated Fig. 2 above, further discloses wherein the first portion of the gap fill layer has a tapered sidewall.
Claim 15: Lee in view of Lee ‘947 in view of Cheng et al. in view of Endo et al. discloses the semiconductor arrangement of claim 14, and Lee, in annotated Fig. 2 above, further discloses wherein:
a second portion of the substrate separates the first portion of the gap fill layer from the first component (PD2 on the left); and
the second portion of the substrate has a tapered sidewall that aligns with the tapered sidewall of the first portion of the gap fill layer.
Claim 26: Lee in view of Lee ‘947 in view of Cheng et al. in view of Endo et al. discloses the semiconductor arrangement of claim 9.
Lee in view of Lee ‘947 in view of Cheng et al. in view of Endo et al., as applied to claim 9, appears not to explicitly disclose a dielectric layer vertically between the gap fill layer and the first grid structure.
Cheng et al., however, in Fig. 9 and in paragraph 40 and 41, further discloses a dielectric layer (904) vertically between the gap fill layer (902) and the first grid structure (the two left 906) in order to reduce crosstalk between pixels.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify Lee in view of Lee ‘947 in view of Cheng et al. in view of Endo et al., as applied to claim 9, with the further disclosure of Cheng et al. to have made a dielectric layer vertically between the gap fill layer and the first grid structure in order to reduce crosstalk between pixels (paragraph 40 of Cheng et al.).
Claim 31: Lee in view of Lee ‘947 in view of Cheng et al. in view of Endo et al. discloses the semiconductor arrangement of claim 9.
Lee in view of Lee ‘947 in view of Cheng et al. in view of Endo et al., as applied to claim 9, appears not to explicitly disclose a distance between a top of the substrate to a bottom of the first portion of the gap fill layer overlying the first component is 500 to 10,000 angstroms.
Cheng et al., however, in Figs. 6 and 9 and in paragraph 33, further discloses a distance between a top of the substrate (404) to a bottom of the first portion (902 over 106A) of the gap fill layer (902) overlying the first component (106A) is 500 to 10000 angstroms (about 20 nm to about 500 nm, that is 200 to 5000 angstroms) in order to increase the amount of light absorbed.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify Lee in view of Cheng et al. in view of Endo et al., as applied to claim 9, with the further disclosure of Cheng et al. to have made a distance between a top of the substrate to a bottom of the first portion of the gap fill layer overlying the first component is 500 to 10,000 angstroms in order to increase the amount of light absorbed (paragraph 33 of Cheng et al.). Also, in the case where the claimed ranges overlap or lie inside ranges disclosed by the prior art a prima facie case of obviousness exists (M.P.E.P. § 2144.05).
Claim(s) 21-24, 26, 32 and 33 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (U.S. Pub. 2019/0148427) in view of U.S. Pub. 2019/0096947, hereinafter referred to as Lee ‘947, in view of Huang et al. (U.S. Pub. 2018/0151759) in view of Cheng et al. (U.S. Pub. 2019/0096951) in view of Endo et al. (U.S. Pub. 2018/0114808).
Claim 21: Lee discloses a semiconductor arrangement, in Fig. 2 and in paragraphs 17-21 and 36, comprising:
a first photodiode (PD2 on the left);
a second photodiode (PD1);
a substrate (1) laterally between the first photodiode (PD2 on the left) and the second photodiode (PD1);
a gap fill layer (25), comprising:
a first portion (portion of 25 in trench between PD1 and PD2 on the left) laterally between the first photodiode (PD2 on the left) and the second photodiode (PD1) and separated from the first photodiode (PD2 on the left) by the substrate (1),
a second portion (portion of 25 above PD2 on the left) overlying the first photodiode (PD2 on the left),
a buffer layer (23) between the substrate (1) and the gap fill layer (25);
a dielectric layer (41) overlying the gap fill layer (170); and
a connection structure (39) extending through the substrate (1) and in contact with the buffer layer (23).
Lee appears not to explicitly disclose the gap fill layer comprises a metal, and the gap fill layer has a homogenous composition.
Lee ‘947, however, in Fig. 9 and in paragraphs 34 and 41, the dielectric material (104a and 302) comprising a metal is a suitable material for the gap fill layer (104a and 302) that is homogenous in composition.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Lee with the disclosure of Lee ‘947 to have made the gap fill layer comprises a metal, and the gap fill layer has a homogenous composition because the selection of a known material based on its suitability for its intended purpose is obvious (see, for example, M.P.E.P. § 2144.07, and precedents cited therein).
Lee also appears not to explicitly disclose the second portion of the gap fill layer having tapered sidewalls, and a distance from a top of the substrate to a bottom of the first portion of the gap fill layer overlying the first component is 5001 to 10,000 angstroms.
Huang et al., however, in Figs. 8 and 10 and in paragraphs 20, 29, 35 and 42, the second portion (portion of 806 above 104a) of the gap fill layer (806) having tapered sidewalls, and a distance from a top (top of 902) of the substrate (902) to a bottom (bottom of 117 and/or 817) of the first portion (117 and/or 817) of the gap fill layer (264) overlying the first component (104a) 5001 to 10000 angstrom (from 200 nm to 1000 nm, that is 2000 to 10000 angstroms) in order to increase absorption by the light sensing elements.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify Lee with the disclosure of Huang et al. to have made the second portion of the gap fill layer having tapered sidewalls, and a distance between a top of the substrate to a bottom of the first portion of the gap fill layer overlying the first component is 5001 to 10,000 angstroms in order to increase the probability of the incident light being absorbed (paragraph 35 of Huang et al.). Also, in the case where the claimed ranges overlap or lie inside ranges disclosed by the prior art a prima facie case of obviousness exists (M.P.E.P. § 2144.05).
Lee appears not to explicitly disclose a grid structure overlying the dielectric layer such that a vertical line extending perpendicular to a bottom surface of the substrate intersects the grid structure and the dielectric layer, wherein the dielectric layer is vertically between the gap fill layer and the grid structure.
Cheng et al., however, in Fig. 9 and in paragraphs 38-41, discloses a grid structure (906) overlying the dielectric layer (904) such that a vertical line extending perpendicular to a bottom surface (bottom surface of 404) of the substrate (404) intersects the grid structure (906) and the dielectric layer (904), wherein the dielectric layer (904) is vertically between the gap fill layer (902) and the grid structure (906) in order to reduce crosstalk between pixels.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify Lee with the disclosure of Cheng et al. to have made a grid structure overlying the dielectric layer such that a vertical line extending perpendicular to a bottom surface of the substrate intersects the grid structure and the dielectric layer, wherein the dielectric layer is vertically between the gap fill layer and the grid structure in order to reduce crosstalk between pixels (paragraph 40 of Cheng et al.).
Lee also appears not to explicitly disclose
a first gate structure under the substrate, wherein the first gate structure underlies the first photodiode; and
a first source/drain region under the first gate structure; and
a shallow trench isolation structure adjacent the first source/drain region and underlying the first photodiode.
Endo et al., however, in Fig. 1 and in paragraphs 29 and 34-36, discloses
a first gate structure (126 on the left) under the substrate (104), wherein the first gate structure (126 on the left) underlies the first photodiode (112 on the left); and
a first source/drain region (second from left 125) under the first gate structure (126 on the left); and
a shallow trench isolation structure (middle 127) adjacent the first source/drain region (second from left 125) and underlying the first photodiode (112 on the left) in order to increase the area of the first component and to increase sensitivity.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify Lee with the disclosure Endo et al. to have made a first gate structure under the substrate, wherein the first gate structure underlies the first photodiode; and a first source/drain region under the first gate structure; and a shallow trench isolation structure adjacent the first source/drain region and underlying the first photodiode in order to increase the area of the first component and to increase sensitivity (paragraph 29 of Endo et al.).
Claim 22: Lee in view of Huang et al. in view of Cheng et al. in view of Endo et al. discloses the semiconductor arrangement of claim 21.
Lee in view of Huang et al. in view of Cheng et al. in view of Endo et al., as applied to claim 21, appears not to explicitly disclose a second gate structure under the substrate, wherein the second gate structure underlies the first photodiode;
a second source/drain region under the second gate structure;
a first doped well region underlying the first photodiode; and
a second doped well region underlying the first photodiode and underlying the second photodiode, wherein:
the first source/drain region is disposed in the first doped well region;
the second source/drain region is disposed in the second doped well region; and
the shallow trench isolation region is between the first doped well region and the second doped well region.
Endo et al., however, in Fig. 1 and in paragraphs 29 and 34-36, further discloses a second gate structure (126 on the right) under the substrate (104), wherein the second gate structure (126 on the right) underlies the first photodiode (112 on the left);
a second source/drain region (second from the right 125) under the second gate structure (126 on the right);
a first doped well region (124 on the left) underlying the first photodiode (112 on the left); and
a second doped well region (124 on the right) underlying the first photodiode (112 on the left) and underlying the second photodiode (112 on the right), wherein:
the first source/drain region (second from the left 125) is disposed in the first doped well region (left 124);
the second source/drain region (second from the right 125) is disposed in the second doped well region (right 124); and
the shallow trench isolation region (middle 127) is between the first doped well region (left 124) and the second doped well region (right 124).
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It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify Lee in view of Huang et al. in view of Cheng et al. in view of Endo et al., as applied to claim 21, with the further disclosure of Endo et al. to have made a second gate structure under the substrate, wherein the second gate structure underlies the first photodiode; a second source/drain region under the second gate structure; a first doped well region underlying the first photodiode; and a second doped well region underlying the first photodiode and underlying the second photodiode, wherein: the first source/drain region is disposed in the first doped well region; the second source/drain region is disposed in the second doped well region; and the shallow trench isolation region is between the first doped well region and the second doped well region in order to increase the area of the first component and to increase sensitivity (paragraph 29 of Endo et al.).
Claim 23: Lee in view of Lee ‘947 in view of Huang et al. in view of Cheng et al. in view of Endo et al. discloses the semiconductor arrangement of claim 21.
Lee in view of Lee ‘947 in view of Cheng et al. in view of Endo et al., as applied to claim 21, appears not to explicitly disclose a top surface of a portion of the substrate overlying the first photodiode is non-planar.
Cheng et al., however, in Figs. 6 and 9 and in paragraph 33, further discloses a top surface (602) of a portion of the substrate (404) overlying the first photodiode (106A) is non-planar in order to increase the amount of light absorbed.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify Lee in view of Lee ‘947 in view of Cheng et al. in view of Endo et al. with the further disclosure of Cheng et al. to have made a top surface of a portion of the substrate overlying the first photodiode is non-planar in order to increase the amount of light absorbed (paragraph 33 of Cheng et al.).
Claim 24: Lee in view of Lee ‘947 in view of Huang et al. in view of Cheng et al. in view of Endo et al. discloses the semiconductor arrangement of claim 21, and Lee, in Fig. 2, further discloses wherein:
the first portion (portion of 25 in trench between PD1 and PD2 on the left) of the gap fill layer (25) is laterally between a first portion (upper portion of PD2 on the left) of the first photodiode (PD2 on the left) and a first portion (upper portion of PD1) of the second photodiode (PD1),
a second portion (lower portion of PD2 on the left) of the first photodiode (PD2 on the left) is laterally separated from a second portion (lower portion of PD1) of the second photodiode (PD1) by the substrate (1), and
the gap fill layer (25) is not laterally between the second portion (lower portion of PD2 on the left) of the first photodiode (PD2 on the left) and the second portion (lower portion of PD1) of the second photodiode (PD1).
Claim 32: Lee in view of Lee ‘947 in view of Huang et al. in view of Cheng et al. in view of Endo et al. discloses the semiconductor arrangement of claim 21.
Lee in view of Lee ‘947 in view of Huang et al. in view of Cheng et al. in view of Endo et al., as applied to claim 21, appears not to explicitly disclose wherein:
the gap fill layer comprises a third portion overlying the first photodiode and having a second tapered sidewall,
the second portion is separated from the third portion by a portion of the substrate having a planar top surface, and
the distance from the top of the substrate to the bottom of the second portion of the gap fill layer is measured from the planar top surface to the bottom of the second portion of the gap fill layer.
Cheng et al., however, in annotated Fig. 9 below and in paragraphs 16 and 27, further discloses wherein:
the gap fill layer (902) comprises a third portion overlying the first photodiode (106A) and having a second tapered sidewall, and
the second portion is separated from the third portion by a portion of the substrate (404) having a planar top surface in order to increase the likelihood of incident light being absorbed by the photodiodes.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify Lee in view of Lee ‘947 in view of Cheng et al. in view of Endo et al., as applied to claim 21, with the further disclosure of Cheng et al. to have made the gap fill layer comprises a third portion overlying the first photodiode and having a second tapered sidewall, and the second portion is separated from the third portion by a portion of the substrate having a planar top surface in order to increase the likelihood of incident light being absorbed by the photodiodes (paragraph 27 of Cheng et al.).
Lee in view of Lee ‘947 in view of Huang et al. in view of Cheng et al. in view of Endo et al. would therefore disclose the distance from the top of the substrate to the bottom of the second portion of the gap fill layer is measured from the planar top surface to the bottom of the second portion of the gap fill layer.
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Claim 33: Lee in view of Lee ‘947 in view of Huang et al. in view of Cheng et al. in view of Endo et al. discloses the semiconductor arrangement of claim 21.
Lee in view of Lee ‘947 in view of Huang et al. in view of Cheng et al. in view of Endo et al., as applied to claim 21, appears not to explicitly disclose wherein:
the gap fill layer comprises:
a third portion overlying the first photodiode and having a second tapered sidewall; and
a fourth portion overlying the first photodiode and between the second portion of the gap fill layer and the third portion of the gap fill layer, and the fourth portion has a planar bottom surface.
Cheng et al., however, in annotated Fig. 9 above and in paragraphs 16 and 27, further discloses wherein
the gap fill layer (902) comprises:
a third portion overlying the first photodiode (106A) and having a second tapered sidewall; and
a fourth portion overlying the first photodiode and between the second portion of the gap fill layer and the third portion of the gap fill layer, and the fourth portion has a planar bottom surface in order to increase the likelihood of incident light being absorbed by the photodiodes.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify Lee in view of Lee ‘947 in view of Cheng et al. in view of Endo et al., as applied to claim 21, with the further disclosure of Cheng et al. to have made the gap fill layer comprises: a third portion overlying the first photodiode and having a second tapered sidewall; and a fourth portion overlying the first photodiode and between the second portion of the gap fill layer and the third portion of the gap fill layer, and the fourth portion has a planar bottom surface in order to increase the likelihood of incident light being absorbed by the photodiodes (paragraph 27 of Cheng et al.).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-5, 7-9, 11, 14, 15, 21-24, 26, 27 and 31-33 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/J.L/ Examiner, Art Unit 2815
/JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815
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