Detailed Action
This office action is in response to the request for continued examination filed on March 18th, 2026. Claims 1-4, 6-14, 21-22, and 24-28 are pending. Claims 3 and 13 have been withdrawn.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on March 18th, 2026, has been entered.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on June 12th, 2026, was filed prior to the mailing date of the response to the request for continued examination. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Arguments
Applicant's arguments filed March 18th, 2026, have been fully considered but they are not persuasive.
Applicant argues (pgs. 9-10, “Remarks”) that Hsu, Bhagavat, and the other cited references fail to teach the limitations presented in amended Claims 1, 8, and 21.
However, as seen below Claims 1 and 8 are rejected by Hsu, Hung, Chen, Ramachandran, and Pancholi. Claim 21 is rejected by Bhagavat, Hung, Scanlan, Ramachandran, Lai, Chen, and Pancholi.
Therefore, applicant’s arguments are not persuasive and are moot in view of the new grounds of rejection.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-2, 4, 6-7, 9, 21-22, and 24-28 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the redistribution structure" in lines 9 and 21. It is unclear if the limitation is the first, second, or a third different redistribution structure. For the purpose of examination the limitation will be interpreted as “the second redistribution structure”.
Claim 6 recites the limitation "the redistribution structure" in line 2. There is insufficient antecedent basis for this limitation in the claim. It is unclear if the limitation is the first, second, or a third different redistribution structure. For the purpose of examination the limitation will be interpreted as “the second redistribution structure”.
Claim 7 recites the limitation "the redistribution structure" in line 2. There is insufficient antecedent basis for this limitation in the claim. It is unclear if the limitation is the first, second, or a third different redistribution structure. For the purpose of examination the limitation will be interpreted as “the second redistribution structure”.
Claim 9 recites the limitation "a third integrated passive device" in line 2. It is unclear if the limitation is the third integrated passive device defined in Claim 8 or a different one. For the purpose of examination the limitation will be interpreted as “a fourth redistribution structure”.
Claim 21 recites the limitation “nearest sidewall” in line 10. This description is inconsistent with figure 5A and paragraphs [0042] and [0057] of applicant’s filed specification where a distance to a sidewall is defined. However, the depicted distance is not to the “nearest sidewall” and the filed specification does not use or define the term “nearest”. For the purpose of examination, the limitation will be interpreted as “nearest outer sidewall”.
Claim 26 recites the limitation "a first functional die" in line 2. It is unclear if the limitation is the first functional die defined in Claim 21 or a different one. For the purpose of examination the limitation will be interpreted as “the first functional die”.
Claim 26 recites the limitation "an encapsulant" in line 3. It is unclear if the limitation is the first functional die defined in Claim 21 or a different one. For the purpose of examination the limitation will be interpreted as “another encapsulant”.
Claim 27 recites the limitation “nearest sidewall” in line 2. This description is inconsistent with figure 5A and paragraphs [0042] and [0057] of applicant’s filed specification where a distance to a sidewall is defined. However, the depicted distance is not to the “nearest sidewall” and the filed specification does not use or define the term “nearest”. For the purpose of examination, the limitation will be interpreted as “nearest outer sidewall”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate that the corresponding limitations are addressed with a secondary reference/embodiment in an obviousness analysis.
Claims 1-2, 4, 6-12, and 27-28 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (2017/0229322 A1; hereinafter Hsu) in view of Hung et al. (2018/0025992 A1; hereinafter Hung), Chen et al. (2018/0374821 A1; hereinafter Chen), Ramachandran et al. (2020/0176427 A1; hereinafter Ramachandran), and Pancholi et al. (2019/0348389 A1; hereinafter Pancholi).
Regarding Claim 1, Hsu (fig. 10G) teaches a semiconductor device ([0121], 1000) comprising:
a first redistribution structure ([0109], 906);
a first integrated passive device (IPD) ([0028], a first 112) bonded to the first redistribution structure (906);
a second IPD ([0028], a second 112, see fig. 1F) bonded to the first redistribution structure (906);
a first molding compound ([0035], 116) encapsulating the first IPD (first 112) and planar with external contacts ([0074], 504, see fig. 5C) of the first IPD (first 112) and the second IPD (second 112)
a second redistribution structure ([0082], 511) over and electrically connected to the first IPD (first 112);
a third IPD ([0083], 512) on an opposing side of [second] the redistribution structure (511) as the first IPD (first 112), wherein the third IPD (512) is electrically connected to the first IPD (first 112) by the second redistribution structure (511), wherein
capacitors ([0029]) within the first IPD (first 112) and the third IPD (512) are interconnected in a parallel arrangement, wherein
the third IPD is a more advanced process node than the first IPD; and
a second molding compound ([0084], 516) encapsulating the third IPD (512);
a conductive feature ([0116], 1002) extending through the first molding compound (116), wherein the conductive feature (1002) comprises:
a conductive via (1002); and
a solder region on the conductive via, wherein at least a portion of the solder region is embedded within the first molding compound, wherein
the solder region has a first height that is larger than a second height of a portion of the first molding compound located between the first IPD and the redistribution structure; and
an array of external connectors ([0067], 404) on an opposite side of the first IDP (first 112) from the second IPD (second 112), the array of external connectors (404) comprising parallel lines of ground connections and power connections;
a third redistribution structure ([0027], 111) bonded to the array of external connectors (404); and
a first functional die bonded to the third redistribution structure.
Hsu doesn’t teach a solder region on the conductive via, wherein at least a portion of the solder region is embedded within the first molding compound, wherein the solder region has a first height that is larger than a second height of a portion of the first molding compound located between the first IPD and the redistribution structure.
However, Hung (fig. 6) teaches a solder region ([0042], 46) on the conductive via ([0042], 90), wherein at least a portion of the solder region (46) is embedded within the first molding compound ([0042], 78), wherein the solder region (46) has a first height (height of 46, referred to as first height, see annotated fig. 6) that is larger (see fig. 6) than a second height (height of the portion of 78 between 70 and 20, referred to as second height, see annotated fig. 6) of a portion of the first molding compound (78) located between the first IPD ([0042], 70) and the redistribution structure ([0042], 20). Hung also teaches the solder region is formed by a low temperature operation and helps prevent thermal damage ([0043]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Hsu to include the solder region of Hung to prevent thermal damage.
Hsu doesn’t teach the array of external connectors comprising parallel lines of ground connections and power connections.
However, in another embodiment, Hsu (figs. 4H-4I) teaches the array of external connectors ([0071], 404) comprising parallel lines of ground connections and power connections ([0064], 404 are arranged in parallel lines and connected to power and ground features 106, see annotated fig. 4I). Hsu also teaches this provides external power and ground to the device package ([0071]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Hsu to include the power and ground of Hsu to provide power and ground to the device package.
Hsu doesn’t teach capacitors within the first IPD and the third IPD are interconnected in a parallel arrangement.
However, Ramachandran (fig. 6) teaches capacitors ([0032], 102) within the first IPD ([0037], 204) and the third IPD ([0037], 100) are interconnected in a parallel arrangement ([0033], [0037], both sets of 102 within 100 and 204 may be parallel and then are electrically connected to each other). It is well known that a parallel arrangement of capacitors increases the overall capacitance.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Hsu to include the parallel capacitors of Ramachandran to increase capacitance.
Hsu doesn’t teach the third IPD is a more advanced process node than the first IPD.
However, Pancholi (fig. 1) teaches the third IPD ([0027], 101) is a more advanced process node than the first IPD ([0027], 121). Pancholi also teaches that this may reduce cost ([0027]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Hsu to include different process nodes of Pancholi to reduce cost.
Hsu doesn’t teach a first functional die bonded to the third redistribution structure.
However, Chen (fig. 10I) teaches a first functional die ([0026], 102) bonded to the third redistribution structure ([0026], 101). Chen also teaches that this forms a single electronic module with different electronic devices performing different functionalities ([0019]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Hsu to include the first functional die of Chen to provide a single electronic module with multiple functionalities.
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Regarding Claim 2, Hsu (fig. 10G) teaches the semiconductor device of claim 1, wherein a face of the first IPD (first 112) faces a face of the second IPD (second 112).
Regarding Claim 4, Hsu (fig. 10G) teaches the semiconductor device of claim 1 further comprising a second conductive via (a second 1002) extending through the first molding compound (116).
Regarding Claim 6, Hsu (fig. 10G) teaches the semiconductor device of claim 1, wherein the first IPD (first IPD) is electrically connected to the redistribution structure (511) by a copper pillar ([0031], 1002).
Regarding Claim 7, the combination of Hsu and Hung teaches the semiconductor device of claim 1, wherein the first IPD (Hsu, first 112) is electrically connected to the redistribution structure (Hsu, 511) by the solder region (Hung, 46).
Regarding Claim 8, Hsu (fig. 10G) teaches a semiconductor device ([0120]-[0121], 1000, 150) comprising:
a first redistribution structure ([0043], 150);
a first functional die bonded to the first redistribution structure using a plurality of external connections ([0067], 404), wherein
the plurality of external connections comprises parallel lines of ground connections and power connections; and
a first integrated passive device stack (1000) bonded to the first redistribution structure (150), the first integrated passive device stack (1000) comprising:
a second redistribution structure ([0027], 111);
a first integrated passive device ([0028], a first 112) over and bonded to the second redistribution structure (111);
a second integrated passive device ([0115], a second 112, not shown) over and bonded to the second redistribution structure (111);
a first molding compound ([0035], 116) encapsulating the first integrated passive device (first 112), the first molding compound (116) being planar with external die contacts ([0074], 504, see fig. 5F) of the first integrated passive device (first 112);
a third redistribution structure ([0082], 511) over the first integrated passive device (first 112),
the third redistribution structure (511) being connected to the second redistribution structure (111) by first through vias ([0114], 1002) that extend through the first molding compound (116), wherein
the first through vias (1002) comprise: a conductive via (1002); and
a solder region on the conductive via, wherein at least a portion of the solder region is embedded within the first molding compound, wherein
the solder region has a first height that is larger than a second height of a portion of the first molding compound located between the first integrated passive device and the third redistribution structure; and
a third integrated passive device ([0083], 512) over and bonded to the third redistribution structure (511),
the third integrated passive device (512) comprising second external connections ([0083], 514) along a first side of the third integrated passive device (512), wherein
capacitors ([0029]) within the first integrated passive device (first 112) and the third integrated passive device (512) are interconnected in a parallel arrangement, wherein
the third integrated passive device is a more advanced process node than the first integrated passive device.
Hsu doesn’t teach a first functional die bonded to the first redistribution structure.
However, Chen (fig. 10I) teaches a first functional die ([0026], 102) bonded to the first redistribution structure ([0026], 101). Chen also teaches that this forms a single electronic module with different electronic devices performing different functionalities ([0019]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Hsu to include the first functional die of Chen to provide a single electronic module with multiple functionalities.
Hsu doesn’t teach the plurality of external connections comprises parallel lines of ground connections and power connections.
However, in another embodiment, Hsu (figs. 4H-4I) teaches the plurality of external connections ([0071], 404) comprises parallel lines of ground connections and power connections ([0064], 404 are arranged in parallel lines and connected to power and ground features 106, see annotated fig. 4I). Hsu also teaches this provides external power and ground to the device package ([0071]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Hsu to include the power and ground of Hsu to provide power and ground to the device package.
Hsu doesn’t teach a solder region on the conductive via, wherein at least a portion of the solder region is embedded within the first molding compound, wherein the solder region has a first height that is larger than a second height of a portion of the first molding compound located between the first integrated passive device and the third redistribution structure.
However, Hung (fig. 6) teaches a solder region ([0042], 46) on the conductive via ([0042], 90), wherein at least a portion of the solder region (46) is embedded within the first molding compound ([0042], 78), wherein the solder region (46) has a first height (height of 46,referred to as first height, see annotated fig. 6) that is larger (see fig. 6) than a second height (height of the portion of 78 between 70 and 20, referred to as second height, see annotated fig. 6) of a portion of the first molding compound (78) located between the first integrated passive device ([0042], 70) and the third redistribution structure ([0042], 20). Hung also teaches the solder region is formed by a low temperature operation and helps prevent thermal damage ([0043]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Hsu to include the solder region of Hung to prevent thermal damage.
Hsu doesn’t teach capacitors within the first integrated passive device and the third integrated passive device are interconnected in a parallel arrangement.
However, Ramachandran (fig. 6) teaches capacitors ([0032], 102) within the first integrated passive device ([0037], 204) and the third integrated passive device ([0037], 100) are interconnected in a parallel arrangement ([0033], [0037], both sets of 102 within 100 and 204 may be parallel and then are electrically connected to each other). It is well known that a parallel arrangement of capacitors increases the overall capacitance.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Hsu to include the parallel capacitors of Ramachandran to increase capacitance.
Hsu doesn’t teach the third integrated passive device is a more advanced process node than the first integrated passive device.
However, Pancholi (fig. 1) teaches the third integrated passive device ([0027], 101) is a more advanced process node than the first integrated passive device ([0027], 121). Pancholi also teaches that this may reduce cost ([0027]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Hsu to include different process nodes of Pancholi to reduce cost.
Regarding Claim 9, Hsu (fig. 10G) teaches the semiconductor device of claim 8, further comprising: a third integrated passive device (a third 112) between the second redistribution structure (111) and the third redistribution structure (511); and a first encapsulant (116) surrounding the third integrated passive device (a third 112) and the first integrated passive device (a first 112).
Regarding Claim 10, Hsu (fig. 10G) teaches the semiconductor device of claim 8, wherein the first through vias (1002) comprise copper pillars ([0031]).
Regarding Claim 11, the combination of Hsu and Hung teaches the semiconductor device of claim 10, wherein the first through vias (Hsu, 1002) comprise: copper pillars (Hsu, [0031]); and solder balls (Hung, 46) in physical contact with the copper pillars (Hsu, 1002).
Regarding Claim 12, Hsu (fig. 10G) teaches the semiconductor device of claim 8, wherein the first integrated passive device (first 112) and the second integrated passive device (112) are configured in a face-to-face configuration.
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Hsu, Chen, Ramachandran, Pancholi, and Hung as applied to Claim 8 above, and further in view of Scanlan et al. (2016/0093580 A1; hereinafter Scanlan).
Regarding Claim 27, Hsu doesn’t teach the semiconductor device of claim 8, wherein a sidewall of the first integrated passive device is spaced apart from a nearest sidewall of an encapsulant by a distance of between about 50μm and about 2000μm.
However, Scanlan (fig. 7) teaches a sidewall of the first integrated passive device ([0103], outer sidewall of 24) is spaced apart from a nearest sidewall of an encapsulant ([0103], outer sidewall of 182) by a distance of between about 50μm and about 2000μm ([0103], O1). Scanlan also teaches this distance helps prevent chipping ([0103]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Hsu to include the spacing of Scanlan to help prevent chipping.
Claim 28 is rejected under 35 U.S.C. 103 as being unpatentable over Hsu, Chen, Ramachandran, Pancholi, and Hung as applied to Claim 1 above, and further in view of Scanlan.
Regarding Claim 28, Hsu doesn’t teach the semiconductor device of claim 1, wherein a sidewall of the first molding compound is located between about 50μm and about 2000μm from the first IPD.
However, Scanlan (fig. 7) teaches a sidewall of the first molding compound ([0103], 182) is located between about 50μm and about 2000μm ([0103]) from the first IPD ([0103], 24). Scanlan also teaches this distance helps prevent chipping ([0103]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Hsu to include the spacing of Scanlan to help prevent chipping.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Hsu, Chen, Ramachandran, Pancholi, and Hung as applied to Claim 8 above, and further in view of Liu et al. (2017/0098629 A1; hereinafter Liu)
Regarding Claim 14, Hsu doesn’t teach the semiconductor device of claim 8, wherein the first integrated passive device stack further comprises: a fourth redistribution structure over the second integrated passive device, the fourth redistribution structure being connected to the third redistribution structure by second through vias; and a third integrated passive device over the fourth redistribution structure.
However, Liu (fig. 3) teaches a semiconductor device comprising an additional redistribution structure ([0023], 104) over the second integrated device ([0027], 200), the additional redistribution structure being connected to the underlying redistribution structure ([0030], 204) by second through vias ([0034], 306), and a third integrated device ([0021], 100) over the additional redistribution structure (104). Furthermore, it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPC 8.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a fourth redistribution structure over the second integrated passive device, the fourth redistribution structure being connected to the third redistribution structure by second through vias; and a third integrated passive device over the fourth redistribution structure in order to provide the integrated passive device stack including multilevel integrated passive devices.
Claims 21-22 and 25-26 are rejected under 35 U.S.C. 103 as being unpatentable over Bhagavat et al. (2020/0312766 A1; hereinafter Bhagavat) in view of Hung, Lai et al. (2019/0385941 A1; hereinafter Lai), Scanlan, Ramachandran, Pancholi, and Chen.
Regarding Claim 21, Bhagavat (fig. 2) teaches a semiconductor device ([0050], 105) comprising:
through vias ([0055], 205a) over a first redistribution structure ([0053], 172), wherein the through vias (205a) comprise:
a conductive via (205a); and
a solder region on the conductive via;
a first integrated passive device ([0053], 155) on the first redistribution structure (172) adjacent to the through vias (205a);
a second integrated passive device ([0053], 150) on the first redistribution structure (172) adjacent to the through vias (205a);
an encapsulant ([0050], 120) encapsulating the first integrated passive device (155) and the through vias (205a), wherein
a sidewall of the first integrated passive device is spaced apart from a nearest sidewall of the encapsulant by a distance of between about 50μm and about 2000μm, wherein
the encapsulant (120) is co-planar (see fig. 13) with external contacts ([0056], 205b/205c) of the first integrated passive device (155), wherein at least a portion of the solder region is embedded within the encapsulant;
a second redistribution structure ([0050], 115) over the encapsulant (120) and in electrical connection with the through vias (205a);
a third integrated passive device ([0054], 130) fusion bonded to the second redistribution structure (115) and in electrical connection with the through vias (205a), wherein
capacitors within the first integrated passive device (155) and the third integrated passive device (130) are interconnected in a parallel arrangement, wherein
the third integrated passive device is a more advanced process node than the first integrated passive device, and wherein
the first integrated passive device (155) is attached to the first redistribution structure (172) with an adhesive ([0058], 235);
a plurality of external connections ([0057], 220) on the first redistribution structure (172), wherein
the plurality of external connections are arranged in an array of rows and columns, and wherein
the plurality of external connections comprises parallel lines of ground connections and power connections;
a third redistribution structure bonded to the plurality of external connections; and
a first functional die bonded to the third redistribution structure.
Bhagavat doesn’t teach a solder region on the conductive via and at least a portion of the solder region is embedded within the encapsulant.
However, Hung (fig. 6) teaches a solder region ([0042], 46) on the conductive via ([0042], 90) and at least a portion of the solder region (46) is embedded within the encapsulant ([0042], 78). Hung also teaches the solder region is formed by a low temperature operation and helps prevent thermal damage ([0043]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Hsu to include the solder region of Hung to prevent thermal damage.
Bhagavat doesn’t teach a sidewall of the first integrated passive device is spaced apart from a nearest sidewall of the encapsulant by a distance of between about 50μm and about 2000μm.
However, Scanlan (fig. 7) teaches a sidewall of the first integrated passive device ([0103], outer sidewall of 24) is spaced apart from a nearest sidewall of the encapsulant ([0103], outer sidewall of 182) by a distance of between about 50μm and about 2000μm ([0103], O1). Scanlan also teaches this distance helps prevent chipping ([0103]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Bhagavat to include the spacing of Scanlan to help prevent chipping.
Bhagavat doesn’t teach capacitors within the first IPD and the third IPD are interconnected in a parallel arrangement.
However, Ramachandran (fig. 6) teaches capacitors ([0032], 102) within the first IPD ([0037], 204) and the third IPD ([0037], 100) are interconnected in a parallel arrangement ([0033], [0037], both sets of 102 within 100 and 204 may be parallel and then are electrically connected to each other). One of ordinary skill in the art could have substituted the integrated passive device of Ramachandran for the integrated passive device of Bhagavat and yielded the predictable results of a functional device package.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the integrated passive device of Ramachandran for the integrated passive device of Bhagavat, since simple substitution of passive devices for another is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Bhagavat doesn’t teach the third integrated passive device is a more advanced process node than the first integrated passive device.
However, Pancholi (fig. 1) teaches the third integrated passive device ([0027], 101) is a more advanced process node than the first integrated passive device ([0027], 121). Pancholi also teaches that this may reduce cost ([0027]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Bhagavat to include different process nodes of Pancholi to reduce cost.
Bhagavat doesn’t teach a third redistribution structure bonded to the plurality of external connections; and a first functional die bonded to the third redistribution structure.
However, Chen (fig. 10I) teaches a third redistribution structure ([0026], 101) bonded to the plurality of external connections ([0021], 103); and a first functional die ([0026], 102) bonded to the third redistribution structure ([0026], 101). Chen also teaches that this forms a single electronic module with different electronic devices performing different functionalities ([0019]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Bhagavat to include the first functional die of Chen to provide a single electronic module with multiple functionalities.
Bhagavat doesn’t teach the plurality of external connections are arranged in an array of rows and columns, and wherein the plurality of external connections comprises parallel lines of ground connections and power connections.
However, Lai (figs. 4-6) teaches a plurality of external connections ([0050]-[0051], G2, P2) are arranged in an array of rows and columns (see fig. 4), and wherein the plurality of external connections (G2, P2) comprises parallel lines of ground connections and power connections ([0050], G2 and P2 are arranged in parallel lines and provide power and ground connections). Lai also teaches rows and columns of power and ground connections reduce parasitic inductance ([0063]-[0064]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Bhagavat to include external connections of Lai to reduce parasitic inductance.
Regarding Claim 22, Bhagavat (fig. 2) teaches the semiconductor device of claim 21, wherein the first integrated passive device (155) is in electrical connection with the first redistribution structure (172).
Regarding Claim 24, Ramachandran (fig. 6) teaches the semiconductor device of claim 21, wherein the first integrated passive device (204) is an integrated passive capacitor ([0037]).
Regarding Claim 25, Bhagavat (fig. 2) teaches the semiconductor device of claim 21, further comprising a third redistribution layer ([0059], 110, see fig. 1) bonded to the first redistribution structure (172).
Regarding Claim 26, Chen (fig. 10I) teaches the semiconductor device of claim 25, further comprising: a first functional die (102) bonded to the third redistribution layer (101); and an encapsulant ([0021], 105) encapsulating the first functional die (102).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hung et al. (2014/0252646 A1) teaches a package-on-package device. See fig. 22 and [0040]-[0043].
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/A.H./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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