Prosecution Insights
Last updated: April 19, 2026
Application No. 17/025,972

PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

Non-Final OA §102
Filed
Sep 18, 2020
Examiner
CHEN, JACK S J
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Advanced Semiconductor Engineering Inc.
OA Round
1 (Non-Final)
76%
Grant Probability
Favorable
1-2
OA Rounds
2y 10m
To Grant
82%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allow Rate
432 granted / 565 resolved
+8.5% vs TC avg
Moderate +6% lift
Without
With
+5.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
33 currently pending
Career history
598
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
30.0%
-10.0% vs TC avg
§102
34.2%
-5.8% vs TC avg
§112
26.3%
-13.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 565 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Group I, Species 7 in the reply filed on 11/16/2022 is acknowledged. While Examiner acknowledges that Applicant indicated that claims 28-32 read on the elected species 7 (fig. 9). These claims do not read on the elected species because the elected species at least fails to show having a space defined between a top surface of the second electronic device and a first lateral surface of the first electronic device; and a reinforcement structure disposed in the space. Therefore, they are withdrawn from further consideration. Claims 28-32 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 11/16/2022. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1-4, 10-12, 14 and 21-27 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cho, CN 109979889 A. Re claim 1. Cho discloses a package structure, comprising: a redistribution structure 110 (i.e., figs. 7, 8, 10, 11, 12 or 13); a first electronic device 120’ (i.e, fig. 8, 10 etc.) disposed over the redistribution structure; a second electronic device 130B (i.e., fig. 8, 10 etc.) disposed over the redistribution structure; and a reinforcement structure 150 B (i.e, fig. 8, 10 etc.) disposed over the second electronic device 130B; wherein the first electronic device 120’ horizontally overlaps the reinforcement structure 150B (i.e, fig. 8, 10 etc.), see figs. 1-13 and pages 1-13 for more details. Re claim 2. The package structure of claim 1, wherein a portion of the reinforcement structure 150 is over the first electronic device 120’ (i.e, fig. 8, 10 etc.). Re claim 3. The package structure of claim 2, wherein the reinforcement structure 150 B is bonded to a portion of a top surface of the first electronic device 120’ and the second electronic device 130B through an adhesive layer 161 (i.e, fig. 8, 10 etc.). Re claim 4. The package structure of claim 1, wherein a width of the reinforcement structure 150B is greater than a width of a spacing between the first electronic device 120’ and the second electronic device 130B (i.e, fig. 8, 10 etc.). Re claim 10. The package structure of claim 1, further comprising an encapsulant 160 Re claim 11. The package structure of claim 1, wherein a width of the reinforcement structure 150B is greater than a width of the second electronic device 130B (i.e, fig. 8, 10 etc.). Re claim 12. The package structure of claim 11, wherein the reinforcement structure 150B covers an entire top surface of the second electronic device 130B (i.e, fig. 8, 10 etc.). Re claim 14. The package structure of claim 3, further comprising a heat dissipation structure 170 attached to the first electronic device 120’, the second electronic device 130B and the reinforcement structure 150B through a thermal material 180 (i.e., fig. 10), wherein the thermal material 180 contacts the adhesive layer (i.e., fig. 10). Re claim 21. The package structure of claim 3, wherein the adhesive layer 161 includes a portion disposed between a first lateral surface of the reinforcement structure 150B and a second lateral surface of the first electronic device 120’ facing the first lateral surface of the reinforcement structure 150B (i.e., fig. 8). Re claim 22. The package structure of claim 3, further comprising a protection layer (i.e. fig. 8, where s2 is located) disposed between the first electronic device 120’ and the second electronic device 130B, wherein the adhesive layer 161 is disposed between the protection layer and the reinforcement structure (i.e., fig. 8). Re claim 23. The package structure of claim 22, wherein the adhesive layer 161 contacts an entire top surface of the protection layer (i.e., fig. 8). Re claim 24. The package structure of claim 1, wherein the first electronic device 120’ includes a first top surface having a first elevation and a second top surface having a second elevation higher than the first elevation (i.e., fig. 8, 10), and a top surface of the reinforcement structure 150B is level with the second top surface of the first electronic device 120’ (i.e., fig. 8 or 10). Re claim 25. The package structure of claim 24, wherein a third top surface of the second electronic device 130B is lower than the second top surface of the first electronic device 120’ (fig. 8 or 10). Re claim 26. The package structure of claim 24, wherein a third top surface of the second electronic device 130B is level with the first top surface of the first electronic device 120’ (fig. 8). Re claim 27. The package structure of claim 24, wherein the first electronic device 120’ further includes a lateral surface extending between the first top surface and the second top surface, and a vertical length of the lateral surface is greater than a thickness of the reinforcement structure 150B in a cross-sectional view (fig. 8 or 10). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACK CHEN whose telephone number is (571)272-1689. The examiner can normally be reached Monday to Friday, 8am to 4pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J. Green can be reached on (571)270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JACK S CHEN/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Sep 18, 2020
Application Filed
Nov 16, 2022
Response after Non-Final Action
Aug 05, 2024
Response Filed
Aug 05, 2024
Response after Non-Final Action
Dec 02, 2024
Interview Requested
Apr 18, 2025
Non-Final Rejection — §102
Sep 23, 2025
Response after Non-Final Action
Sep 23, 2025
Response Filed

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
76%
Grant Probability
82%
With Interview (+5.9%)
2y 10m
Median Time to Grant
Low
PTA Risk
Based on 565 resolved cases by this examiner. Grant probability derived from career allow rate.

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