DETAILED ACTION
Table of Contents
I. Notice of Pre-AIA or AIA Status 3
II. Claim Rejections - 35 USC § 112 3
A. Claims 33-35 are rejected under 35 U.S.C. 112(a) as failing to comply with the enablement requirement. 3
B. Claim 18 is rejected under 35 U.S.C. 112(d) as being of improper dependent form … 6
III. Claim Rejections - 35 USC § 103 7
A. Claims 1-4, 7, 11, 12, 32, and 13-15, 17-20, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over US 2012/0202357 (“Sato”) in view of US 2007/0093012 (“Chua”), US 2006/0051506 (“Senzaki”), and as evidenced by US 2005/0236626 (“Takafuji”). 7
B. Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Sato in view of Chua, Senzaki, and as evidenced by Takafuji, as applied to claim 1 above, and further in view of US 5,849,643 (“Gilmer”). 26
C. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Sato in view of Chua, Senzaki, and as evidenced by Takafuji, as applied to claim 1 above, and further in view of US 2003/0049942 (“Haukka”). 27
D. Claim 16 is under 35 U.S.C. as being unpatentable over Sato in view of Chua, Senzaki, and as evidenced by Takafuji, as applied to claim 13, above, and further in view of US 2008/0057659 (“Forbes”). 28
E. Claim 31 is rejected under 35 U.S.C. 103 as being unpatentable over Sato in view of Chua, Senzaki, and as evidenced by Takafuji, as applied to claim 1 above, and further in view of US. 2008/0258219 (“Thean”). 29
IV. Response to Arguments 30
Conclusion 31
[The rest of this page is intentionally left blank.]
I. Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
II. Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
A. Claims 33-35 are rejected under 35 U.S.C. 112(a) as failing to comply with the enablement requirement.
The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention, without undue experimentation.
Claims 33-35 read,
33. (New) The method of forming a semiconductor structure of claim 1, wherein post-treating the high-k dielectric material with N2 is performed at a temperature below 300° C.
34. (New) The method of forming a semiconductor structure of claim 13, wherein post-treating the high-k dielectric material with N2 is performed at a temperature below 300° C.
35. (New) The method of forming a semiconductor structure of claim 21, wherein post-treating the high-k dielectric material with N2 is performed at a temperature below 300° C.
The specification fails to provide enabling disclosure for inserting the claimed “about 10 at.% to about 10 at.% nitrogen” into a high-k dielectric of any composition using specifically N2 gas at a temperature below 300 ℃, as required by claims 33-35. In this regard, it is noted that the specification fails to provide empirical data or even one example of even one single process of any kind using to insert the nitrogen, instead, providing a series lists of process types (¶ 47, infra), nitrogen-containing gases (¶ 47, infra), temperature ranges (¶ 49, infra), and atomic percentage (at.%) ranges of incorporation into any high-k dielectric (¶ 48, infra). Particularly, with regard to the lists, the specification states,
[0047] Post-treatment operations may additionally include further contacting the substrate with a second nitrogen-containing precursor relative to the pre-treatment nitrogen-containing precursor, when used. The second nitrogen-containing precursor may include any nitrogen-containing precursor described above, and may include nitrogen gas, as well as any nitrogen-containing precursor noted elsewhere. The second nitrogen-containing precursor may include a plasma-activated or enhanced nitrogen-containing precursor, a thermally-activated nitrogen, or some other nitrogen precursor, which may allow nitrogen radicals or nitrogen atoms to be incorporated within the high-k structure, which may stabilize the film or settle the film towards an equilibrium state. …
[0048] Nitrogen incorporation may be controlled to limit the incorporation in the film, in order to maintain the structural and electrical properties. In some embodiments, a post-treatment nitridation may incorporate less than or about 20 atomic % nitrogen at a surface region of the high-k film, and may incorporate less than or about 15 atomic % nitrogen, less than or about 10 atomic % nitrogen, less than or about 8 atomic % nitrogen, less than or about 6 atomic % nitrogen, less than or about 4 atomic % nitrogen, less than or about 2 atomic % nitrogen, or less. In some embodiments, an incorporation between about 3 atomic % and about 7 atomic % may maintain a higher k-value than higher nitrogen incorporation, and may better stabilize the film than lower nitrogen incorporation. By surface region may be meant an exposed surface of the material, although the nitrogen incorporation may extend to any distance within the film, and may be consistent, or form a reducing gradient through the material.
[0049] A post-treatment oxidation or nitridation may be performed at any of the temperatures noted previously, although in some embodiments the post-treatment oxidation and/or nitridation may be performed at a temperature range below or about 500° C., and may be performed at a temperature range below or about 400° C., below or about 300° C., below or about 200° C., below or about 100° C., or less depending on the operation being performed.
(Instant Specification: ¶¶ 48-49; emphasis added)
Thus, the Instant Inventor makes clear that the particular processing type, i.e. “operation being performed” (id.), used to insert the desired atomic percentage of nitrogen affects the temperature range that must be used. However, it is exceedingly well-known in the art that N2 gas is very stable, so stable, in fact, that it is typically used an inert carrier gas, which is the case even in the Instant Application, i.e. “The nitrogen may serve as a carrier for oxygen and may not become part of the interface or substrate” (¶ 32). Among the naturally-occurring diatomic gases N2 is the most stable because the N atoms share a triple bond having a bonding energy of 945 kJ/mol, versus a much stronger nitriding compound, ammonia (NH3) having N-H single bonds with a bonding energy of only about 389 kJ/mol.
Additional evidence that merely a temperature of 300 ℃ and N2 gas will not incorporate 10 atom% to 20 atom% N into a high-k dielectric comes from prior art reference of record, Senzaki (infra), which provides actual empirical data for a thermal nitridation of HfSiOx films with two examples using N2 gas at 363 ℃ yielding 2.2 and 1.9 atom% and one example at 450 ℃ for 30 minutes yielding 3.5 at% (Senzaki: ¶ 45). In addition, in the examples in Senzaki using rapid thermal annealing for 5 minute periods with the stronger NH3 as the nitriding gas, yielded 4.4 to 5.5 atom% N in the HfSiOx films at 700 ℃ and 18 atom% N at 800 ℃. The combined information shows that the atom% N insertion is directly related to the temperature and also related to the nitriding gas.
Based on the foregoing evidence and the lack of evidence in the Instant Application, the claimed limitation, “post-treating the high-k dielectric material with N2 is performed at a temperature below 300° C”, that must result in “about 10 at.% to about 10 at.% nitrogen” incorporated into a high-k dielectric of any composition, was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the claimed process, without undue experimentation, if it is even possible.
Examiner will consider any factual objective evidence that Applicant may provide to show that post-treating a high-k dielectric material with N2 gas performed at a temperature below 300° C” resulting in “about 10 at.% to about 10 at.% nitrogen” incorporation into the high-k dielectric.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
B. Claim 18 is rejected under 35 U.S.C. 112(d) as being of improper dependent form …
… for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Claim 18 reads,
18. (Previously Presented) The method of forming a semiconductor structure of claim 13, wherein the post-treating comprises exposing the substrate and high-k dielectric material to a nitrogen-containing precursor.
Claim 13 limits the post-treating gas to N2 gas; therefore, claim 18 broadens the claim by opening the post-treating gas to any nitrogen-containing precursor.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
III. Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A. Claims 1-4, 7, 11, 12, 32, and 13-15, 17-20, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over US 2012/0202357 (“Sato”) in view of US 2007/0093012 (“Chua”), US 2006/0051506 (“Senzaki”), and as evidenced by US 2005/0236626 (“Takafuji”).
Claim 1 reads,
1. (Currently Amended) A method of forming a semiconductor structure, the method comprising:
[1] removing a native oxide from a surface of a substrate;
[2] delivering nitrous oxide to the substrate and thermally annealing the surface to form an oxide-containing interface;
[3] subsequent to annealing the surface to form the oxide-containing interface, delivering an oxygen-containing precursor to the substrate;
[4a] contacting the substrate with the oxygen-containing precursor,
[4b] wherein the contacting introduces reactive ligands on the oxide-containing interface, and
[4c] wherein the contacting is performed at a temperature between 500 °C and 575 °C;
[5] forming a high-k dielectric material overlying the oxide-containing interface by performing an atomic layer deposition process utilizing a metal halide and water; and
[6] post-treating the high-k dielectric material with nitrogen gas (N2) to insert between about 10 at.% and about 20 at.% nitrogen in the high-k dielectric material.
With regard to claim 1, Sato discloses,
1. (Currently Amended) A method of forming a semiconductor structure, the method comprising:
[1] removing a native oxide from a surface of a substrate [¶ 25: “Step 1”];
[2] delivering …[oxygen]… to the substrate and thermally annealing the surface to form an oxide-containing interface [i.e. SiO2; Fig. 1 ¶¶ 13, 17 and ¶ 25: “Step 2”];
[3] subsequent to annealing the surface to form the oxide-containing interface, delivering an oxygen-containing precursor [H2O or NH3/H2O] to the substrate [Fig. 1; ¶¶ 13, 16-19 and ¶ 25: “Step 3”];
[4a] contacting the substrate with the oxygen-containing precursor [H2O for Samples C through I in Table 1 or NH3/H2O for Samples F through I in Table 1; ¶ 25],
[4b] wherein the contacting introduces reactive ligands [i.e. hydroxyl ligands] on the oxide-containing interface [Fig. 1; ¶¶ 13, 16-19], and
[4c] wherein the contacting is performed at a temperature between … [less than about 450 °C (¶ 15) with actual examples at 275 ℃ (¶ 25)];
[5] forming a high-k dielectric material [e.g. HfO2; ¶ 25] overlying the oxide-containing interface by performing an atomic layer deposition process utilizing a metal halide [HfCl4] and water. [¶¶ 13, 14 and ¶ 25, “Step 4”]; and
[6] … [not taught] …
With regard to feature [1] of claim 1, the dilute HF cleaning step in Sato inherently removes the native oxide, as evidenced by Takafuji at paragraph [0044], which states, “A single crystalline silicon wafer (single crystalline silicon substrate) 40 is cleaned by a general cleaning method (e.g., by which a natural oxide film is removed with dilute hydrofluoric acid, and a particle, organic matter, and the like are removed by SC1 and SC2 cleaning agents).” As such, the burden of proof is shifted to Applicant to prove the contrary. (See MPEP 2112(I)-(V).)
With regard to feature [2] of claim 1, Sato does not teach that the oxidant used to form the interfacial layer is nitrous oxide (N2O), using instead, oxygen (¶ 25: “Step 2”).
Chua, like Sato, teaches a method of making a high-k gate dielectric that includes first removing a native oxide 204 from a silicon substrate 200, then thermally oxidizing the silicon substrate to form a SiO2 interface layer 206 and then depositing a high-k dielectric layer 208 by ALD on the interface layer 206 (Chua: Figs. 1, 2A-2E; ¶¶ 22-44). Also like Sato, Chua teaches that the oxidant used for the thermal oxidation of the Si substrate 200 to form the SiO2 interface layer is oxygen (¶¶ 24-25). Chua teaches that in another embodiment nitrous oxide (N2O) can be used (Chua: ¶ 26).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use nitrous oxide (N2O) instead of oxygen as the oxidant in the process of Sato because Chua teaches that nitrous oxide (N2O) is a suitable oxidant for the same purpose of forming an interface layer upon which is subsequently deposited a high-k dielectric for making a gate dielectric (supra). As such the selection of nitrous oxide (N2O) in place of oxygen is obvious material choice. (See MPEP 2144.07.)
With regard to feature [4c] of claim 1, Sato teaches that the temperature at which the oxide-containing interface, i.e. SiO2 in Fig. 1, is contacted by the water or water plus ammonia to introduce the hydroxyls (which are reactive to aid deposition of the high-k dielectric by ALD) is at temperatures “less than about 450 °C” (¶ 15; emphasis added), which falls outside the claimed range of 500 °C to 575 °C. Nonetheless, Sato is drawn the identical endeavor as in the Instant Application of activating a silicon oxide interfacial layer by forming –OH groups to aid atomic layer deposition of a high-k gate dielectric.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use a temperature in the range of “less than about 450 °C” (id.) to expose the interface layer to the water or water/ammonia to form the reactive hydroxyl ligands because this range falls within the range claimed in Sato, and to perform said exposure for a time sufficient to form the –OH ligands because this is the purpose for said exposure, as stated in Sato.
The claimed temperature ranges for exposure to the oxygen-containing precursor of 500 ℃ to 575 ℃ is held to be prima facie obvious in the absence of unexpected results. See In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). (See MPEP 2144.05(III)(A); emphasis added.)
See also In re Huang, 40 USPQ2d 1685, 1688(Fed. Cir. 1996)(claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40°C and 80°C and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100°C and an acid concentration of 10%). (See MPEP 2144.05(I); emphasis added.) Noting that neither of the claimed and prior art temperature or concentration overlap but that a prima facie case of obviousness still exists.
In this case, the evidence of record in the Instant Application teaches away from the existence of unexpected results for using a temperature in the range of 500 °C to 575 °C relative to the temperature range of “less than about 450 ℃” in Sato. In this regard, the Instant Application states,
[0040] The pre-treatment may be performed at a temperature configured to activate the precursor and/or the surface of the substrate. For example, in a situation in which a nitrogen-and-hydrogen-containing precursor may be used as the pre-treatment precursor, the substrate may be maintained at a temperature greater than or about 300° C. while delivering the precursor. Similarly, a pre-treatment with an oxygen-containing precursor may also be performed while maintaining a substrate temperature greater than or about 300° C. For any pre-treatment operation the substrate may also be maintained at a temperature greater than or about 400° C., greater than or about 500° C., greater than or about 600° C., greater than or about 700° C., greater than or about 800° C., or greater. As temperature for the pre-treatment decreases below or about 500° C., the effectiveness may be reduced. Similarly, as temperatures are increased above or about 700° C., nucleation may not be improved, and excess precursor may be incorporated on the surface, which may degrade the mobility of the device. Consequently, in some embodiments the temperature may be maintained between about 500° C. and about 700° C. during the pre-treatment.
(Specification: p. 13, ¶ 40; emphasis added)
Thus, the Instant Application shows that any temperature above 300 ℃, particularly the temperature range of 300 ℃ to 450 ℃ disclosed in Sato will result in the same “activation of the precursor”. As such, the evidence suggests that there would be no unexpected result for the claimed temperature range of feature [4c] of claim 1.
With regard to feature [6] of claim 1,
[6] post-treating the high-k dielectric material with nitrogen gas (N2) to insert between about 10 at.% and about 20 at.% nitrogen in the high-k dielectric material.
Sato does not teach performing nitrogen treatment of the high-k dielectric, e.g. HfO2.
Chua further teaches that the high-k dielectric, e.g. HfO2 or hafnium silicate (HfSiOx), is treated with ammonia (NH3) or a mixture of NH3 and N2 to insert nitrogen into the high-k dielectric in order to reduce leakage current (Chua: step 109 in Fig. 1; ¶ 38 and ¶¶ 33-34 giving the thermal nitridation conditions).
Senzaki, like Sato and Chua, teaches an ALD method of making a high-k gate dielectric of HfO2 or HfSiOx (Senzaki: ¶¶ 15-16). Also like Chua, Senzaki teaches nitridizing the high-k dielectric reduces leakage current of, e.g., HfO2 (Senzaki: ¶ 33, Table 2). Still further like Chua, Senzaki teaches that nitrogen is inserted by thermal nitridation of the high-k dielectric using ammonia (Senzaki: ¶¶ 47-50; Chua: ¶ 33 (supra)).
Senzaki further teaches (1) 18 atomic % nitrogen insertion using NH3 at a temperature of 800 ℃ (Senzaki: Table 5 in ¶ 49), and (2) 3.5 atomic % nitrogen insertion using N2 gas, alone—as required by feature [6] of claim 1—at 450 ℃ (Senzaki: Table 4 in ¶ 45).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to nitridize the high-k HfO2 gate dielectric of Sato in order to reduce the leakage current as taught by each of Chua and Senzaki (supra).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to nitridize the high-k HfO2 dielectric of Sato using N2 gas, alone, because Senzaki teaches that N2 gas, alone, can be used to incorporate nitrogen into HfO2 and HfSiOx dielectric materials (supra).
Finally, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to insert a total of, e.g., 18 atom%, nitrogen into the high-k HfO2 dielectric of Sato because Senzaki teaches that 18 atom% can be inserted into the high-k dielectric for the purpose of, at least, reducing the leakage current. As such, Chua and Senzaki may be seen as improvements to Sato in these aspects. (See MPEP 2143.)
While it is noted that Senzaki only shows incorporation of 3.5 atom% nitrogen into the high-k dielectric using nitrogen alone (Senzaki: Table 4 in ¶ 45), Senzaki still teaches that amounts of 18 atom% incorporated are also desired. Thus, to the extent that 18 atom % nitrogen incorporation may not be attainable using N2 gas alone—a point that the Instant Application also fails to show is possible (supra)—then this would be a difference in the claimed range of nitrogen incorporation of 10 atom% to 20 atom%. However, the claimed range of 10 atom% to 20 atom% is prima facie obvious held to be prima facie obvious in the absence of unexpected results. See In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). (See MPEP 2144.05(III)(A); emphasis added.) See also In re Huang, 40 USPQ2d 1685, 1688(Fed. Cir. 1996)(claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). (See MPEP 2144.05(I); emphasis added.)
In this case, the evidence of record in the Instant Application teaches away from the existence of unexpected results for incorporating 10 atom% to 20 atom% nitrogen, using N2 gas alone, relative to the 3.5 atom% inserted using N2 gas alone, in Senzaki. In this regard, the Instant Application states,
[0048] Nitrogen incorporation may be controlled to limit the incorporation in the film, in order to maintain the structural and electrical properties. In some embodiments, a post-treatment nitridation may incorporate less than or about 20 atomic % nitrogen at a surface region of the high-k film, and may incorporate less than or about 15 atomic % nitrogen, less than or about 10 atomic % nitrogen, less than or about 8 atomic % nitrogen, less than or about 6 atomic % nitrogen, less than or about 4 atomic % nitrogen, less than or about 2 atomic % nitrogen, or less. In some embodiments, an incorporation between about 3 atomic % and about 7 atomic % may maintain a higher k-value than higher nitrogen incorporation, and may better stabilize the film than lower nitrogen incorporation. By surface region may be meant an exposed surface of the material, although the nitrogen incorporation may extend to any distance within the film, and may be consistent, or form a reducing gradient through the material.
(Instant Specification: ¶ 45; emphasis added)
Thus, even the Instant Application appears to indicate that 3 atom% to 7 atom% nitrogen incorporation into the high-k dielectric is preferred over the currently-claimed 10 atom% to 20 atom%.
This is all of the features of claim 1.
Claim 2 reads,
2. (Original) The method of forming a semiconductor substrate of claim 1, wherein the removing includes an in-situ dry chemical process.
The examples described in paragraph [0025], “Step 1” of Sato use a wet chemical cleaning in dilute HF and SC-1, which inherently removes the native oxide as evidenced by Takafuji (Takafuji: ¶ 44, supra). Sato, however, teaches that the pre-cleaning processes, e.g. SC1 can be performed using vapors in a chamber of a cluster tool, i.e. an “in-situ dry chemical process”, in order to prevent “air breaks” that expose the substrate to contaminants (¶¶ 20-23).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to perform the native oxide removal using vapors of HF and SC1 in the chamber of the cluster tool shown in Fig. 2, in order to prevent air breaks and the associated contamination, as taught in Sato (id.).
Claim 3 reads,
3. (Original) The method of forming a semiconductor structure of claim 2,
[1] wherein the removing is performed in a first processing chamber, and
[2] wherein the method further comprises transferring the substrate from the first processing chamber to a second processing chamber prior to forming the high-k dielectric material.
As explained above, Sato states that the removing of the native oxide, i.e. the “pre-cleaning” can be performed in the cluster tool shown in Fig. 2 (id.). Sato further teaches that chambers 34 can be configured as an ALD chamber while at least one of chambers 36 and 38 can be configured as a “pre-clean” chamber, which are separate chambers from chamber 34 (¶ 22). In addition, Sato teaches that and chambers 62, 64, 66, and 68 can be configured in a similar manner to chambers 32, 34, 36, and 38 (¶ 23).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to perform the pre-cleaning to remove native oxide from the Si substrate in one of chamber 36 or 38 and to perform the ADL in chamber 34 (1) because Sato states that the chambers can be configured for these processes, and (2) in order to prevent cross-contamination of the chemicals used in each of the distinct processes.
This is all of the features of claim 3.
With regard to claim 4, Sato further discloses,
4. (Original) The method of forming a semiconductor structure of claim 1, wherein the method is performed in one or more processing chambers without exposing the surface of the substrate to atmosphere [¶¶ 20-23; Fig. 2 (supra)].
Claim 7 reads,
7. (Previously Presented) The method of forming a semiconductor structure of claim 1, further comprising, subsequent forming the high-k dielectric material, performing a thermal anneal.
Sato does not teach that the high-k dielectric layer, e.g. HfO2, that is deposited using ALD is subsequently thermally annealed.
Chua further teaches that the ALD deposited high-k dielectric, e.g. HfO2 (¶ 37), can be annealed first in ammonia at, e.g. 800 °C, in order to reduce leakage current (step 109 in Fig. 1: ¶ 38 referring to ¶¶ 33-34 for thermal nitridation conditions) and then in oxygen at, e.g. 1000 °C, also to reduce leakage current (step 112 in Fig. 1; ¶ 43).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to perform the additional high temperature anneal in oxygen at 1000 °C on the high-k gate dielectric in Sato/Chua/Senzaki, in order to further improve the leakage current, as taught in Chua.
With regard to claims 11 and 12, Sato further discloses,
11. (Original) The method of forming a semiconductor structure of claim 1, wherein the substrate comprises a silicon-containing material [¶ 25].
12. (Original) The method of forming a semiconductor structure of claim 1, wherein the high-k dielectric material comprises at least one element selected from the group consisting of hafnium, zirconium, silicon, lanthanum, aluminum, titanium, and strontium [¶ 25: “step 4”].
With regard to claim 32, Sato further discloses,
32. (Previously Presented) The method of forming a semiconductor structure of claim 1, wherein the oxygen-containing precursor comprises a hydroxyl group [-OH].
See discussion under feature [4c] of claim 1.
Claim 13 reads,
13. (Currently Amended) A method of forming a semiconductor structure, the method comprising:
[1] removing a native oxide from a surface of a substrate contained in a first semiconductor processing chamber;
[2] transferring the substrate to a second semiconductor processing chamber without breaking vacuum conditions; Page 3 of 8Appl. No. 17/062,286
[3] delivering nitrous oxide to the substrate and thermally annealing the surface to form an oxide-containing interface layer in the second semiconductor processing chamber;
[4a] pre-treating the oxide-containing interface by contacting the substrate with an oxygen-containing precursor
[4b] while substantially maintaining a thickness of the oxide-containing interface layer and
[4c] while substantially maintaining the substrate at a temperature between 500 ℃ and 575 ℃;
[5] transferring the substrate to a third semiconductor processing chamber without breaking vacuum conditions;
[6] forming a high-k dielectric material overlying the pre-treated oxide-containing interface in the third semiconductor processing chamber housing the pre-treated substrate;
[7] transferring the substrate to a fourth semiconductor processing chamber without breaking vacuum conditions; and
[8] post-treating the high-k dielectric material with a nitrogen gas (N2) treatment to insert between about 10 at.% and about 20 at.% nitrogen in the high-k dielectric material.
With regard to claim 13, Sato discloses,
13. (Currently Amended) A method of forming a semiconductor structure, the method comprising:
[1] removing a native oxide from a surface of a substrate [i.e. par 25: “Bare-Si wafers” and “Step 1”] contained in a first semiconductor processing chamber [¶¶ 20-24];
[2] transferring the substrate to a second semiconductor processing chamber without breaking vacuum conditions [¶¶ 20-25]; Page 3 of 8Appl. No. 17/062,286
[3] delivering … [oxygen] … to the substrate and thermally annealing the surface to form an oxide-containing interface layer in the second semiconductor processing chamber [i.e. SiO2; Fig. 1; ¶¶ 13, 17, 20-24 and ¶ 25: “Step 2”];
[4a] pre-treating the oxide-containing interface by contacting the substrate with an oxygen-containing precursor [i.e. H2O or NH3/H2O; abstract; ¶¶ 13, 16-19 and ¶ 25, “Step 2”]
[4b] while substantially maintaining a thickness of the oxide-containing interface layer [¶ 27: “a dense thermal oxide surface such as silicon oxide is surface treated to functionalize the surface [i.e. with –OH groups] without substantially changing the thickness of the substrate”]
[4c] while substantially maintaining the substrate at a temperature between 500 ℃ and 575 ℃ [as explained under claim 1, above];
[5] transferring the substrate to a third semiconductor processing chamber without breaking vacuum conditions [¶¶ 5, 8, 20-24 and especially ¶¶ 25-26];
[6] forming a high-k dielectric material [e.g. HfO2; ¶ 25] overlying the pre-treated oxide-containing interface in the third semiconductor processing chamber housing the pre-treated substrate [¶¶ 13, 14, 20-24, 26 and ¶ 25, “Step 4”];
[7] transferring the substrate to a fourth semiconductor processing chamber without breaking vacuum conditions [¶¶ 5, 8, 20-24 and especially ¶¶ 25-26]; and
[8] … [not taught] …
With regard to feature [1] of claim 13, as explained above under the rejection of claim 1, that the cleaning process of “step 1” in Sato inherently removes native oxide is evidenced by Takafuji (supra).
With regard to feature [2] of claim 13, the use of N2O instead of O2 as the oxidant to form the interfacial oxide in Step 2” of Sato is obvious in view of Chua for the reasons explained above under the rejection of claim 1.
With regard to feature [4] of claim 13, the claimed temperature range of 500 ℃ to 575 ℃ is obvious for the same reasons as explained above under the rejection of claim 1.
With regard to feature [8] of claim 13,
[8] post-treating the high-k dielectric material with a nitrogen gas (N2) treatment to insert between about 10 at.% and about 20 at.% nitrogen in the high-k dielectric material.
This feature is obvious in view of Chua and Senzaki for the reasons explained under the rejection of feature [6] of claim 1 (supra).
With regard to the claimed first through fourth processing chambers and the transferring of the substrate from one process chamber to another without a vacuum break, as required in claim 13, Sato states that “air breaks”, i.e. vacuum breaks, are avoided in order to prevent contamination of the silicon substrate during thermal oxidation of the Si wafers to form the interfacial oxide, activation of said interfacial oxide to form surface –OH groups, and ALD of the high-k dielectric, and that the air breaks are avoided by using a cluster tool, such as shown in Fig. 2 (Sato: ¶¶ 5, 8, 20-24 and especially ¶¶ 25-26). The cluster tool includes different chambers for each of the different kinds of process steps:
[0022] FIG. 2 shows an example of a cluster tool or multi-chamber processing system 10 that can be used in conjunction with an aspect of the invention. The processing system 10 can include one or more load lock chambers 12, 14 for transferring substrates into and out of the system 10. Typically, since the system 10 is under vacuum, and the load lock chambers 12, 14 may "pump down" substrates introduced into the system 10. A first robot 20 may transfer the substrates between the load lock chambers 12, 14, and a first set of one or more substrate processing chambers 32, 34, 36, 38. Each processing chamber 32, 34, 36, 38, may be configured to perform a number of substrate processing operations. For example, processing chamber 32 can be an etch processor designed to practice an etch process, and processing chamber 34 can be a deposition reaction chamber for performing ALD or CVD. Processing chambers 36, 38 may also be configured to further provide, for example, cyclical layer deposition (CLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etch, pre-clean, chemical clean, thermal treatment such as RTP, plasma nitridation, degas, orientation, EUV lithography (e.g. a stepper chamber) and other substrate processes.
(Sato: ¶ 22; emphasis added)
Paragraph [0023] discusses the robots 20, 50 and additional process chambers 62, 64, 66, 68.
Sato further states,
[0025] FIG. 3 shows the differences in growth rates as a function of different surface treatment conditions. Sample HfO2 films were grown using an ALD techniques on silicon oxide films. For sample preparation, Bare-Si wafers were sequentially processed through Steps 1 through Step 4, as shown in FIG. 3. Steps 2 to Step 4 were processed without air break or exposure to air. After samples were processed, HfO2 films thickness were quantified by X-ray Photoelectron Spectroscopy system. Process condition details are as follows and as summarized in Table 1: …
(Sato: ¶ 25; emphasis added)
With regard to “step 1” in paragraph [0025], which is a cleaning process used to remove native oxide, as explained above, Sato states that typically wet chemical cleaning processes, can be performed using “gas phase reactions” and thereby be performed in a process chamber of a cluster tool:
[0020] According to embodiments of the invention, a surface that simulates an [sic] surface treated by an ex situ process such as SC1 can be generated in situ using gas phase reactions. This eliminates the need for an air break between the formation of the base oxide and the gate oxide which should eliminate excess carbon. Excess carbon can produce a large hysteresis capacitance value (CV) in high K dielectric films.
[0021] As used herein, “in situ” refers to a process that is prepared in a process chamber environment, and not outside a process chamber, where contamination of the substrate surface can occur. In one embodiment, the processes described herein can be performed in a single or stand alone process chamber. In other embodiments, the processes described herein can be performed in a cluster tool under load locked conditions in which there is no air break to move the substrate to subsequent process chambers.
(Sato: ¶¶ 20, 21; emphasis added)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to perform each of the process steps 1 through 4 in paragraph [0025] (i.e. step 1, which is any of a “pre-clean” or “chemical clean” or “etching” (¶ 22); step 2, which is a “thermal treatment such as RTP” (¶ 22); step 3, which is a thermal treatment; and step 4, which is an ALD process), as well as the nitridation step of Senzaki used in Sato (supra), in separate process chambers of the cluster tool without air break (i.e. vacuum break) (1) in order to avoid cross-contamination of the process chambers by the chemicals used for each process step, as would be apparent to one having ordinary skill in the art, and (2) in order to prevent air contamination of the Si wafers, as expressed in Sato (¶¶ 5, 8, 20-25).
This is all of the features of claim 13.
Claim 14 reads,
14. (Original) The method of forming a semiconductor structure of claim 13, wherein the removing includes an in-situ dry chemical process.
As explained under claim 13, above, Sato states that typically wet chemical cleaning processes, can be performed using “gas phase reactions” and thereby be performed in a process chamber of a cluster tool (Sato: ¶¶ 20-21).
As such, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use an in-situ dry chemical process to remove the native oxide because Sato suggests this (id.).
Claim 15 reads,
15. (Original) The method of forming a semiconductor structure of claim 13, wherein the fourth semiconductor processing chamber is the second semiconductor processing chamber.
As explained above, the second processing chamber for thermal oxidation to form the interfacial oxide and the fourth processing chamber used to perform the thermal nitridation of Senzaki to the ALD deposited high-k dielectric layer of Sato are both thermal processes.
As such, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to perform each of the processes of forming the interfacial oxide and the Senzaki process of nitridizing the high-k dielectric layer of Sato in the same processing chamber in order to reduce the number of reactors/chambers needed in the cluster tool, thereby reducing the cost of the cluster tool, as well as reducing the footprint required for said cluster tool.
Moreover, inasmuch as the instant claims indicate that said two processes can be formed in separate chambers or the same chamber, there appears to be nothing critical to the use of separate chambers or the same chamber for the two processes.
This is all of the features of claim 15.
With regard to claim 17, Sato further discloses,
17. (Original) The method of forming a semiconductor structure of claim 13, wherein the method is performed in one or more processing chambers without exposing the surface of the substrate to atmosphere.
See discussion under claims 13.
With regard to claim 18, Sato modified according to Chua and Senzaki, as explained above under claims 1 and 13, further teaches,
18. (Previously Presented) The method of forming a semiconductor structure of claim 13, wherein the post-treating comprises exposing the substrate and high-k dielectric material to a nitrogen-containing precursor [i.e. the thermal nitridation using N2 as taught by Senzaki (supra)].
Claim 19 reads,
19. (Original) The method of forming a semiconductor structure of claim 13, further comprising, subsequent the post-treating, annealing the high-k dielectric material.
Because Sato does not teach the thermal nitridation, Sato also does not teach the post-nitridation anneal required in claim 19.
However, Chua further teaches the post-nitridation anneal of the high-k dielectric:
19. (Original) The method of forming a semiconductor structure of claim 13, further comprising, subsequent the post-treating [i.e. step 109], annealing the high-k dielectric material 208 [step 110 and/or step 112 in Fig. 1 of Chua; ¶¶ 39, 41, 43].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, in addition to the thermal nitridation of Chua/Senzaki of the high-k dielectric of Sato, to perform the associated post-nitridation anneal of the nitridized high-k dielectric, in order to reduce the leakage current, as taught in Chua.
This is all of the features of claim 19.
With regard to claim 20, bearing in mind the rejections under 35 USC 122(b) and (d), above, Sato further discloses,
20. (Original) The method of forming a semiconductor structure of claim 13, wherein the nitrogen-containing precursor for the pre-treating [“step 3” in Sato] comprises ammonia [i.e. NH3/H2O (Sato: ¶ 25)].
Claim 21 reads,
21. (Currently Amended) A method of forming a semiconductor structure, the method comprising:
[1] removing a native oxide from a surface of a substrate comprising a silicon- containing material contained in a semiconductor processing chamber;
[2] delivering nitrous oxide to the substrate and thermally annealing the surface to form an oxide-containing interface;
[3] pre-treating the substrate comprising the silicon-containing material having the oxide-containing interface thereon by contacting the substrate with an oxygen-containing precursor while maintaining the substrate at a first temperature between 500º C and about 575° C;
[4] forming a high-k dielectric material overlying the pre-treated substrate while maintaining the pre-treated substrate at a second temperature less than the first temperature; and
[5] post-treating the high-k dielectric material with nitrogen gas (N2) to insert between about 10 at.% and about 20 at.% nitrogen in the high-k dielectric material.
With regard to claim 21, Sato discloses,
21. (Currently Amended) A method of forming a semiconductor structure, the method comprising:
[1] removing a native oxide from a surface of a substrate comprising a silicon- containing material contained in a semiconductor processing chamber [¶¶ 20-23, 25; see further explanation below];
[2] delivering …[oxygen]… to the substrate and thermally annealing the surface to form an oxide-containing interface [i.e. SiO2; Fig. 1 ¶¶ 13, 17 and ¶ 25: “Step 2”];
[3] pre-treating the substrate comprising the silicon-containing material having the oxide-containing interface thereon by contacting the substrate with an oxygen-containing precursor [H2O for Samples C through I in Table 1 or NH3/H2O for Samples F through I in Table 1; ¶ 25] while maintaining the substrate at a first temperature … [“less than about 450° C” (¶ 15)];
[4] forming a high-k dielectric material [e.g. HfO2; ¶ 25] overlying the pre-treated substrate while maintaining the pre-treated substrate at a second temperature [e.g. 275 °C] less than the first temperature [¶¶ 13, 14 and ¶ 25, “Step 4”; see further explanation below]; and
[5] … [not taught] …
With regard to feature [1] of claim 21, the dilute HF cleaning step in Sato inherently removes the native oxide, as evidenced by Takafuji at paragraph [0044], which states, “A single crystalline silicon wafer (single crystalline silicon substrate) 40 is cleaned by a general cleaning method (e.g., by which a natural oxide film is removed with dilute hydrofluoric acid, and a particle, organic matter, and the like are removed by SC1 and SC2 cleaning agents).” As such, the burden of proof is shifted to Applicant to prove the contrary. (See MPEP 2112(I)-(V).)
Further with regard to feature [1], as explained above under the rejection of claim 2, the examples described in paragraph [0025], “Step 1” of Sato use a wet chemical cleaning in dilute HF and SC-1, which inherently removes the native oxide as evidenced by Takafuji (Takafuji: ¶ 44, supra). Sato, however, teaches that the pre-cleaning processes, e.g. SC1 can be performed using vapors in a chamber of a cluster tool, i.e. an “in-situ dry chemical process”, in order to prevent “air breaks” that expose the substrate to contaminants (¶¶ 20-23).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to perform the native oxide removal using vapors of HF and SC1 in the chamber of the cluster tool shown in Fig. 2, in order to prevent air breaks and the associated contamination, as taught in Sato (id.).
With regard to feature [2] of claim 21, Sato does not teach that the oxidant used to form the interfacial layer is nitrous oxide (N2O), using instead, oxygen (¶ 25: “Step 2”).
Chua, like Sato, teaches a method of making a high-k gate dielectric that includes first removing a native oxide 204 from a silicon substrate 200, then thermally oxidizing the silicon substrate to form a SiO2 interface layer 206 and then depositing a high-k dielectric layer 208 by ALD on the interface layer 206 (Chua: Figs. 1, 2A-2E; ¶¶ 22-44). Also like Sato, Chua teaches that the oxidant used for the thermal oxidation of the Si substrate 200 to form the SiO2 interface layer is oxygen (¶¶ 24-25). Chua teaches that in another embodiment nitrous oxide (N2O) can be used (Chua: ¶ 26).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use nitrous oxide (N2O) instead of oxygen as the oxidant in the process of Sato because Chua teaches that nitrous oxide (N2O) is a suitable oxidant for the same purpose of forming an interface layer upon which is subsequently deposited a high-k dielectric for making a gate dielectric (supra). As such the selection of nitrous oxide (N2O) in place of oxygen is obvious material choice. (See MPEP 2144.07.)
With regard to feature [3] of claim 21, this feature is obvious for the reasons discussed under feature [4c] of claim 1, which is incorporated here in its entirety.
With regard to feature [4], Sato discloses that the ALD deposition of HfO2 in Examples A-I in Table 1 (¶ 25) is performed at 275 °C, which is a temperature lower than a range, e.g. 449 °C to 400 °C, of exposure to the water or water/ammonia to form the reactive hydroxyl ligands.
This is all of the features of claim 21 taught in Sato.
With regard to feature [5] of claim 21,
[5] post-treating the high-k dielectric material with nitrogen gas (N2) to insert between about 10 at.% and about 20 at.% nitrogen in the high-k dielectric material.
This feature is obvious for the reasons discussed under feature [6] of claim 1, which is incorporated here.
This is all of the features of claim 21.
B. Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Sato in view of Chua, Senzaki, and as evidenced by Takafuji, as applied to claim 1 above, and further in view of US 5,849,643 (“Gilmer”).
Claim 5 reads,
5. (Original) The method of forming a semiconductor structure of claim 1, wherein the native oxide is removed from the surface of the substrate to a depth of up to or about 20 Å.
The prior art of Sato in view of Chua, Senzaki, and as evidenced by Takafuji, as explained above, teaches each of the features of claim 1.
Sato, as evidenced by Takafuji, and Chua do not indicate the thickness of the native oxide that is removed.
Gilmer teaches that silicon forms a native oxide of typically 10 Å when exposed to an oxygen bearing ambient (col. 1, lines 59-65).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to remove the 10 Å of native oxide because Sato and Chua remove the native oxide during the cleaning.
This is all of the features of claim 5.
C. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Sato in view of Chua, Senzaki, and as evidenced by Takafuji, as applied to claim 1 above, and further in view of US 2003/0049942 (“Haukka”).
Claim 6 reads,
6. (Original) The method of forming a semiconductor structure of claim 1, wherein delivering nitrous oxide to the substrate and thermally annealing the surface forms an oxide-containing interface of a thickness of up to about 5 Å.
The prior art of Sato in view of Chua, Senzaki, and as evidenced by Takafuji, as explained above, teaches each of the features of claim 1.
Sato forms the interface oxide layer in Examples B-I to 10 Å (Sato: ¶ 25: “Step 2”). Similarly, Chua teaches that the interface oxide is formed to a thickness of, preferably 2 to 10 Å, which overlaps the claimed range.
Haukka, like each of Sato and Chua, teaches a method of making a high-k gate dielectric that includes first removing a native oxide from a silicon substrate (Haukka: ¶¶ 26-27; step 10 in Fig. 1), then thermally oxidizing the silicon substrate to form a SiO2 interface layer (Haukka: ¶ 37 in Fig. 1) and then depositing a high-k dielectric layer by ALD on the interface layer (Haukka: ¶¶ 57-62; part of step 50 in Fig. 1). Also like each of Sato and Chua, Haukka teaches that the oxidant used for the thermal oxidation of the Si substrate to form the SiO2 interface layer can be oxygen and can be grown to, “more preferably”, a thickness of less than 10 Å (Haukka: ¶¶ 29, 34). Also like Chua, Haukka further teaches that nitrous oxide (N2O) can be used instead of oxygen (Haukka: ¶ 37). Haukka further teaches that the thickness of the interface layer can be most preferably grown to a thickness of 5 Å (Haukka: ¶ 29) and provides examples of 5 Å for each of the ozone (O3) and nitrous oxide (N2O) as oxidants (Haukka: ¶¶ 34, 37).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make the thickness of the SiO2 interface layer in Sato to be 5 Å because Haukka teaches that this thickness is most preferable for an interface layer on which a high-k gate dielectric layer is formed.
D. Claim 16 is under 35 U.S.C. as being unpatentable over Sato in view of Chua, Senzaki, and as evidenced by Takafuji, as applied to claim 13, above, and further in view of US 2008/0057659 (“Forbes”).
Claim 16 reads,
16. (Original) The method of forming a semiconductor structure of claim 13, further comprising performing a thermal anneal prior to removing the native oxide.
Sato in view of Chua, Senzaki, and as evidenced by Takafuji teaches each of the features of claim 13.
Sato does not teaches performing a thermal anneal prior to removing the native oxide.
Forbes, like Sato, further teaches that a native oxide is removed prior to forming the high k gate dielectric (Forbes: ¶¶ 55-56). Forbes further teaches that other layers and regions, such as source and drain regions may be formed prior to the cleaning step that removes the native oxide (Forbes: ¶ 55). Forbes further teaches that the formation of the source and drain regions is performed by “conventional ion implantation and subsequent annealing” (Forbes: ¶ 89). As such, Forbes teaches “performing a thermal anneal prior to removing the native oxide”.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the source and drain regions in Sato, and thereby perform a thermal annealing process, prior to removing the native oxide, because Forbes teaches that the high-k gate dielectric, including the native oxide removal, can be performed either before or after the formation of the source and drain regions (Forbes: ¶ 55), thereby indicating that the sequence is a matter of design choice. (See MPEP 2143.)
This is all of the features of claim 16.
E. Claim 31 is rejected under 35 U.S.C. 103 as being unpatentable over Sato in view of Chua, Senzaki, and as evidenced by Takafuji, as applied to claim 1 above, and further in view of US. 2008/0258219 (“Thean”).
Claim 31 reads,
31. (Previously Presented) The method of forming a semiconductor structure of claim 1, wherein the high-k dielectric material is characterized by a k-value greater than or about 20.
The prior art of Sato in view of Chua, Senzaki, and as evidenced by Takafuji, as explained above, teaches each of the features of claim 1.
Sato does not give a dielectric for the HfO2 produced by the ALD method using HfCl4 and H2O.
Thean, like Sato, teaches that it is known to produce a HfO2 layer by ALD using HfCl4 and H2O that has a dielectric constant of about 30 (Thean: ¶ 36).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make the dielectric constant of the HfO2 of Sato/Chua to have a dielectric greater than 20 because Thean teaches that it is known to have a dielectric constant of about 30.
IV. Response to Arguments
Applicant’s arguments filed 10/17/2025 have been fully considered but they are not persuasive.
Applicant argues,
As presented, independent claims 1, 13, and 21 specify the post-treating is
performed with nitrogen gas (N2). Chua heavily focuses on treating high-k dielectric material with ammonia. See Chua, paras. [0033], [0034], and [0038]. Further, Senzaki does provide data when treatment is performed using N2. See Senzaki, Table 4. Table 4 of Senzaki is only able to incorporate a maximum of 3.5 at.% nitrogen when using N2. Conversely, the present Application explains a nitrogen-containing precursor used during the post-treatment may be any nitrogen-containing precursor noted elsewhere, but specifically identifies nitrogen gas (or N2 as one skilled in the art would appreciate) as being a candidate for post-treatment. See Publication, para. [0047]. The other cited references do not cure the deficiencies of Chua and Senzaki. As the cited references do not teach or suggest post-treating performed with nitrogen gas (N2) to insert between about 10 at.% and about 20 at.% nitrogen in the high-k dielectric material, amended claims 1, 13, and 21 are believed to be allowable over the cited references.
(Remarks filed 10/17/2025: paragraph bridging pp. 8-9l emphasis added)
Bearing in mind the rejection of new claims 33-35 for lack of enablement, Examiner notes that Applicant acknowledges that “Senzaki is only able to incorporate a maximum of 3.5 at.% nitrogen when using N2” (id.), but fails to explain how the Instant Inventor was able to force 10 at% to 20 at% into the high-k dielectric. And Examiner respectfully submits that the Instant Application does not “explain” how 10 at% to 20 at% N can be incorporated into any unidentified high-k dielectric using only N2 gas at a temperature less than 300 ℃ if at all. As explained above, the Instant Application merely provides a series of lists without any empirical data or even one single example. That is not “explanation”, and Applicant cannot merely decree that 10 at% to 20 at% can be incorporated into any high-k dielectric using only N2 gas, particularly while noting that others fails using the same conditions. Examiner respectfully maintains that Applicant’s alleged success in incorporating 10 at% to 20 at% using only the very stable N2 gas, while the prior art failed, achieving only 3.5 at% at 450 ℃, cannot be so novel and nonobvious as to warrant patentability, while simultaneously omitting the details as to how the success was achieved, or any empirical evidence showing that is was, in fact, achieved where others failed. In other words, things that are well known in the art may be omitted from the specification, but “well-known” is antithetical to “novelty and nonobviousness”.
Examiner respectfully maintains that each of claims 1, 13, and 21 is prima facie obvious for the reasons explained in the rejection above in the absence of evidence that Applicant was actually able to achieve the claimed 10 at% to 20 at% into any high-k dielectric using only N2 gas. Again, Examiner will consider any factual objective evidence that Applicant may provide to show that post-treating a high-k dielectric material with N2 gas, alone, particularly performed at a temperature below 300° C” resulting in “about 10 at.% to about 10 at.% nitrogen” insertion into any high-k dielectric.
Based on the foregoing, Applicant’s arguments are not found persuasive.
Conclusion
Applicant’s amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK KIELIN whose telephone number is (571)272-1693. The examiner can normally be reached Mon-Fri: 10:00 AM-7:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on 571-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
Signed,
/ERIK KIELIN/
Primary Examiner, Art Unit 2814