Attorney’s Docket Number: 44017349US02
Filing Date: 11/4/2020
Claimed Priority Date: 11/5/2019 (US 62/931,211)
Inventors: Yang et al.
Examiner: Marcos D. Pizarro
DETAILED ACTION
This Office action responds to the amendment filed on 7/11/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA (or as subject to pre-AIA ) is incorrect, any correction of the statutory basis for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
The amendment filed on 7/11/2025 in reply to the Office action in paper no. 13 has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1, 4, 6-8 and 13-24.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 4, 6, 7 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Park (US 2017/0110316) in view of Jong (US 2020/0013897) and Nakamura (US 2014/0048885).
Regarding claim 1, Park (see, e.g., fig. 7C) shows most aspects of the instant invention including a metal gate stack 420 comprising:
A high-k metal oxide layer 414
A high-k capping layer 426A on the oxide layer
A PMOS work function layer 426B on the capping layer
Park also teaches several materials from which the capping and the work function layers can be made of, including TiSiN for the capping layer and MoN for the work function layer (see, e.g., par.0116/l.4 and par.0118/l.5). Jong (see, e.g., par.0114-0115), in a similar gate stack to Park, teaches that TiSiN and MoN are known work function materials. Moreover, Jong explicitly describes that the work function of a transistor may be adjusted by selecting different materials for the work function layer (see, e.g., Jong: pars. 0117-0118). Jong is evidence showing that one of ordinary skill in the art would have selected TiSiN and MoN, as capping and work function layers not only from a material standpoint but also for achieving a specific adjustment in the transistor’s work function.
Accordingly, in view of Jong’s teachings, it would have been obvious at the time of filing the invention to select TiSiN and MoN from among the materials in Park to fine tune the work function of the transistor.
Park is also evidence showing that one of ordinary skill in the art would have appreciated that having a TiSiN capping layer and a MoN function layer would result in no change in the performance of a gate stack. That is, the gate stacks of Park would yield the predictable result of electrically coupling the gate electrode to the channel of the transistor if the materials for the capping and work function layers are selected from among the listed materials. The specific claimed materials for the capping and work function layers, i.e., TiSiN and MoN, absent any criticality, are only considered to be the “optimum” materials from the list of materials disclosed by Park that a person having ordinary skill in the art would have been able to determine using routine experimentation based, among other things, on the desired work function for the transistor, manufacturing costs, etc. (see Boesch, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e., results which are different in kind and not in degree from the results of the prior art, will be obtained, as long as a gate stack comprising capping and work function layers is used, as already suggested by Park.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have a TiSiN capping layer and a MoN function layer because these were specifically recognized in the semiconductor art for their use as capping and function layers of a gate stack, as taught by Park and Jong, and because selecting a material for its conventional use would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Park also fails to show the capping and work function layers comprising the recited thicknesses of these layers. However, differences in thickness will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such thicknesses are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Jong (see, e.g., pars 0068-0069), for example, teaches that the effective work function of a gate stack would depend on the thicknesses of these layers. Accordingly, the specific claimed thicknesses, i.e., 5-25Å and 5-50Å, are only considered to be the “optimum” thicknesses that a person having ordinary skill in the art would have been able to determine using routine experimentation based, among other things, on the desired effective work function, manufacturing costs, etc. (see Boesch, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e., results which are different in kind and not in degree from the results of the prior art, will be obtained as long as a TiSiN capping layer and a MoN work function layer are used, as already suggested by Park/Jong.
Since the applicant has not established the criticality (see next paragraph below) of the claimed thicknesses, it would have been obvious to one of ordinary skill in the art to use these values in the device of Park/Jong.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed thicknesses or any unexpected results arising therefrom. Where patentability is said to be based upon particular variable or dimension recited in a claim, the applicant must show that the chosen variables and dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding claims 1, 4, 6 and 7, Park teaches the metal gate stack comprises a high-k gate dielectric, a capping layer, and a work function layer. Park explicitly discloses that the capping layer may be formed of TiSiN (see, e.g., par. 0116/l.4), and that the PMOS work function layer may be formed of MoN (see, e.g., par. 0118/l.5). Accordingly, Park further teaches a gate stack with an provide improved flat-band voltage (Vfb) and a reduce EOT relative to conventional gate stacks, including those using TiN materials.
While Park does not expressly quantify the magnitude of the Vfb improvement, Nakamura teaches that the Vfb of a PMOS transistor is a result-effective variable that may be predictably adjusted by modifying the thickness of the capping layer. Nakamura discloses that variations in capping layer thickness can produce Vfb shifts of several hundred millivolts, e.g., up to approximately 500 mV, demonstrating that substantial Vfb adjustments are achievable through routine gate stack optimization. See, e.g., Nakamura: fig. 3B and par. 0040.
Although Nakamura’s experimental data are illustrated using a TiN capping layer, Nakamura also teaches that TiSiN is an alternative capping layer material (see, e.g., par. 0031/ll.11), and the mechanism for Vfb adjustment described by Nakamura arises from gate stack electrostatics rather than from a material-specific anomaly. Accordingly, one of ordinary skill in the art would have reasonably expected that similar thickness-dependent Vfb adjustments would occur when TiSiN is used as the capping layer.
Like Nakamura, Jong teaches that the work function of the gate stack can be adjusted by adjusting the thickness of the capping and work function layers (see, e.g., pars. 0068-0069). Jong further teaches that the work function of a PMOS transistor may be tuned by selecting appropriate work function materials (see, e.g., pars. 0116-0118), reinforcing that Vfb optimization through material selection and layer thickness adjustment was well known in the art.
Therefore, it would have been obvious to one of ordinary skill in the art to implement the TiSiN/MoN gate stack taught by Park and to adjust the capping layer thickness, as taught by Nakamura, to obtain a desired Vfb improvement, including an improvement of greater than +275 mV relative to a stack comprising a TiN work function layer. Achieving such a Vfb value represents no more than the predictable result of routine optimization of known result-effective variables.
Applicant has not provided evidence demonstrating that the claimed Vfb improvement is unexpected in kind or that the claimed value reflects criticality beyond what is taught or suggested by the prior art. Accordingly, the Vfb limitation does not render the claimed subject matter non-obvious.
Since the applicants have not established the criticality (see paragraph 14 above) of the stated Vfbs, and similar Vfbs have been used in gate stacks before, as taught by Nakamura, it would have been obvious to one of ordinary skill in the art to use these values in the device of Park.
Regarding claim 24, Park (see, e.g., par.0114/ll.6-7) shows that the oxide layer comprises HfO2.
Claims 21-23, 8 and 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Park/Jong/Nakamura in view of Clark (US 2013/0052814).
Regarding claim 8, see the comments above in paragraphs 6-21 with respect to claim 1, which are considered to be repeated here.
Regarding claims 8, 13, 14 and 21-23, Park/Jong show most aspects of the instant invention including a gate stack with a reduced EOT-increase relative to a stack comprising a TiN capping layer and a work function layer comprising MoN or TiN (see, e.g., Park: par. 0116/l.4 and par. 0118/l.5). He, however, fails to specify that the EOT increase is reduced by greater than +0.3 Å, or that the EOT increases less than +0.3Å and +0.05Å. Clark (see, e.g., par.0031/ll.10-15), on the other hand, teaches that EOT reductions would enhance the scalability of a gate stack and the performance of a transistor.
The specific claimed EOTs, absent any criticality, are only considered to be the “optimum” EOTs for the gate stack of Park that a person having ordinary skill in the art would have been able to determine using routine experimentation based, among other things, on transistor performance, scalability, manufacturing costs, etc. (see Boesch, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e., results which are different in kind and not in degree from the results of the prior art, will be obtained as long as a gate stack comprising an MoN work function layer on a TiSiN capping layer is used, as already suggested by Park/Jong.
Accordingly, since the applicants have not established the criticality (see paragraph 14 above) of the stated EOT reductions, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to use these values in the gate stack of Park to enhance the scalability of the stack and the performance of the transistor, as taught by Clark.
Regarding claim 15, Park (see, e.g., fig. 7C) shows the gate stack further comprising:
A substrate material 402 with an oxidized surface 412
A gate electrode 428 on the work function material 426B
wherein:
The metal oxide layer 414 is on the oxidized surface 412
The gate stack has an improved Vfb relative to a gate stack comprising a work function material comprising TiN (see, e.g., par. 0116/l.4 and par.0118/l.5)
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Park//Jong/Nakamura/Clark in view of Ragnarsson (US 2015/0357244).
Regarding claim 16, Park (see, e.g., fig. 7C) shows most aspects of the instant invention including the gate electrode 428 comprising a layer of TiN. He also teaches using said TiN layer as a gap-fill layer for the gate electrode. See, e.g., Park: par.0122. Park, however, fails to teach the gate electrode additionally comprising a first layer of TiAl. Ragnarsson, in a similar gate stack to Park, teaches using a first layer of TiAl layer and a second layer of TiN layer as gap filling layers for gate electrodes in a transistor. He teaches that the TiAl layer can be seen as a further work function tuning layer whose presence will influence the work function of the gate stack. See, e.g., Ragnarsson: par.0070/ll.29-35.
Accordingly, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have the gate electrode of Park also comprising the TiAl layer of Ragnarsson to further tune the work function of the gate stack.
Response to Arguments
The applicants argue:
Park only discloses a laundry list of possible materials for the capping and work function layers. There are 133 possible combinations that the skilled artisan would have to synthesize and test to realize the benefits of the combination of TiSiN and MoN. The skilled artisan would have to embark on a fishing expedition to arrive at the claimed combination. Without the benefit of hindsight there is absolutely no reason why one skilled in the art would pick from the numerous laundry list of materials and arrive at the particular claimed stack of TiSiN and MoN. In addition, Park and Jong fail to identify some reason, suggestion, or motivation to make the claimed TiSiN/MoN gate stack. That is, nothing in Park or Jong would lead a person of ordinary skill in the art to modify the prior art laundry list to arrive at the claimed gate stack of TiSiN/MoN.
The examiner responds:
Applicant’s arguments have been considered but they are not persuasive.
Park expressly discloses a metal gate stack in which the capping layer may be selected from TiN, TaN, TiAlN, TaAlN, TiSiN, or combinations thereof (see, e.g., par.0116), and further discloses that the work function layer may be selected from Mo, Pd, Ru, Pt, TiN, WN, TaN, Ir, TaC, RuN, and MoN (see, e.g., par.0118). Thus, Park explicitly teaches both TiSiN and MoN as capping and work-function layer materials.
Contrary to Applicant’s assertion, the selection of TiSiN and MoN from among Park’s disclosed materials does not require impermissible hindsight reconstruction or a “fishing expedition.” Rather, Park presents a finite number of identified and predictable material options for each layer, all of which are taught to be functionally suitable for use in the gate stack. Selecting from among such known alternatives constitutes routine optimization, which has been held to be prima facie obvious (see In re Peterson, 315 F.3d 1325 (Fed. Cir. 2003); KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007)).
Further, Jong provides additional evidence that TiSiN and MoN are known materials used to adjust transistor work function (see, e.g., pars. 0114-0115), reinforcing that a person of ordinary skill in the art would have been motivated to select these materials to achieve a desired work function. The combination of Park and Jong therefore provides an articulated rationale for selecting TiSiN as the capping layer and MoN as the work function layer based on known material properties and design considerations.
Applicant’s argument that Park merely discloses a “laundry list” of materials is unavailing. The mere presence of multiple disclosed alternatives does not render the selection of a particular combination non-obvious absent a showing of criticality or unexpected results. Applicant has not provided evidence demonstrating that the claimed TiSiN/MoN gate stack yields results that are unexpected in kind relative to the gate stacks disclosed by Park. Any alleged reduction in EOT and improvements in Vfb represent, at most, a difference in degree arising from predictable material properties and does not overcome the prima facie case of obviousness (see In re Boesch, 617 F.2d 272 (CCPA 1980)).
Accordingly, it would have been obvious to one of ordinary skill in the art to select TiSiN and MoN from the materials disclosed by Park, as further supported by Jong, to form the claimed metal gate stack, with the expectation of predictable performance.
The applicant argues:
The claims recite that the stack has an improved Vfb of +125 mV relative to a stack comprising a TiN work function layer, and a reduced EOT relative to a stack comprising a TiN capping layer and a MoN work function layer. The prior art of record fails to show these limitations in the claims. Nakamura teaches improvements in Vfb but only for a TiN capping layer, not for TiSiN.
The examiner responds:
Park (see, e.g., fig. 7C) teaches a PMOS metal gate stack comprising a high-k gate dielectric 414, a capping layer 426A, and a work function layer 426B. Park explicitly discloses that the capping layer may be formed of TiSiN (see, e.g., par.0116/l.4), and that the PMOS work function layer may be formed of MoN (see, e.g., par. 0118/l.5). Hence, Park teaches that the disclosed gate stack provides improved flat-band voltage (Vfb) and reduced EOT increases relative to gate stacks including TiN.
While Park does not expressly quantify the magnitude of the Vfb improvement, Nakamura teaches that the flat-band voltage of a PMOS transistor is a result-effective variable that may be predictably adjusted by modifying the thickness of the capping layer (see, e.g., fig. 3 and par. 0040). Nakamura discloses that variations in capping layer thickness can produce Vfb shifts of several hundred millivolts, up to approximately 500 mV, demonstrating that substantial Vfb adjustments are achievable through routine gate stack optimization.
Although Nakamura’s experimental data illustrated in figure 3B is for a TiN capping layer, Nakamura also teaches that TiSiN is an alternative capping layer material (see, e.g., par. 0031/l.10-11), and the mechanism for Vfb adjustment described by Nakamura arises from gate stack electrostatics rather than from a material-specific anomaly. Accordingly, one of ordinary skill in the art would have reasonably expected that similar thickness-dependent Vfb adjustments would occur when TiSiN is used as the capping layer.
Like Nakamura, Jong teaches that the work function of a gate stack can be adjusted by adjusting the thickness of the capping and work function layers (see, e.g., par. 00669). Jong further teaches that the work function of a PMOS transistor may be tuned by selecting appropriate work function materials (see, e.g., 0116-0118), reinforcing that Vfb optimization through material selection and layer thickness adjustment was well known in the art.
Therefore, it would have been obvious to one of ordinary skill in the art to implement the TiSiN/MoN gate stack taught by Park and to adjust the capping layer thickness, as taught by Nakamura, to obtain a desired Vfb improvement, including an improvement of greater than +125 mV relative to a stack comprising a TiN work function layer. Achieving such a Vfb value represents no more than the predictable result of routine optimization of known result-effective variables.
Applicant has not provided evidence demonstrating that the claimed Vfb improvement is unexpected in kind or that the claimed value reflects criticality beyond what is taught or suggested by the prior art.
Conclusion
Applicant's amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, this action is made final. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire three months from the mailing date of this action. In the event a first reply is filed within two months of the mailing date of this final action and the advisory action is not mailed until after the end of the three-month shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than six months from the mailing date of this final action.
Papers related to this application may be submitted directly to Art Unit 2814 by facsimile transmission. Papers should be faxed to Art Unit 2814 via the Art Unit 2814 Fax Center. The faxing of such papers must conform to the notice published in the Official Gazette, 1096 OG 30 (15 November 1989). The Art Unit 2814 Fax Center number is (571) 273-8300. The Art Unit 2814 Fax Center is to be used only for papers related to Art Unit 2814 applications.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Marcos D. Pizarro at (571) 272-1716 and between the hours of 9:00 AM to 7:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Marcos.Pizarro@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/Marcos D. Pizarro/Primary Examiner, Art Unit 2814
MDP/mdp
January 8, 2026