DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Previous action: claims 1 through 13, 15 through 16, 22 through 25, and 27 rejected.
Present action: claims 1 through 13, 15 through 16, 22 through 25, and 27 rejected.
Previous rejection of claim under 35 U.S.C. 112, 2nd paragraph withdrawn, new rejection of claims 22 through 25 under 35 U.S.C. 112, 2nd paragraph applied.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 22 through 25 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 25 recites the limitation "the second integrated circuit" in 12 and 13. There is insufficient antecedent basis for this limitation in the claim. Further, there is no precedent first integrated circuit. For the purpose of examination the examiner will assume that the amendment was erroneously placed.
Claims 22, 23, and 24 depend from and incorporate claim 25.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s) or interpreted for the purpose of examination.
Claim(s) 1 through 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2022/0139880) in view of Chen (US 2020/0058632) in view of Bhagavat (US 2014/0145300).
Regarding claim 1.
Lee teaches:
An integrated circuit structure, comprising: a semiconductor device, comprising:
a backside BEOL structure (fig 5c:230; [para 0052]) comprising a plurality of wirings (fig 5c:232; [para 0052]) respectively in a dielectric layers (fig 5c:231; [para 0052]), wherein the plurality of wirings (fig 5c:232; [para 0052]) comprises a power/ground interconnect (fig 5c:232; [para 0034,0052]);
a front end of line (FEOL) structure (fig 5c:ID2; [para 0050]) disposed over the backside BEOL structure (fig 5c:230; [para 0052]) and comprising a device (fig 5c:212; [para 0050]) and a power/ground contact (fig 5c; [para 0034,0050]) connecting the device (fig 5c:212; [para 0050]), the power/ground interconnect (fig 5c:232; [para 0034,0052]) connecting the power/ground contact (fig 5c; [para 0034,0050]);
a front side back end of line (BEOL) structure (fig 5c:222; [para 0048,0051]) disposed over a front side of the FEOL structure (fig 5c:ID2; [para 0050]);
;
and a carrier substrate (fig 5b:400; [para 0051]) attached to the front side BEOL structure (fig 5c:222; [para 0048,0051]) .
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Lee does not teach an encapsulating dielectric material is substantially coplanar with a lateral side surface of the FEOL structure, and an opposite lateral side surface of the backside BEOL structure is coplanar with a lateral side surface of the dielectric material
Chen teaches:
a backside BEOL structure (fig 1d:500; [para 0022]) comprising a plurality of wirings (fig 1d:520; [para 0022]) respectively in a plurality of dielectric layers (fig 1d:510; [para 0022]), wherein the plurality of wirings (fig 1d:520; [para 0022]) comprises a interconnect;
a dielectric material (fig 1b:400; [para 0020]) laterally encapsulating the FEOL structure (fig 1b:300; [para 0019]) and the front side BEOL structure (fig 1b:200; [para 0020]), wherein a lateral side surface of the backside BEOL structure (fig 1L:900; [para 0035]) is substantially coplanar with a lateral side surface of the FEOL structure (fig 1b:300; [para 0019]), and an opposite lateral side surface of the backside BEOL structure (fig 1L:900; [para 0035]) is coplanar with a lateral side surface of the dielectric material (fig 1b:400; [para 0020])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide an encapsulating layer with lateral side surfaces coplanar with lateral side surfaces of the BEOL structures in order to facilitate singulation of the devices using cutting (Chen; [para 0037]), further it would have been obvious to provide the wiring layers in a plurality of dielectric layers in order that the structure can be built up layer by layer.
Lee does not teach an adhesive bonding layer on the carrier
Bhagavat teaches:
a carrier substrate (fig 7hL:714; [para 0074]) attached through an adhesive layer (fig 7h:713; [para 0074]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide an adhesive for the carrier substrate in order that the bond will be temporary making removal of the carrier easier (paragraph 74)
Regarding claim 2.
Lee in view of Chen in view of Bhagavat teaches the integrate circuit structure as claimed in claim 1, further:
Lee teaches:
the front side BEOL structure is free of power/ground interconnect connecting the power/ground contact (fig 5c).
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Regarding claim 3.
Lee in view of Chen in view of Bhagavat teaches the integrate circuit structure as claimed in claim 1, further:
Lee teaches:
a base substrate (fig 5a:211; [para 0050]) disposed between the FEOL structure (fig 5c:ID2; [para 0050]) and the backside BEOL structure (fig 5c:230; [para 0052]) and a through substrate via (fig 5c:241; [para 0051]) extending through the base substrate (fig 5c:211; [para 0050]) and connecting the power/ground contact (fig 5c:222p; [para 0051])
Regarding claim 4.
Lee in view of Chen in view of Bhagavat teaches the integrate circuit structure as claimed in claim 1, further:
Lee teaches:
a power/ground terminal disposed (fig 5e:321; [para 0054]) on the backside BEOL structure (fig5c,5e:230; [para 0052]) and connecting the power/ground interconnect (fig 5c:232; [para 0054]).
Regarding claim 5.
Lee in view of Chen in view of Bhagavat teaches the integrate circuit structure as claimed in claim 1, further:
Lee teaches:
an I/O terminal disposed on a bonding surface of the front side BEOL structure (fig 5c:222; [para 0048,0051]) and connecting an I/O contact on the FEOL structure (fig 5c,d:ID2; [para 0050]).
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Regarding claim 6.
Lee in view of Chen in view of Bhagavat teaches the integrate circuit structure as claimed in claim 1, further:
Lee teaches:
the FEOL structure (fig 6a:242; [para 0052]) is in contact with the backside BEOL structure (fig 5c:230; [para 0052]), and the front side BEOL structure (fig 5c:222; [para 0048,0051]).
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Regarding claim 7.
Lee in view of Chen in view of Bhagavat teaches the integrate circuit structure as claimed in claim 1, further:
Lee teaches:
an I/O terminal disposed on a bonding surface of the backside BEOL structure (fig 5c:230; [para 0052]) and connecting an I/O contact on the FEOL structure (fig 5c:242; [para 0039,0051]).
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Regarding claim 8
Lee in view of Chen in view of Bhagavat teaches the integrate circuit structure as claimed in claim 1, further:
Lee does not teach in the embodiment a dielectric material covering side structures of the FEOL and the front side BEOL.
Lee teaches a second embodiment:
wherein the dielectric material (fig 8:310; [para 0066]) covers a side surface of the FEOL structure, and a side surface of the front side BEOL structure (fig 7,8; [para 0035.0066]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a dielectric over front and side surface in order to encapsulate and thereby protect the fabricated structure from contamination and damage.
Claim(s) 9, 10, 11, 12, 13 and 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2022/0139880) in view of Chen (US 2020/0058632) in view of Yu (US 2015/0303174)
Regarding claim 9.
Lee teaches:
A stacked integrated circuit structure, comprising:a first integrated circuit (fig 6a:100; [para 0064]) comprising:
a semiconductor dies (fig 6a:100 ; [para 0055]) , wherein each of the semiconductor dies (fig 6a:100; [para 0055]) comprises:
a first FEOL structure comprising a first device (fig 6a:id1; [para 0042]) and a first power/ground contact (fig 6a,8141; [para 0060]) connecting the first device (fig 6a:id1; [para 0042]);
a first front side BEOL structure disposed over a front side of the first FEOL structure;
and a first backside BEOL structure (fig 6a,8:330; [para 0060]) extended over the first FEOL structure of each of the semiconductor dies (fig 6a:100; [para 0055]), wherein the first backside BEOL structure (fig 5c:230; [para 0052]) comprising a plurality of wirings (fig 5c:232; [para 0052]) respectively in a dielectric layers (fig 5c:231; [para 0052]);
a second integrated circuit (fig 6a:200; [para 0057]) stacked over the first integrated circuit (fig 6a:100; [para 0057]) and bonded with the first front side BEOL structure (fig 6a,8; [para 0060]);
and a dielectric material (fig 6a,8:310; [para 0060]) laterally encapsulating the first FEOL structure and the first front side BEOL structure, .
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Lee does not teach an encapsulating dielectric material is substantially coplanar with a lateral side surface of the FEOL structure, and an opposite lateral side surface of the backside BEOL structure is coplanar with a lateral side surface of the dielectric material
Chen teaches:
wherein the first backside BEOL (fig 1d:500; [para 0022])structure comprising a plurality of wirings (fig 1d:520; [para 0022]) respectively in a plurality of dielectric layers (fig 1d:510; [para 0022])
a dielectric material (fig 1b:400; [para 0020]) laterally encapsulating the FEOL structure (fig 1b:300; [para 0019]) and the front side BEOL structure (fig 1b:200; [para 0020]), wherein a lateral side surface of the backside BEOL structure (fig 1L:900; [para 0035]) is substantially coplanar with a lateral side surface of the FEOL structure (fig 1b:300; [para 0019]), and an opposite lateral side surface of the backside BEOL structure (fig 1L:900; [para 0035]) is coplanar with a lateral side surface of the dielectric material (fig 1b:400; [para 0020])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide an encapsulating layer with lateral side surfaces coplanar with lateral side surfaces of the BEOL structures in order to facilitate singulation of the devices using cutting (Chen; [para 0037]), further it would have been obvious to provide the wiring layers in a plurality of dielectric layers in order that the structure can be built up layer by layer.
Lee does not teach side-by-side semiconductor dies.
Yu teaches:
a first integrated circuit comprising: a plurality of semiconductor dies (fig 13a:104a,b; [para 0088]) arranged in a side-by-side manner (fig 13a; [para 0088]), wherein each of the plurality of semiconductor dies comprises
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to encapsulate multiple stacks of side-by-side die in order to increase the functionality of the device by providing more operating device Duplication of Parts. In reHarza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960).
Regarding claim 10
Lee in view of Chen in view of Yu teaches the stacked integrated circuit structure as claimed in claim 9, further:
Lee teaches:
the first integrated circuit further comprises the dielectric material (fig 6a,8:310; [para 0060]) covering side surfaces of the first FEOL structure, and the first front side BEOL structure (fig 6a,8; [para 0066]).
Regarding claim 11.
Lee in view of Chen in view of Yu teaches the stacked integrated circuit structure as claimed in claim 9, further:
Lee teaches:
the first integrated circuit (fig 6a:100; [para 0064]) further comprises a first I/O terminal on a bonding surface of the first front side BEOL structure bonded with second integrated circuit (fig 6a,8:200; [para 0023,0056]).
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Regarding claim 12.
Lee in view of Chen in view of Yu teaches the stacked integrated circuit structure as claimed in claim 9, further:
Lee teaches:
the second integrated circuit (fig 6a,8:200; [para 0056]) comprises:
a second FEOL structure comprising a second device (fig 6a:ID2; [para 0061]]) and a second power/ground contact (fig 6a:222; [para 0050]) connecting the second device (fig 6a:ID2; [para 0061]); a second front side BEOL structure disposed on a front side of the first front side BEOL structure;
and a second backside BEOL structure (fig 6a,8:340; [para 0056]) disposed on a backside of the first front side BEOL structure where the second power/ground contact is disposed (fig 8).
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Regarding claim 13.
Lee in view of Chen in view of Yu teaches the stacked integrated circuit structure as claimed in claim 9, further:
Lee teaches:
the second integrated circuit comprises: a base substrate (fig 6a,8:211; [para 0050]);
a second FEOL structure disposed over the base substrate;
and a second BEOL structure disposed over and electrically connecting the second FEOL structure, wherein the second BEOL structure is bonded with the first front side BEOL structure (fig 8; [para 0060,0065]).
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Regarding claim 27.
Lee in view of Chen in view of Yu teaches the stacked integrated circuit structure as claimed in claim 9, further:
Lee teaches:
the second integrated circuit (fig 6a:200; [para 0059]) is attached to the first front side BEOL structure and a top surfaced of the dielectric material (fig 6a:310; [para 0060]).
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Claim(s) 15 and16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2022/0139880) in view of Chen (US 2020/0058632) in view of Yu (US 2015/0303174) as applied to claim 9 above, and further in view of Park (US 2016/0351472).
Regarding claim 15.
Lee in view of Chen in view of Yu teaches the stacked integrated circuit structure as claimed in claim 9,
Lee in view of Chen in view of Yu does not teach an additional semiconductor device positioned between the first and second integrated circuits.
Park teaches:
providing an additional semiconductor device (fig 11:620; [para 0164]) between a first integrated circuit (fig 11:620; [para 0164]) and a second integrated circuit (fig 11:620; [para 0164]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide an additional semiconductor device in order to provide additional semiconductor device functions. In reHarza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960).
Regarding claim 16.
Lee in view of Chen in view of Yu in view of Park teaches the stacked integrated circuit structure as claimed in claim 15, further:
Park teaches:
the semiconductor device comprises: an intermediate base substrate;
a plurality of intermediate I/O terminals (fig 11:650; [para 0166]) on two opposite sides of the intermediate base substrate (fig 11:620; [para 0166]);
and an intermediate through via (fig 11:622; [para 0166]) extending through the intermediate base substrate (fig 11:620; [para 0166]) and connecting the plurality of intermediate I/O terminals (fig 11:650; [para 0166]), wherein the plurality of intermediate I/O terminals are connected to a first I/O terminals of the first integrated circuit (fig 11:620; [para 0166]) and a second I/O terminals of the second integrated circuit (fig 11:620; [para 0166]) respectively.
Claim(s) 25, 22, 23, and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2022/0139880) in view of Chen (US 2020/0058632) in view of Yu (US 2015/0303174)
Regarding claim 25.
Lee teaches:
An integrated circuit structure, comprising:
a semiconductor dies (fig 6a:1000; [para 0057]) , wherein each of the semiconductor dies (fig 6a:1000; [para 0057]) comprises:
a FEOL structure comprising a device (fig 6a,8:Id1; [para 0042]) and a power/ground contact connecting the device;
and a front side BEOL structure disposed over a front side of the FEOL structure (fig 6a,8; [para 0024,0026]);
a dielectric material (fig 6a:310; [para 0058]) [surrounding the of semiconductor die];
and a backside BEOL structure (fig 8:330; [para 0060]) in contact with a back side of the FEOL structure of each of the semiconductor dies (fig 6a:1000; [para 0057]), (
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Lee does not teach an encapsulating dielectric material is substantially coplanar with a lateral side surface of the FEOL structure, and an opposite lateral side surface of the backside BEOL structure is coplanar with a lateral side surface of the dielectric material
Chen teaches:
a semiconductor die (fig 1c,1L:310; [para 0017]), wherein the semiconductor die (fig 1c,1L:310; [para 0017]) comprises: a FEOL structure (fig 1b:300; [para 0019]);
and a front side BEOL structure (fig 1L:200; [para 0035]) disposed over a front side of the FEOL structure (fig 1b:300; [para 0019]);
a dielectric material (fig 1b:400; [para 0020]) (laterally surrounding)the semiconductor die (fig 1c,1L:310; [para 0017]);
and a backside BEOL structure (fig 1c,1L:900; [para 0035]) in contact with a back side of the FEOL structure (fig 1b:300; [para 0019]) of each of the semiconductor die (fig 1c,1L:310; [para 0017]), wherein a lateral side surface of the backside BEOL structure (fig 1c,1L:900; [para 0035]) is substantially coplanar with a lateral side surface of the FEOL structure (fig 1b:300; [para 0019]) of the semiconductor die (fig 1c,1L:310; [para 0017]),
and is coplanar with a lateral side surface of the the dielectric material (fig 1b:400; [para 0020])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide an encapsulating layer with lateral side surfaces coplanar with lateral side surfaces of the BEOL structures in order to facilitate singulation of the devices using cutting (Chen; [para 0037])
Yu teaches:
a plurality of semiconductor dies (fig 13b:104a; [para 0084]): arranged in a side-by-side manner (fig 13b), wherein each of the plurality of semiconductor dies (fig 13b:104a; [para 0084]) comprises:
a dielectric material filling (fig 12c,13b:124; [para 0084]) a gap between the plurality of semiconductor dies (fig 13b:104a; [para 0084]);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to encapsulate multiple stacks of die in order to increase the functionality of the device by providing more operating device Duplication of Parts. In reHarza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960).
Regarding claim 22.
Lee in view of Chen in view of Yu teaches the integrated circuit structure of claim 25, further:
Lee teaches:
the dielectric material (fig 6a:310; [para 0058]) is in contact with an upper surface of the backside BEOL structure (fig 8:330; [para 0060]).
Regarding claim 23.
Lee in view of Chen in view of Yu teaches the integrated circuit structure of claim 25, further:
Lee teaches:
the semiconductor device comprises a carrier (fig 6a:340; [para 0056]) disposed on a bonding surface of the front side BEOL structure (fig 8; [para 0035,0056).
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Regarding claim 24.
Lee in view of Chen in view of Yu teaches the integrated circuit structure of claim 25, further:
Lee teaches:
the dielectric material (fig 6a:310; [para 0060]) laterally encapsulating the FEOL structure and the front side BEOL structure and covering a side surface of each layer of the FEOL structure (fig 8; [para 0030,0035]).
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Response to Arguments
Applicant's arguments filed 6/9/2026 have been fully considered but they are not persuasive.
The applicant argues that the prior art does not teach the limitations of the amended claims.
However, the applicant will note, as detailed in the rejection above, that the combinations of Lee (US 2022/0139880) in view of Chen (US 2020/0058632) in view of Bhagavat (US 2014/0145300) and Lee (US 2022/0139880) in view of Chen (US 2020/0058632) in view of Yu (US 2015/0303174) teaches the limitations of the amended claims.
In particular, regarding claims 1 and 9 the applicant will note that Chen teaches forming the BEOL structure comprising a plurality of dielectric layer with a plurality of wiring layers embedded therein.
Regarding claim 25, the claim is unclear and ambiguous regarding the presence of “the second integrated circuit” because the element lacks antecedent basis and there is not first integrated circuit. The examiner assumes that the amendment was intended for a different claim that comprised proper antecedence.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J GOODWIN whose telephone number is (571)272-8451. The examiner can normally be reached Monday - Friday, 11:00 - 19:00.
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/D.J.G/Examiner, Art Unit 2817 /NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817
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