Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment
The amendment filed on 05/19/2025 has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, claims 1-9, 11-15, and 21-26 are pending in this application.
Response to Arguments
Note: Applicant’s arguments regarding Lee teaching the limitations of claims 5-6 have been found persuasive. Therefore, the previous rejection has been withdrawn.
Applicant's arguments filed 05/19/2025 have been fully considered but they are moot.
I. Applicant asserts:
Regarding claim 1, Huang does not teach "a gate spacer, wherein the first fin structure, the second fin structure, the capping layer, the gate dielectric layer, and the first gate electrode and the second gate electrode are disposed between a first sidewall surface of the gate spacer and a second sidewall surface of the gate spacer."
Examiner’s response:
The claim amendments necessitated new search and Zang et al. (US 9911736 B1; hereinafter “Zang”) has been found. Zang discloses, in figs. 24A-24B, a device comprising:
a gate spacer (499) (C. 13, L. 64-67 and C. 14, L. 1-35),
wherein a first fin structure (411), a second fin structure (451) (C. 17, L. 1-20), a gate dielectric layer (481) (C. 17, L. 30-35), and a first gate electrode (416) and a second gate electrode (456) (C. 18, L. 11-15) are disposed between a first sidewall surface of the gate spacer (left sidewall surface of 499) and a second sidewall surface of the gate spacer (right sidewall surface of 499).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Zang into the device of Huang form a gate spacer to isolate the source/drain regions from the gate.
The combined teachings of Huang and Zang disclose wherein the capping layer (Huang: fig. 10B, 66) are disposed between a first sidewall surface of the gate spacer (Zang: figs. 24A-24B, left sidewall surface of 499) and a second sidewall surface of the gate spacer (Zang: figs. 24A-24B, right sidewall surface of 499).
II. Applicant asserts:
Regarding claim 21, Chi does not teach "a first fin structure disposed on a substrate over a first doped region having a first conductivity type and a second fin structure disposed on the substrate over a second doped region having a second conductivity type different than the first conductivity type.. . wherein an interface of the first gate electrode and the second gate electrode overlies an interface of the first doped region and the second doped region."
Examiner’s response:
The claim amendments necessitated new search and Liaw et al. (US 20160284695 A1; hereinafter “Liaw”) has been found.
Liaw discloses, in figs. 1A-1C, a device comprising:
a first fin structure 112 disposed on a substrate 174 over a first doped region 114 having a first conductivity type (e.g., p-type well) (¶18-19, 30) and
a second fin structure 111 disposed on the substrate 174 over a second doped region 113 having a second conductivity type (e.g., n-type) different than the first conductivity type (¶18-19, 30),
wherein an interface of a first gate electrode 172 and a second gate electrode 171 overlies an interface of the first doped region 114 and the second doped region 113 (¶36).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Liaw into the device of Chi such that individual FETs can be controlled independently with different work function gate materials (¶36-37 of Liaw).
III. Applicant asserts:
Claim 4 depends from independent claim 1, which is believed to be allowable over Huang for at least the foregoing reasons.
Examiner’s response:
As described above, claim 1 is unpatentable over Huang in view of Zang. Therefore, the arguments are moot.
IV. REJECTION OF CLAIMS 5 AND 6 UNDER 35 U.S.C. § 103
Applicant’s arguments regarding Lee teaching the limitations of claims 5-6 have been found persuasive. Therefore, the previous rejection has been withdrawn.
However, an updated search and/or consideration has resulted in new art Ching et al (US 20150091099 A1, hereinafter “Ching”) and Fung et al. (US 20150137268 A1; hereinafter “Fung”). Claims 5-6 are unpatentable over Huang in view of Zang, Ching and Fung.
V. Applicant asserts:
Regarding claim 9, Huang does not teach "a dummy gate disposed over the first semiconductor fin structure."
Examiner’s response:
The claim amendments necessitated new search and Liaw et al. (US 20160284695 A1; hereinafter “Liaw”) has been found.
Liaw discloses, in figs. 1A-1C, a device comprising:
a first semiconductor fin structure 112 disposed over a first-type device region 114 of a substrate and a second semiconductor fin structure 111 disposed over a second-type device region 113 of the substrate,
the second-type device region 113 being opposite the first-type device region 114 (¶18-19, 30); and
a dummy gate 124 (¶17) disposed over the first semiconductor fin structure 112.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Liaw into the device of Huang such that individual FETs can be controlled independently with different work function gate materials (¶36-37 of Liaw).
Furthermore, one would have been motivated to form a dummy gate in the device of Huang as Liaw teaches dummy gates are formed alongside gate electrodes in a semiconductor device to provide a fully dense gate environment for facilitating epitaxial growth of source/drain (S/D) regions (¶16 of Liaw).
VI, VII, VIII: No substantial arguments have been presented for claims 22-26. All three independent claims 1, 9 and 21 stand rejected in this Office action and likewise, dependent claims 22-26 are described as rejected as well.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al (US8796666B1, published 2014-08-05, hereinafter “Huang”) in view of Zang et al. (US 9911736 B1; hereinafter “Zang”).
Regarding claim 1, fig. 10B of Huang teaches a device comprising:
a first fin structure (left 44) and a second fin structure (right 44) disposed over a substrate (10), the first structure (left 44) and second fin structure (right 44) each comprising a first sidewall surface (left sidewall of each fin), an opposing second sidewall surface (right sidewall of each fin), and a top surface (top of each fin) extending from the first sidewall surface (left sidewall of each fin) to the opposing second sidewall surface (right sidewall of each fin);
a capping layer (46) that comprises silicon and germanium (col. 4 ln. 17-19) disposed on the first sidewall surface (left sidewall of each fin), the opposing second sidewall surface (right sidewall of each fin), and the top surface (top of each fin) of the first fin structure (left 44);
a gate dielectric layer (62) disposed on the first sidewall surface (left sidewall of the second fin), the opposing second sidewall surface (right sidewall of the second fin), and the top surface (top of the second fin) of the second fin structure (right 44);
a first gate electrode (64) disposed over the capping layer (46) and a second gate electrode (64) disposed over the gate dielectric layer (62) (i.e. there is a gate electrode disposed over both fins).
Huang does not expressly disclose:
a gate spacer,
wherein the first fin structure, the second fin structure, the capping layer, the gate dielectric layer, and the first gate electrode and the second gate electrode are disposed between a first sidewall surface of the gate spacer and a second sidewall surface of the gate spacer.
In the same field of endeavor, Zang discloses, in figs. 24A-24B, a device comprising:
a gate spacer (499) (C. 13, L. 64-67 and C. 14, L. 1-35),
wherein a first fin structure (411), a second fin structure (451) (C. 17, L. 1-20), a gate dielectric layer (481) (C. 17, L. 30-35), and a first gate electrode (416) and a second gate electrode (456) (C. 18, L. 11-15) are disposed between a first sidewall surface of the gate spacer (left sidewall surface of 499) and a second sidewall surface of the gate spacer (right sidewall surface of 499).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Zang into the device of Huang form a gate spacer to isolate the source/drain regions from the gate.
The combined teachings of Huang and Zang disclose wherein the capping layer (Huang: fig. 10B, 66) are disposed between a first sidewall surface of the gate spacer (Zang: figs. 24A-24B, left sidewall surface of 499) and a second sidewall surface of the gate spacer (Zang: figs. 24A-24B, right sidewall surface of 499).
Regarding claim 2, Huang in view of Zang teaches the device of claim 9 provided above.
Furthermore, fig. 10B of Huang teaches the gate dielectric layer (62) extends from the second fin structure (right 44) to the first fin structure (left 44), such that the gate dielectric layer (62) is disposed over the first fin structure (left 44) and the gate dielectric layer (62) is between the first gate electrode (64) and the capping layer (46).
Regarding claim 3, Huang in view of Zang teaches the device of claim 9 provided above.
Furthermore, fig. 10B of Huang teaches the gate dielectric layer (62) is a first gate dielectric layer, the device further comprising a second gate dielectric layer (62, since there's no stated difference between the first and second gate dielectric layers) disposed on the capping layer (46) and between the capping layer (46) and the first gate electrode (64).
Regarding claim 7, Huang in view of Zang teaches the device of claim 1 provided above.
Zang further discloses, in figs. 24A-24B, the device of claim 1, wherein: the first fin structure (411) is associated with a first transistor having a first-type of conductivity (e.g., p-type) and the second fin structure (451) is associated with a second transistor having a second-type of conductivity (e.g., n-type), and the second-type of conductivity is being opposite the first-type of conductivity (C. 12, L. 65-67, C. 13, L. 1-5).
Regarding claim 8, Huang in view of Zang teaches the device of claim 1 provided above.
Zang further discloses, in figs. 24A-24B, wherein the first-type of conductivity is p-type and the second-type of conductivity of n-type (C. 12, L. 65-67, C. 13, L. 1-5).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Zang and Liaw et al. (US 20160284695 A1; hereinafter “Liaw”).
Regarding claim 4, Huang in view of Zang teaches the device of claim 1 provided above. Huang does not teach wherein: the first gate electrode is formed of a different material than the second gate electrode, and wherein the first gate electrode interfaces with the second gate electrode.
However, Zang discloses, in figs. 24A-24B, the device comprising: a first gate electrode (416) formed of a different material than a second gate electrode (456), and wherein the first gate electrode (416) interfaces with the second gate electrode (456) (C. 18, L. 11-15).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Zang into the device of Huang such that individual FETs can be controlled independently with different work function gate materials (¶36-37 of Liaw).
Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Zang and further in view of Ching et al (US 20150091099 A1, hereinafter “Ching”) and Fung et al. (US 20150137268 A1; hereinafter “Fung”).
Regarding claim 5, Huang in view of Zang teaches the limitations of claim 1 as provided above. Huang in view of Zang does not teach source/drain feature disposed on the first fin structure, and wherein the capping layer includes a first concentration of germanium and the source/drain feature includes a second concentration of germanium that is different than the first concentration of germanium.
However, in a similar field of endeavor, figs. 9A-9B of Ching teaches source/drain feature (36) disposed on a first fin structure (21) (¶9, 13), and
wherein a capping layer (24B3) includes a first concentration of germanium (para. [0020], " Furthermore, germanium-rich portions 24B have a gradient germanium percentage, with the germanium percentage of the outmost portion being the highest. In the directions of arrows 44, the germanium percentages gradually and continuously decrease, until the germanium percentage is reduced to the germanium percentage of center portions 24A. Layers 24B 1, 24B2, and 24B3 are schematically illustrated to show the layers that have increasingly reduced germanium percentages.") and
the source/drain feature (36) includes a second concentration of germanium (para. [0013], " epitaxy regions 36 comprise silicon germanium with a germanium percentage between about 15 percent and about 60 percent").
Ching teaches germanium-rich portions 24B may have germanium percentages between about 45 percent and about 100 percent and the capping layer 24B3 has the lowest germanium percentages (¶20) and S/D regions 36 comprise silicon germanium with a germanium percentage between about 15 percent and about 60 percent (¶13).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify the teachings of Ching and have a different concentration of germanium in the capping layer than in S/D region in the device of Huang/Zang in order to provide stress inducing S/D portions and achieve high mobility and improve transistor performance (¶2-5, 11-12 of Fung).
It has been held to be within the general skill of a worker in the art to select a different concentration of germanium in the capping layer than in S/D region on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. A person of ordinary skills in the art is motivated to select different concentration of germanium in the capping layer than in S/D region in order to control strain and mobility in the channel region and thus control device performance.
Regarding claim 6, Huang in view of Zang, Ching and Fung teach the limitations of claim 5.
As described above, Ching teaches germanium-rich portions 24B may have germanium percentages between about 45 percent and about 100 percent and the capping layer 24B3 has the lowest germanium percentages (¶20) and S/D regions 36 comprise silicon germanium with a germanium percentage between about 15 percent and about 60 percent (¶13).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify the teachings of Ching and have a higher second concentration of germanium in the S/D region than a first concentration in capping layer in the device of Huang/Zang in order to provide stress inducing S/D portions and achieve high mobility and improve transistor performance (¶2-5, 11-12 of Fung).
It has been held to be within the general skill of a worker in the art to select a higher concentration of S/D region than in the capping layer on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. A person of ordinary skills in the art is motivated to select a higher concentration of germanium in the S/D region in the capping layer in order to control strain and mobility in the channel region and thus control device performance.
Claim(s) 9, 12-15, 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al (US8796666B1, published 2014-08-05, hereinafter “Huang”) in view of Liaw et al. (US 20160284695 A1; hereinafter “Liaw”).
Regarding claim 9, fig. 10B of Huang teaches
a capping layer (46) that includes silicon and germanium (col. 4 ln. 17-19) disposed directly on a top surface (top of each fin) and opposing sidewall surfaces (left and right sidewalls of each fin) of the first semiconductor fin structure (left 44);
a gate dielectric layer (62) disposed directly on a top surface (top of each fin) and opposing sidewall surfaces (left and right sidewalls of each fin) of the second semiconductor fin structure (right 44) and directly on the capping layer (46) disposed directly on the top surface (top of each fin) and opposing sidewall surfaces (left and right sidewalls of each fin) of the first semiconductor fin structure (left 44); and
a first gate electrode (64) disposed over the capping layer (46) and a second gate electrode (64) disposed over the gate dielectric layer (62) (i.e. there is a gate electrode disposed over both fins).
Huang does not teach a first semiconductor fin structure disposed over a first-type device region of a substrate and a second semiconductor fin structure disposed over a second-type device region of the substrate, the second-type device region being opposite the first-type device region; and a dummy pate disposed over the first semiconductor fin structure.
In the same field of endeavor, Liaw discloses, in figs. 1A-1C, a device comprising:
a first semiconductor fin structure 112 disposed over a first-type device region 114 of a substrate and a second semiconductor fin structure 111 disposed over a second-type device region 113 of the substrate,
the second-type device region 113 being opposite the first-type device region 114 (¶18-19, 30); and
a dummy gate 124 (¶17) disposed over the first semiconductor fin structure 112.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Liaw into the device of Huang such that individual FETs can be controlled independently with different work function gate materials (¶36-37 of Liaw).
Furthermore, one would have been motivated to form a dummy gate in the device of Huang as Liaw teaches dummy gates are formed alongside gate electrodes in a semiconductor device to provide a fully dense gate environment for facilitating epitaxial growth of source/drain (S/D) regions (¶16 of Liaw).
Regarding claim 12, Huang in view of Liaw teaches the device of claim 9 provided above. Huang does not teach the first gate electrode is formed of a different material than the second gate electrode, and wherein the first and second gate electrodes extend to the same height above the substrate.
Liaw further discloses, in figs. 1A-1C, the first gate electrode 172 is formed of a different material than the second gate electrode 171 (¶36-37), and wherein the first and second gate electrodes 172, 171 extend to the same height above the substrate 174 (shown in fig. 1B).
Regarding claim 13, Huang in view of Liaw teaches the device of claim 9 provided above.
Liaw further discloses, in figs. 1A-1C, the first-type device region is p-type (i.e., P-well; 114) and the second-type device region is n-type (i.e., N-well; 113) (¶18-19, 30).
Regarding claim 14, Huang in view of Liaw teaches the device of claim 9 provided above.
Furthermore, fig. 10B of Huang teaches a dielectric isolation feature (32, col. 2 ln. 39-45) disposed on the substrate (10) between the first semiconductor fin structure (left 44) and the second semiconductor fin structure (right 44, the 32 elements are between each fin), wherein the capping layer (46) interfaces with the dielectric isolation feature (32, col. 2 ln. 39-45).
Regarding claim 15, Huang in view of Liaw teaches the device of claim 14 provided above.
Furthermore, fig. 10B of Huang teaches the dielectric isolation feature (32, col. 2 ln. 39-45) extends continuously from the first semiconductor fin structure (left 44) to the second semiconductor fin structure (right 44); and
the gate dielectric layer (62) interfaces with the dielectric isolation feature (32, col. 2 ln. 39-45, 62 is in contact with an interface of 32).
Regarding claim 26, Huang in view of Liaw teaches the device of claim 9 provided above.
Liaw further discloses, in figs. 1, 1A-1B, the device further comprising a source/drain feature (S/D features in the fins 112, underneath the contact 145) disposed in the first semiconductor fin structure 112 and disposed between the first gate electrode 172 (shown as 123 in fig. 1) and the dummy gate 124 (¶26, 43-44).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Liaw into the device of Huang and dispose the S/D features in the first semiconductor fin structure and disposed between the first gate electrode and the dummy gate.
One would have been motivated to do so as Liaw teaches the epitaxial growth of the source/drains is facilitated or improved in a fully dense gate environment. Such an environment is achievable when dummy gates are arranged alongside gate electrodes so as to promote epitaxial growth of the source/drains between gate electrodes and adjacent dummy gates (¶44 of Liaw).
Claim(s) 21-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chi et al (US20130270641A1, published 2013-10-17, hereinafter “Chi”) in view of Liaw et al. (US 20160284695 A1; hereinafter “Liaw”).
Regarding claim 21, figs. 1A - 1H of Chi teaches:
a first fin structure (20A) and a second fin structure (20B) disposed on a substrate (10), wherein the first fin structure (20A) and a second fin structure (20B) each include a first sidewall surface (left sidewall of each fin), an opposing second sidewall surface (right sidewall of each fin), and a top surface (top of each fin) extending from the first sidewall surface (left sidewall of each fin) to the second sidewall surface (right sidewall of each fin);
a capping layer (30) that includes silicon and germanium (para. [0030]) disposed directly on the first sidewall surface (left sidewall of each fin) and the second sidewall surface (right sidewall of each fin) of the first fin structure (20A), wherein the capping layer (30) is not disposed on the second fin structure (20B, 30 is not disposed on 20B);
a gate dielectric layer (40A) disposed directly on the first sidewall surface (left sidewall of each fin), the second sidewall surface (right sidewall of each fin), and the top surface (top of each fin) of the second fin structure (20B), wherein the gate dielectric layer (40A) extends to at least the capping layer (30) disposed directly on the first sidewall surface (left sidewall of each fin) of the first fin structure (30, 40A extends across both the first and second fins 20A and 20B); and
a first gate electrode (40B) disposed over the capping layer (30) disposed directly on the first sidewall surface (left sidewall of each fin) and the second sidewall surface (right sidewall of each fin) of the first fin structure (20A) and a second gate electrode (40B) disposed over and interfacing with the gate dielectric layer (40A) disposed directly on the first sidewall surface (left sidewall of each fin), the second sidewall surface (right sidewall of each fin), and the top surface (top of each fin) of the second fin structure (20B).
Chi does not expressly disclose the first fin structure disposed on the substrate over a first doped region having a first conductivity type and the second fin structure disposed on the substrate over a second doped region having a second conductivity type different than the first conductivity type, wherein an interface of the first gate electrode and the second gate electrode overlies an interface of the first doped region and the second doped region.
In the same field of endeavor, Liaw discloses, in figs. 1A-1C, a device comprising:
a first fin structure 112 disposed on a substrate 174 over a first doped region 114 having a first conductivity type (e.g., p-type well) (¶18-19, 30) and
a second fin structure 111 disposed on the substrate 174 over a second doped region 113 having a second conductivity type (e.g., n-type) different than the first conductivity type (¶18-19, 30),
wherein an interface of a first gate electrode 172 and a second gate electrode 171 overlies an interface of the first doped region 114 and the second doped region 113 (¶36).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Liaw into the device of Chi such that individual FETs can be controlled independently with different work function gate materials (¶36-37 of Liaw).
Regarding claim 22, Chi in view of Liaw teaches the limitations of claim 21 as provided above.
Liaw further discloses, in figs. 1A-1C, wherein: the first gate electrode 172 comprises a first set of material layers, and the second gate electrode 171 comprises a second set of material layers that is different than the first set of material layers (¶36-37).
Regarding claim 23, Chi in view of Liaw teaches the limitations of claim 21 as provided above.
Liaw further discloses, in figs. 1A-1C, wherein: the first set of material layers of the first gate electrode 172 comprises a first type work function layer, the second set of material layers of the second gate electrode 171 comprises a second type work function layer, and the first type work function layer is different than the second type work function layer (¶36-37).
Claims 24 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Chi in view of Liaw and further in view of Ching et al (US 20150091099 A1, hereinafter “Ching”) and Fung et al. (US 20150137268 A1; hereinafter “Fung”).
Regarding claim 24, Chi in view of Liaw teaches the limitations of claim 21 as provided above.
Chi in view of Liaw does not teach a source/drain feature disposed on the first fin structure, and wherein the capping layer that comprises silicon and germanium interfaces with the source/drain feature.
However, in a similar field of endeavor, figs. 9A-9B of Ching teaches source/drain feature (36) disposed on a first fin structure (21) (¶9, 13), and
wherein a capping layer (24B3) that comprises silicon and germanium interfaces with the source/drain feature (36) (¶13, 20).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify the teachings of Ching and have a germanium in the S/D region in the device of Huang/Zang in order to provide stress inducing S/D portions and achieve high mobility and improve transistor performance (¶2-5, 11-12 of Fung).
It has been held to be within the general skill of a worker in the art to select a germanium in the S/D region on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. A person of ordinary skills in the art is motivated to select germanium in the S/D region in order to control strain and mobility in the channel region and thus control device performance.
Regarding claim 25, Chi in view of Liaw, Ching and Fung teach the limitations of claim 24 as provided above. Chi does not teach the source/drain feature comprises germanium at a first concentration and the capping layer comprises germanium at a second concentration that is different than the first concentration.
However, in a similar field of endeavor, figs. 9A-9B of Ching teaches source/drain feature (36) disposed on a first fin structure (21) (¶9, 13), and
wherein a capping layer (24B3) includes a first concentration of germanium (para. [0020], " Furthermore, germanium-rich portions 24B have a gradient germanium percentage, with the germanium percentage of the outmost portion being the highest. In the directions of arrows 44, the germanium percentages gradually and continuously decrease, until the germanium percentage is reduced to the germanium percentage of center portions 24A. Layers 24B 1, 24B2, and 24B3 are schematically illustrated to show the layers that have increasingly reduced germanium percentages.") and
the source/drain feature (36) includes a second concentration of germanium (para. [0013], " epitaxy regions 36 comprise silicon germanium with a germanium percentage between about 15 percent and about 60 percent").
Ching teaches germanium-rich portions 24B may have germanium percentages between about 45 percent and about 100 percent and the capping layer 24B3 has the lowest germanium percentages (¶20) and S/D regions 36 comprise silicon germanium with a germanium percentage between about 15 percent and about 60 percent (¶13).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify the teachings of Ching and have a different concentration of germanium in the capping layer than in S/D region in the device of Huang/Zang in order to provide stress inducing S/D portions and achieve high mobility and improve transistor performance (¶2-5, 11-12 of Fung).
It has been held to be within the general skill of a worker in the art to select a different concentration of germanium in the capping layer than in S/D region on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. A person of ordinary skills in the art is motivated to select different concentration of germanium in the capping layer than in S/D region in order to control strain and mobility in the channel region and thus control device performance.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NILUFA RAHIM whose telephone number is (571)272-8926. The examiner can normally be reached M-F 9am-5:30pm EST.
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/NILUFA RAHIM/Primary Examiner, Art Unit 2893
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