DETAILED ACTION
The RCE filed February 25, 2026 has been entered. Claims 1-20 are pending. Claim 12 and 19 have been cancelled. Claims 1, 11 and 16 are independent.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 10, 11, 13, 18 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by McCombs et al. (US 2013/0188435).
Regarding independent claim 1, McCombs et al. disclose a static random access memory device (para. 31: … SRAM … external system memory 405 may also include a shared I/O unit …), comprising:
a cell array (see FIG. 3) comprising a plurality memory cells, wherein the cell array is divided into a first sub array (13A) and a second sub array (13B) reducing a bit line length of bit lines of the cell array by half1 (see FIG. 3, and also so EXMINER’S MARKUP below), and wherein:
the first sub array (13A, and also see EXAMINER’S MARKUP below) comprises:
a first plurality of memory cells (array Bitcells 0) of the plurality of memory cells arranged in a first plurality of columns (e.g., para. 0007: the memory includes a number of storage arrays each configured to provide data on respective bitlines …; further this is an inherent characteristic of memory array structure), wherein each column comprises a bit line (bl) and a bit line bar (blb),
a first plurality of bit lines (bl on 13A, along with para. 0007, i.e., data on respective bitlines) connected to the first plurality of memory cells (13A), and
a first plurality of bit lines bars (blb on 13A, along with para. 0007, i.e., data on respective bitlines) connected to the first plurality of memory cells (13A), wherein the first plurality of bit lines and the first plurality of bit line bars are respectively coupled to a portion of the first plurality of memory cells that are disposed in that column (see FIG. 3 and accompanying disclosure, along with EXMINER’S MARKUP below); and
the second sub array (13B, and also see EXAMINER’S MARKUP below) comprises comprising:
a second plurality of memory cells (array Bitcells 1) of the plurality of memory cells arranged in a second plurality of columns (e.g., para. 0007: the memory includes a number of storage arrays each configured to provide data on respective bitlines …; further this is an inherent characteristic of memory array structure), wherein each column comprises a bit line (bl) and a bit line bar (blb),
a second plurality of bit lines (bl on 13B, along with para. 0007, i.e., data on respective bitlines) connected to the second plurality of memory cells (13B), and
a second plurality of bit lines bars (blb on 13B, along with para. 0007, i.e., data on respective bitlines) connected to the second plurality of memory cells (13B), wherein the second plurality of bit lines and the second plurality of bit line bars are respectively coupled to a portion of the second plurality of memory cells that are disposed in that column (see FIG. 3 and accompanying disclosure, along with EXMINER’S MARKUP below); and
a single input output block (219A-B, 27 and 29, and also see EXAMINER’S MARKUP below) placed between the first sub array (13A) and the second sub array (13B), wherein the single IO block comprises a first side and a second side opposite the first side (see FIG. 3, and also see EXAMINER’S MARKUP below), wherein the first side is configured to receive each of the first plurality of bit lines and the first plurality of bit line bars (bl/blb coupled 13A, along with para. 0007, i.e., data on respective bitlines …) extending from the first sub array directly to the IO block, wherein the second side is configured to receive each of the second plurality of bit lines and the second plurality of bit line bars (bl/blb coupled 13B, along with para. 0007, i.e., data on respective bitlines …) extending from the second sub array directly to the IO block (see FIG. 3, and also see EXAMINER’S MARKUP below), and wherein the IO block comprises:
a shared latch (29) configured to receive latch output signals from both the first sub array and the second sub array,
a data input terminal (FIG. 2 (Components shown in FIG. 3 that are the same as those shown in FIG. 2): Din) connected to the shared latch and configured to receive data to be written input the first plurality of memory cells or the second plurality of memory cells and
a data output terminal (FIGS 2-3: d_out) connected to the shared latch and configured to provide data read from the first plurality of memory cells or the second plurality of memory cells (see FIGS. 1-3 along with EXAMINER’S MARKUP below, and accompanying disclosure).
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Regarding claims 10 and 13, which depends from claims 1 and 11, respectively, McCombs et al. disclose a write controller coupled to the first plurality of bit lines and the second plurality of bit lines (see e.g., FIG. 1 and accompanying disclosure).
Regarding independent claim 11, McCombs et al. disclose a memory device (para. 31: … SRAM … external system memory 405 may also include a shared I/O unit …), comprising:
an array (see FIG. 3) comprising a plurality memory cells, wherein the cell array is divided into a first sub array (13A) and a second sub array (13B) reducing a bit line length of bit lines of the cell array by half1 (see FIG. 3, and also so EXMINER’S MARKUP above), and wherein:
the first sub array (13A, and also see EXAMINER’S MARKUP above) comprises:
a first plurality of memory cells (array Bitcells 0) of the plurality of memory cells arranged in a first plurality of columns (e.g., para. 0007: the memory includes a number of storage arrays each configured to provide data on respective bitlines …; further this is an inherent characteristic of memory array structure), wherein each column comprises a bit line (bl) and a bit line bar (blb),
a first plurality of bit lines (bl on 13A, along with para. 0007, i.e., data on respective bitlines) connected to the first plurality of memory cells (13A), and
a first plurality of bit lines bars (blb on 13A, along with para. 0007, i.e., data on respective bitlines) connected to the first plurality of memory cells (13A), wherein the first plurality of bit lines and the first plurality of bit line bars are respectively coupled to a portion of the first plurality of memory cells that are disposed in that column (see FIG. 3 and accompanying disclosure, along with EXMINER’S MARKUP above); and
the second sub array (13B, and also see EXAMINER’S MARKUP above) comprises comprising:
a second plurality of memory cells (array Bitcells 1) of the plurality of memory cells arranged in a second plurality of columns (e.g., para. 0007: the memory includes a number of storage arrays each configured to provide data on respective bitlines …; further this is an inherent characteristic of memory array structure), wherein each column comprises a bit line (bl) and a bit line bar (blb),
a second plurality of bit lines (bl on 13B, along with para. 0007, i.e., data on respective bitlines) connected to the second plurality of memory cells (13B), and
a second plurality of bit lines bars (blb on 13B, along with para. 0007, i.e., data on respective bitlines) connected to the second plurality of memory cells (13B), wherein the second plurality of bit lines and the second plurality of bit line bars are respectively coupled to a portion of the second plurality of memory cells that are disposed in that column (see FIG. 3 and accompanying disclosure, along with EXMINER’S MARKUP above); and
a single input output block (219A-B, 27 and 29, and also see EXAMINER’S MARKUP above) placed between the first sub array (13A) and the second sub array (13B), wherein the single IO block comprises a first side and a second side opposite the first side (see FIG. 3, and also see EXAMINER’S MARKUP above), wherein the first side is configured to receive each of the first plurality of bit lines and the first plurality of bit line bars (bl/blb coupled 13A, along with para. 0007, i.e., data on respective bitlines …) extending from the first sub array directly to the IO block, wherein the second side is configured to receive each of the second plurality of bit lines and the second plurality of bit line bars (bl/blb coupled 13B, along with para. 0007, i.e., data on respective bitlines …) extending from the second sub array directly to the IO block (see FIG. 3, and also see EXAMINER’S MARKUP above), and wherein the IO block comprises:
a shared latch (29) configured to receive latch output signals from both the first sub array and the second sub array,
a data input terminal (FIG. 2 (Components shown in FIG. 3 that are the same as those shown in FIG. 2): Din) connected to the shared latch and configured to receive data to be written input the first plurality of memory cells or the second plurality of memory cells and
a data output terminal (FIGS 2-3: d_out) connected to the shared latch and configured to provide data read from the first plurality of memory cells or the second plurality of memory cells (see FIGS. 1-3 along with EXAMINER’S MARKUP above, and accompanying disclosure).
Regarding independent claim 18, McCombs et al. disclose a method of forming a static random access memory device (para. 31: … SRAM … external system memory 405 may also include a shared I/O unit …), the method comprising:
forming an array (see FIG. 3) comprising a plurality memory cells, wherein the cell array is divided into a first sub array (13A) and a second sub array (13B) reducing a bit line length of bit lines of the cell array by half1 (see FIG. 3, and also so EXMINER’S MARKUP above), and wherein:
forming the first sub array (13A, and also see EXAMINER’S MARKUP above) comprises:
a first plurality of memory cells (array Bitcells 0) of the plurality of memory cells arranged in a first plurality of columns (e.g., para. 0007: the memory includes a number of storage arrays each configured to provide data on respective bitlines …; further this is an inherent characteristic of memory array structure), wherein each column comprises a bit line (bl) and a bit line bar (blb),
a first plurality of bit lines (bl on 13A, along with para. 0007, i.e., data on respective bitlines) connected to the first plurality of memory cells (13A), and
a first plurality of bit lines bars (blb on 13A, along with para. 0007, i.e., data on respective bitlines) connected to the first plurality of memory cells (13A), wherein the first plurality of bit lines and the first plurality of bit line bars are respectively coupled to a portion of the first plurality of memory cells that are disposed in that column (see FIG. 3 and accompanying disclosure, along with EXMINER’S MARKUP above); and
the second sub array (13B, and also see EXAMINER’S MARKUP above) comprises comprising:
a second plurality of memory cells (array Bitcells 1) of the plurality of memory cells arranged in a second plurality of columns (e.g., para. 0007: the memory includes a number of storage arrays each configured to provide data on respective bitlines …; further this is an inherent characteristic of memory array structure), wherein each column comprises a bit line (bl) and a bit line bar (blb),
a second plurality of bit lines (bl on 13B, along with para. 0007, i.e., data on respective bitlines) connected to the second plurality of memory cells (13B), and
a second plurality of bit lines bars (blb on 13B, along with para. 0007, i.e., data on respective bitlines) connected to the second plurality of memory cells (13B), wherein the second plurality of bit lines and the second plurality of bit line bars are respectively coupled to a portion of the second plurality of memory cells that are disposed in that column (see FIG. 3 and accompanying disclosure, along with EXMINER’S MARKUP above); and
forming a shared input output (IO) block (219A-B, 27 and 29, and also see EXAMINER’S MARKUP above) placed between the first sub array and the second sub array;
extending each of the first plurality of bit lines and the first plurality of bit line bars from the first sub array directly to the IO block (see FIG. 3 along with para. 0007, i.e., data on respective bitlines, and also see EXAMINER’S MARKUP above);
extending each of the second plurality of bit lines and the first plurality of bit line bars from the second sub array directly to the IO block (see FIG. 3 along with para. 0007, i.e., data on respective bitlines, and also see EXAMINER’S MARKUP above), and wherein the IO block comprises:
a shared latch (29) configured to receive latch output signals from both the first sub array and the second sub array,
a data input terminal (FIG. 2 (Components shown in FIG. 3 that are the same as those shown in FIG. 2): Din) connected to the shared latch and configured to receive data to be written into the first plurality of memory cells or the second plurality of memory cells, and
a data output terminal (FIGS 2-3: d_out) connected to the shared latch and configured to provide data read from the first plurality of memory cells or the second plurality of memory cells; and
writing data (FIG. 2 (Components shown in FIG. 3 that are the same as those shown in FIG. 2): Din and Write driver) into the static random access memory device (see FIGS. 1-3 along with EXAMINER’S MARKUP below, and accompanying disclosure).
Further, regarding method claim 18, where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. Examiner has an authority to shift the burden to applicant and require applicant to either: (1) show the prior art memory device and the claimed memory device are not substantially identical; or (2) prove, by evidence, that the prior art memory device is not capable of performing the functions claimed. see MPEP 2112.01(I).
Regarding claim 20, which depends from claim 18, McCombs et al. disclose reading data from the static random access memory device (FIG. 3: sense amp 27 and accompanying disclosure).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 15 are rejected under AIA 35 U.S.C. 103 as being unpatentable over McCombs et al. (US 2013/0188435) in view of Hama (US 2019/0096486).
Regarding claim 2, McCombs et al. teach the limitations of claim 1.
McCombs et al. do not explicitly disclose a word line driver configured to select a row from the first sub array or the second sub array.
However, McCombs teaches a memory array and claimed a word line driver in a memory array is a well-known technology for a type for memory for its purpose.
For support, of the above asserted facts, see for example, Hama teaches in FIG. 2: ROW DECODER, which is the same as applicant’s figure 1: 120.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Hama to the teaching of McCombs et al. such that a memory, as taught by McCombs et al., utilizes a word line driver, as taught by Hama, for the purpose of select word lines, and further these conventional technology are well established in the art of the memory devices.
Regarding claim 15, McCombs et al. teach the limitations of claim 11.
McCombs et al. do not explicitly disclose the IO block comprises a word line driver configured to select a row from the first sub array or the second sub array.
Hama teaches the deficiencies in FIG. 2: ROW DECODER, which is the same as applicant’s figure 1: 120.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Hama to the teaching of McCombs et al. such that a memory, as taught by McCombs et al., utilizes a word line driver, as taught by Hama, for the purpose of select word lines, and further these conventional technology are well established in the art of the memory devices.
Claims 3-9, 14 and 16-17 are rejected under AIA 35 U.S.C. 103 as being unpatentable over McCombs et al. (US 2013/0188435) in view of Shinozaki et al. (US 2008/0266928).
Regarding claims 3 and 16, McCombs et al. teach the limitations of claims 1 and 11, respectively.
McCombs does not explicitly disclose the limitations of claims 3 and 16.
Shinozaki et al. teach a first read multiplexer (FIG. 6: top YSW) coupled to receive data from the first plurality of bit lines, and configured provide a first output in response to a first column select signal; and a second read multiplexer (FIG. 6: bottom YSW) coupled to receive data from the second plurality of bit lines, and configured provide a second output in response to a second column select signal.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Shinozaki et al. to the teaching of McCombs et al. such that a memory, as taught by McCombs et al., utilizes a multiplexer, as taught by Shinozaki et al., for the purpose of select bit lines, and further these conventional technology are well established in the art of the memory devices.
Regarding claims 4 and 17, McCombs et al. teach the limitations of claims 1 and 11, respectively.
McCombs et al. further teach the shared output latch (FIG. 3: 29).
McCombs et al. do not explicitly disclose first and second sense amplifiers.
Shinozaki et al. teach a first sense amplifier (FIG. 6: top left SA) coupled to receive data from the first plurality of bit lines and provide a first output to an output latch; and a second sense amplifier (FIG. 6: top right SA) coupled to receive data from the second plurality of bit lines and provide a second output to an output latch.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Shinozaki et al. to the teaching of McCombs et al. such that a memory, as taught by McCombs et al., utilizes a sense amplifier, as taught by Shinozaki et al., for the purpose of reading differential data, and further these conventional technology are well established in the art of the memory devices.
Regarding claim 5, McCombs et al. and Shinozaki et al., as combined, teach the limitations of claim 4.
Shinozaki et al. further teach the first sense amplifier is not coupled to receive data from the second plurality of bit lines, and wherein the second sense amplifier is not coupled to receive data from the first plurality of bit lines (see e.g., FIG. 6 and accompanying disclosure).
Regarding claim 6, McCombs et al. and Shinozaki et al., as combined, teach the limitations of claim 4.
McCombs et al. and Shinozaki et al. do not explicitly disclose the limitations of claim 6.
However, the first and second sense amplifiers are configured with tri-state logic is a well-known technology for a type of memory circuit for its purpose.
For support, of the above asserted facts, see for example, Mori (US 2014/0003134), FIGS. 11-12 and accompanying disclosure.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize tri-state logic in SRAM sense amplifier circuit because these conventional technology are well established in the art of the memory devices.
Regarding claim 7, McCombs et al. teach the limitations of claim 1.
McCombs et al. do not explicitly disclose a plurality of word lines connected to the first sub array and the second sub array; and a row decoder connected to the plurality of word lines.
However, the limitations of claim 7 is a well-known technology for a type memory for its purpose.
For support, of the above asserted facts, see for example, Shinozaki et al. (US 2008/0266928), FIG. 6 and accompanying disclosure.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize static random access memory used as configuration random access memory in selecting row and columns because these conventional technology are well established in the art of the memory devices.
Regarding claims 8-9 and 14, McCombs et al. teach the limitations of claims 1 and 11, respectively.
McCombs et al. do not explicitly disclose a third sub array and a fourth sub array, wherein the first sub array and the third sub array are positioned on a first side of the IO block and the second sub array and the fourth sub array are positioned on a second side of the IO block opposite the first side, and wherein the first sub array and the second sub array are positioned on a first side of a row decoder and the third sub array and the fourth sub array are positioned on a second side of the row decoder.
However, the limitations of claims 8-9 and 14 are a well-known technology for a type memory for its purpose.
For support, of the above asserted facts, see for example, Shinozaki et al. (US 2008/0266928), FIG. 6 and accompanying disclosure.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize static random access memory extending several arrays because these conventional technology are well established in the art of the memory devices.
Response to Argument
All claims are the same invention, in which a standard memory array structure is simply described, i.e., all claims are identical to or patentably indistinct from, or have unity of invention with claims in the application prior to the entry of the submission under 37 CFR 1.114 (that is, restriction (including a lack of unity of invention) would not be proper) and all claims could have been finally rejected on the grounds and art of record in the next Office action if they had been entered in the application prior to entry under 37 CFR 1.114. Accordingly, THIS ACTION IS MADE FINAL even though it is a first action after the filing of a request for continued examination and the submission under 37 CFR 1.114. See MPEP § 706.07(b). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached on M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached on 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SUNG IL CHO/Primary Examiner, Art Unit 2825
1 See McCombs’s FIG. 3, and further, this is one of the primary reasons why semiconductor memory employs a bank (sub-array) structure.
Prosecution Insights