DETAILED ACTION
This office action is in response to amendment filed 12/09/2025.
Claims 1-20 are pending. Claims 3, 4, 6, 9, 11, and 13-20 have been withdrawn. Claims 1 and 7 have been amended.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 2, 5, 7, 8, 10 and 12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claims 1 and 7 reciting “the first memory device” and “the second memory devices” render the claims indefinite for lacking antecedent basis. It is unclear what is intended by “the first memory device” and “the second memory devices” and how are they related to “the first memory cell” and “the second memory cell”.
Claims 1 and 7 reciting “a respective control gate that is separated from a respective on of the first storage node and the second storage node” and “the respective control gates of the first storage node and the second storage node” render the claims indefinite. Initially, the claims recite the control gates are separate from the storage nodes. The claim also recites the control gates are “of the first storage node and the second storage node” seemingly require the control gates to be parts of the storage nodes. Such contradictory limitation renders the intended scope of the claim indefinite.
Other claims are rejected for depending on a rejected claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 5, 7, 8, 10 and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Seo et al. US 2014/0131785 A1 (Seo).
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In re claim 1, as best understood, Seo discloses (e.g. FIGs. 1-4 & 9-10) an apparatus comprising:
a three-dimensional (3D) NAND structure with a vertical channel CH to conduct current to a first storage node FG of a first memory cell (a lower cell in memory stack) and to a second storage node FG of a second memory cell (an upper cell in memory stack), the vertical channel CH having a polysilicon material to conduct current (¶ 41), and the vertical channel CH having a drain region (region corresponding to level of protrusion P between neighboring gate levels in the memory stack, see highlighted drain region annotated in FIG. 4A above) between the first storage node FG (lower cell) and the second storage node FG (upper cell), wherein each of the first memory cell and the second memory cell further includes a respective control gate CG that is separated from a respective one of the first storage node FG and the second storage node FG by one or more respective dielectric layers 12, and wherein the drain region extends between extensions of two adjacent edges of respective control gates CG of “the first memory device” and “the second memory devices” (“extends between extensions” does not require extending entirely from one of the extension to the other extension; see FIG. 4A above, the drain region corresponding to the highlighted part of the channel layer extends in a region and is disposed between the extensions of the two adjacent edges of the CG); and
a recess (corresponding to location of protrusions P; recess R2 in FIG. 9C) in the drain region filled with a structure P in the recess to extend away from a center of the vertical channel CH and toward “the respective control gates CG of the first storage node (lower cell) and the second storage node (upper cell)”, to reduce resistance in the drain region along the vertical channel between the first storage node and the second storage node (¶ 41-42);
wherein a region between the first storage node FG and the vertical channel layer CH has a first length W1 measured in parallel to a length of the vertical channel (see FIG. 2B), and the drain region has a second length W3 measured in parallel to the length of the vertical channel (see FIG. 4A annotated above), the second length W3 being shorter than the first length W1 (there exists a part of the channel layer between the two gate levels that can be considered as the “drain region” with a length that is smaller than the length of the storage node in the vertical direction).
In an alternative second interpretation, “a region between the first storage node and the vertical channel” may correspond to the highlighted region of the insulator as shown in the annotated FIG. 4A below, which is at least partially “between the first storage node FG and the vertical channel CH” as claimed. The “region” has a first length L1 in its entirety. In such interpretation, the “drain region” can extending entirely from an extension of an edge of one control gate to an extension of an adjacent edge of another control gate (see annotated below). As such, a second length L2 of the “drain region” is shorter than the first length L1 of the entire “region”.
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In re claim 2, Seo discloses (e.g. FIG. 4A) wherein the structure comprises a tab P of polysilicon doped more heavily than the polysilicon material of the vertical channel CH (“protrusions P may comprise a polysilicon layer doped with impurities, and the channel layer CH may include a polysilicon layer not doped with impurities”, ¶ 42), to extend from the polysilicon material of the vertical channel CH.
In re claim 5, Seo discloses (e.g. FIG. 1-4) wherein the first storage node FG (lower cell) and the second storage node FG (upper cell) comprise floating gates FG.
In re claim 7, as best understood, Seo discloses a system (FIGs. 11A-11B) comprising:
a controller 110,211; and
a storage device 120,212 coupled to the controller 110,211, the storage device 120,211 including (¶ 73, FIGs. 1-4 & 9-10)
a three-dimensional (3D) NAND structure with a vertical channel CH to conduct current to a first storage node FG of a first memory cell (a lower cell in memory stack) and to a second storage node FG of a second memory cell (an upper cell in memory stack), the vertical channel CH having a polysilicon material to conduct current (¶ 41), and the vertical channel CH having a drain region (region corresponding to level of protrusion P between neighboring gate levels in the memory stack, see highlighted drain region annotated in “first interpretation” of FIG. 4A above) between the first storage node FG (lower cell) and the second storage node FG (upper cell), wherein each of the first memory cell and the second memory cell further includes a respective control gate CG that is separated from a respective one of the first storage node FG and the second storage node FG by one or more respective dielectric layers 12, and wherein the drain region extends between extensions of two adjacent edges of respective control gates CG of “the first memory device” and “the second memory devices” (“extends between extensions” does not require extending entirely from one of the extension to the other extension; see “first interpretation” of FIG. 4A above, the drain region corresponding to the highlighted part of the channel layer extends in a region and is disposed between the extensions of the two adjacent edges of the CG);
a recess (corresponding to location of protrusions P; recess R2 in FIG. 9C) in the drain region to extend away from a center of the vertical channel CH and toward “the respective control gates CG of the first storage node (lower cell) and the second storage node (upper cell)”; and
a structure P in the recess to reduce resistance in the drain region along the vertical channel between the first storage node and the second storage node (¶ 41-42);
wherein a region between the first storage node FG and the vertical channel layer CH has a first length W1 measured in parallel to a length of the vertical channel (see FIG. 2B), and the drain region has a second length W3 measured in parallel to the length of the vertical channel (see FIG. 4A annotated above), the second length W3 being shorter than the first length W1 (there exists a part of the channel layer between the two gate levels that can be considered as the “drain region” with a length that is smaller than the length of the storage node in the vertical direction).
In an alternative second interpretation, “a region between the first storage node and the vertical channel” may correspond to the highlighted region of the insulator as shown in the annotated “second interpretation” of FIG. 4A above, which is at least partially “between the first storage node FG and the vertical channel CH” as claimed. The “region” has a first length L1 in its entirety. In such interpretation, the “drain region” can extending entirely from an extension of an edge of one control gate to an extension of an adjacent edge of another control gate (see annotated below). As such, a second length L2 of the “drain region” is shorter than the first length L1 of the entire “region”.
In re claim 8, Seo discloses (e.g. FIG. 4A) wherein the structure comprises a tab P of polysilicon doped more heavily than the polysilicon material of the vertical channel CH (“protrusions P may comprise a polysilicon layer doped with impurities, and the channel layer CH may include a polysilicon layer not doped with impurities”, ¶ 42), to extend from the polysilicon material of the vertical channel CH.
In re claim 10, Seo discloses (e.g. FIG. 1-4) wherein the first storage node (lower cell) and the second storage node (upper cell) comprise floating gates FG.
In re claim 12, Seo discloses (e.g. 11A-11B) further comprising one or more of:
a host processor device 112,220 coupled to the controller 110,211;
a display communicatively coupled to a host processor;a network interface 250 communicatively coupled to a host processor 211; or
a battery to power the system (¶ 76).
Response to Arguments
Applicant's arguments filed 12/09/2025 have been fully considered but they are not persuasive.
Regarding claims rejected over Seo, Applicant argues Seo does not teach “the drain region has a second length measured in parallel to the length of the vertical channel, the second length being shorter than the first length” (Remark, pages 8-9).
This is not persuasive. No specific “drain region” has been claimed that would structurally distinguish over a region of Seo’s channel layer CH corresponding to level of protrusion P between neighboring gate levels in the memory stack (as highlighted in the “first interpretation” of FIG. 4A above). The limitation “extends between extensions” does not require extending entirely from one of the extension to the other extension. Therefore, the “drain region” may correspond to the highlighted part of the channel layer as shown in “first interpretation” of FIG. 4A above. Such “drain region” extends in a region and is disposed between the extensions of the two adjacent edges of the CG. The “drain region” as shown has a length W3 that is smaller than the length W1 of the region between the first storage node FG and the channel CH.
In an alternative second interpretation, “a region between the first storage node and the vertical channel” may correspond to the highlighted region of the insulator as shown in the annotated “second interpretation” of FIG. 4A above, which is at least partially “between the first storage node FG and the vertical channel CH” as claimed. The “region” has a first length L1 in its entirety. In such interpretation, the “drain region” can extending entirely from an extension of an edge of one control gate to an extension of an adjacent edge of another control gate (see annotated below). As such, a second length L2 of the “drain region” is shorter than the first length L1 of the entire “region”.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
CN 107068686 teaches (FIG. 13) control gate layers 1005,1009 having a thickness of 10-100 nm, oxide layer 1007,1011 having a thickness of 20-50nm, thinner than the control gate.
US 9,576,977 B2 teaches (FIG. 2F-2J) control gate 171 filled in widened openings 153C to reduce resistance.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU CHEN whose telephone number is (571)270-7881. The examiner can normally be reached Monday-Friday: 9AM-5PM ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WILLIAM KRAIG can be reached at 5712728660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YU CHEN/Primary Examiner, Art Unit 2896
YU CHEN
Examiner
Art Unit 2896