DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4/24/2026 has been entered.
Claims 1-20 are pending. Claims 3, 4, 6, 9, 11, and 13-20 have been withdrawn. Claims 1, 7, and 13 have been amended.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5, 7-8, 10, and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhu CN 107068686 A (cited in PTO-892 mailed on 1/30/2026, foreign document and English translation mailed with PTO-892) in view of Yoo US 2016/0118403 A1.
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In re claim 1, Zhu discloses (e.g. FIGs. 1-15) an apparatus comprising:
a three-dimensional (3D) NAND structure with a vertical channel 1029 to conduct current to a first storage node (charge trapping layer or floating gate of 1023 adjacent gate 1005, ¶ 42-43) of a first memory cell (a lower cell in memory stack) and to a second storage node (charge trapping layer or floating gate of 1023 adjacent to gate 1009) of a second memory cell (an upper cell in memory stack), the vertical channel 1029 having a polysilicon material to conduct current (¶ 50), and the vertical channel 1029 having a drain region S/D (corresponding to region of 1029 at the level of 1007 between neighboring gates 1005,1009 in the memory stack) between the first storage node (in 1023 adjacent to gate 1005 of lower cell) and the second storage node (in 1023 adjacent to gate 1009 of upper cell), wherein each of the first memory cell and the second memory cell further includes a respective control gate 1005,1009 that is separated from a respective one of the first storage node (charge trapping layer or floating gate of 1023) and the second storage node (charge trapping layer or floating gate of 1023) by one or more respective dielectric layers (second gate dielectric layers, ¶ 42-43), and wherein a separation layer 1007 extends between extensions of two adjacent edges of respective control gates 1005,1009 to separate the first memory cell and the second memory cell; and
a recess (corresponding to location of protrusions 1027; recess formed in FIG. 9) in the separation layer 1007 is filled with a structure 1027 that extends away from a center of the vertical channel 1029 and toward the respective control gates 1005,1009 of the first memory cell and the second memory cell, to reduce resistance in the drain region S/D along the vertical channel 1029 between the first storage node and the second storage node (dopants from 1027 reduces resistance of the S/D region ¶ 49);
wherein the respective control gate 1005 of the first memory cell has a thickness measured in parallel to a length of the vertical channel 1029 (1005 has a thickness of about 10-100nm, ¶ 32);
wherein the separation layer 1007 has a second thickness measured in parallel to the length of the vertical channel 1029, from a first adjacent edge (upper edge of 1005) to a second adjacent edge (lower edge of 1009) of the two adjacent edges of the respective control gates 1005,1009 of the first memory cell and the second memory cell (1007 has a thickness of about 20-50nm, ¶ 32).
Zhu teaches the thickness of the separation layer 1007 is about 20-50 nm and the thickness of the control gate 1005 at about 10-100 nm (¶ 32). The thickness of range of the separation layer is less than the thickness range of the control gate 1005.
Furthermore, Yoo discloses a 3D NAND structure including gate openings 153C with increased sizes (see FIG. 2G-2J, ¶ 45) so that the volume of the conductive patterns 171 filling the opening 153C can be increased to reduce resistance (¶ 28,49).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Zhu’s control gates 1005 to have a greater thickness than the separation layer 1007 to increase the gate volume for reducing resistance as taught by Yoo.
In re claim 2, Zhu discloses (e.g. FIGs. 10-12) wherein the structure comprises a tab S/D,1027 of polysilicon doped more heavily than the polysilicon material of the vertical channel 1029 (due to presence of dopant source layer 1027, ¶ 49-53), to extend from the polysilicon material of the vertical channel 1029.
In re claim 5, Zhu discloses (e.g. FIGs. 1-15) wherein the first storage node and the second storage node comprise floating gates (¶ 43).
In re claim 7, Zhu discloses a system comprising:
a controller (processor, ¶ 66); and
a storage device coupled to the controller (¶ 66), the storage device including (FIGs. 1-15)
a three-dimensional (3D) NAND structure with a vertical channel 1029 to conduct current to a first storage node (charge trapping layer or floating gate of 1023 adjacent gate 1005, ¶ 42-43) of a first memory cell (a lower cell in memory stack) and to a second storage node (charge trapping layer or floating gate of 1023 adjacent to gate 1009) of a second memory cell (an upper cell in memory stack), the vertical channel 1029 having a polysilicon material to conduct current (¶ 50), and the vertical channel 1029 having a drain region S/D (corresponding to region of 1029 at the level of 1007 between neighboring gates 1005,1009 in the memory stack) between the first storage node (in 1023 adjacent to gate 1005 of lower cell) and the second storage node (in 1023 adjacent to gate 1009 of upper cell), wherein each of the first memory cell and the second memory cell further includes a respective control gate 1005,1009 that is separated from a respective one of the first storage node (charge trapping layer or floating gate of 1023) and the second storage node (charge trapping layer or floating gate of 1023) by one or more respective dielectric layers (second gate dielectric layers, ¶ 42-43), and wherein a separation layer 1007 extends between extensions of two adjacent edges of respective control gates 1005,1009 to separate the first memory cell and the second memory cell; and
a recess (corresponding to location of protrusions 1027; recess formed in FIG. 9) in the separation layer 1007 is filled with a structure 1027 that extends away from a center of the vertical channel 1029 and toward the respective control gates 1005,1009 of the first memory cell and the second memory cell, to reduce resistance in the drain region S/D along the vertical channel 1029 between the first storage node and the second storage node (dopants from 1027 reduces resistance of the S/D region ¶ 49);
wherein the respective control gate 1005 of the first memory cell has a thickness measured in parallel to a length of the vertical channel 1029 (1005 has a thickness of about 10-100nm, ¶ 32);
wherein the separation layer 1007 has a second thickness measured in parallel to the length of the vertical channel 1029, from a first adjacent edge (upper edge of 1005) to a second adjacent edge (lower edge of 1009) of the two adjacent edges of the respective control gates 1005,1009 of the first memory cell and the second memory cell (1007 has a thickness of about 20-50nm, ¶ 32).
Zhu teaches the thickness of the separation layer 1007 is about 20-50 nm and the thickness of the control gate 1005 at about 10-100 nm (¶ 32). The thickness of range of the separation layer is less than the thickness range of the control gate 1005.
Furthermore, Yoo discloses a 3D NAND structure including gate openings 153C with increased sizes (see FIG. 2G-2J, ¶ 45) so that the volume of the conductive patterns 171 filling the opening 153C can be increased to reduce resistance (¶ 28,49).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Zhu’s control gates 1005 to have a greater thickness than the separation layer 1007 to increase the gate volume for reducing resistance as taught by Yoo.
In re claim 8, Zhu discloses (e.g. FIGs. 10-12) wherein the structure comprises a tab S/D,1027 of polysilicon doped more heavily than the polysilicon material of the vertical channel 1029 (due to presence of dopant source layer 1027, ¶ 49-53), to extend from the polysilicon material of the vertical channel 1029.
In re claim 10, Zhu discloses (e.g. FIGs. 1-15) wherein the first storage node and the second storage node comprise floating gates (¶ 43).
In re claim 12, Zhu discloses further comprising one or more of:
a host processor device (e.g. host processor of computer, ¶ 66) coupled to the controller;
a display communicatively coupled to a host processor (e.g. host process and display of a smart phone, ¶ 66);
a network interface communicatively coupled to a host processor (e.g. network interface and display of a smart phone, ¶ 66); or
a battery to power the system (e.g. battery of smart phone, ¶ 66).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-2, 5, 7-8, 10, and 12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU CHEN whose telephone number is (571)270-7881. The examiner can normally be reached Monday-Friday: 9AM-5PM ET.
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/YU CHEN/Primary Examiner, Art Unit 2896
YU CHEN
Examiner
Art Unit 2896
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