DETAILED ACTION
This Office action is in response to the Amendment filed on 17 August 2026. Claims 11-21, 23-30, and 32 are pending in the application. Claims 1-10, 22, and 31 have been cancelled.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11-16 and 32 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al., US 2019/0043959, in view of Yu et al., US 2016/0163816, both newly cited.
With respect to claim 11, Lee et al. disclose a method, shown in Figs. 12-17, comprising:
forming a fin FA protruding from a substrate 110, see Fig. 12 and Paragraphs [0023]-[0028];
forming a gate structure 122 over a channel region of the fin FA, see Fig. 12 and Paragraph [0094];
forming a gate spacer 124 along a sidewall of the gate structure 122, see Fig. 12 and Paragraph [0094];
forming an epitaxial semiconductor material region 114 in the fin FA adjacent the channel region, see Fig. 12 and Paragraph [0091];
depositing a first dielectric layer 126 over the gate structure 122 and the gate spacer 124, see Fig. 12 and Paragraph [0096], the first dielectric layer comprising a first dielectric material (silicon nitride, Paragraph [0033]);
forming a contact plug 140 extending through the first dielectric layer 126 and contacting the epitaxial semiconductor material region 114, wherein an air gap 130R1 separates the contact plug 140 and the gate spacer 124, wherein the air gap 130R1 exposes the epitaxial semiconductor material 114 of the epitaxial semiconductor material region 114, as shown in Fig. 14, see Paragraphs [0097]-[0104];
depositing a second dielectric layer 132 over the first dielectric layer and over the contact plug, comprising sealing a lower region of the air gap with the second dielectric layer, wherein the second dielectric layer comprises a second dielectric material different from the first dielectric material (silicon oxide or silicon oxynitride, see Paragraph [0035]), see Fig. 15 and Paragraphs [[0105]-[0107];
planarizing the second dielectric layer 132 to expose the contact plug 140, wherein after etching the second dielectric layer 130 a remaining portion of the second dielectric layer 132 seals the lower region of the air gap 130R1/134, see Fig. 16 and Paragraph [0108]; and
depositing a conductive material 174 on the contact plug 140, comprising depositing the conductive material between the contact plug and the first dielectric material and on the remaining portion of the second dielectric layer, see Fig. 17 and Paragraph [0110].
Although Lee et al. disclose planarizing the second dielectric layer 132 to expose the contact plug 140 (see Paragraph [0108]), Lee et al. lack anticipation only of etching the second dielectric layer 132 to expose the contact plug 140. In the same field of endeavor, Yu et al. disclose removing a dielectric layer 185 by an etching or planarization step to remove portions of the dielectric layer 185 above an ILD layer 160 while leaving portions sealing the upper ends of the air gaps 180 in position, see Fig. 1L and 1M and Paragraph [0028]. In light of the teaching of Yu et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the second dielectric layer 132 could have been etched rather than planaraized in the known method of Lee et al., since Yu et al. teach that both an etching step and a planarization step are functionally equivalent for removing portions of a dielectric layer to leave a remaining portion of the dielectric layer sealing the upper ends of air gaps.
With respect to claim 12, in the method of Lee et al., an upper region of the air gap 130R1 separates the first dielectric layer 126 and the contact plug 140, as shown in Figs. 14 and 15.
With respect to claim 13, in the method of Lee et al., a thickness of the remaining portion of the second dielectric layer 132 (above air gap 134) is less than a thickness of the first dielectric layer 126, as shown in Fig. 16.
With respect to claim 14, in the method of Lee et al., the remaining portion of the second dielectric layer 132 (below air gap 134) is closer to the substrate 110 than a top surface of the first dielectric layer 126, as shown in Fig. 16.
With respect to claim 15, in the method of Lee et al., the depositing the conductive material 174 comprises depositing the conductive material on a top surface of the first dielectric layer 126, as shown in Fig. 17.
With respect to claim 16, in the method of Lee et al., the remaining portion of the second dielectric layer 132 extends from the first dielectric layer 126 to a spacer layer 144 on the contact plug 140, as shown in Fig. 16.
With respect to claim 32, in the method of Lee et al., a vertical height of the lower region of the air gap 130R1 is greater than a vertical height of the gate spacer 124, as shown in Fig. 16.
Allowable Subject Matter
Claims 21 and 23-30 are allowable over the prior art of record.
The following is a statement of reasons for the indication of allowable subject matter: The closest prior art of record is Cheng et al., US 2019/0334011. However, Cheng et al. fail to teach or suggest recessing the second portion below a top surface of the ILD, as required in amended claim 21.
Claims 17-20 are allowable over the prior art of record.
The following is a statement of reasons for the indication of allowable subject matter: The newly-cited reference to Cheng et al., US 9,716,158, discloses a method Comprising the steps of depositing a first dielectric layer 31 over the gate stack and over the epitaxial source/drain region (see column 6, lines 6-38); forming an opening in the first dielectric layer to expose the epitaxial source/drain region, as shown in Figs. 1A and 1B; depositing a sacrificial material 36 within the opening, as shown in Figs. 4A and 4B; depositing a first conductive material 38 over the sacrificial material 36 within the opening, as shown in Figs. 6A and 6B; removing the sacrificial material 36 to form a gap 40, as shown in Figs. 7A and 7B; and depositing a second dielectric layer 42 over the first dielectric layer 31, over the conductive layer 38, over the gap 40, wherein the second dielectric layer 42 extends a first distance into the gap (see column 10, line 63-67, bridging column 11 to line 8; and column 11, lines 44-47), as shown in Figs. 8A and 8B. However, Cheng et al. do not teach or suggest etching the second dielectric layer to expose the first conductive material, wherein first portions of the second dielectric layer remain within the gap after the etching. Cheng et al. disclose that the second dielectric layer will fill only the uppermost portions of the air gaps 40 and do not show any portion of the second dielectric layer 42 in the air gaps 40 in the patent figures. Therefore, it would not have been obvious that etching the second dielectric layer 42 in the known method of Cheng et al. to expose the first conductive material would result in portions of the second dielectric layer remaining within the gap after the etching, as required in independent claim 17.
Response to Arguments
Applicant’s arguments with respect to claims 11-16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additionally cited references disclose various methods of fabricating semiconductor devices comprising gate spacers and air gaps.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARY A WILCZEWSKI whose telephone number is (571)272-1849. The examiner can normally be reached M-TH 7:30 AM-5:00 PM.
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MARY A. WILCZEWSKI
Primary Examiner
Art Unit 2898
/MARY A WILCZEWSKI/Primary Examiner, Art Unit 2898
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