DETAILED ACTION
This Office action is in response to the Request for Continued Examination (RCE) and Amendment filed on 03 March 2026. Claims 11-21, 23-30, and 32 are pending in the application. Claims 1-10, 22, and 31 have been cancelled.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03 March 2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11-16 and 32 are again rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al., US 2019/0334011, in view of Varghese et al., US 2020/0303246, both newly cited.
With respect to claim 11, Cheng et al. disclose a method comprising:
forming a fin (between source/drain regions 103A, 103B) protruding from a substrate 101, as shown in Fig. 1, see paragraph [0029];
forming a gate structure 102B over a channel region 108 of the fin, as shown in Fig. 1, see paragraph [0030];
forming a gate spacer 1022 along a sidewall of the gate structure 102B, as shown in Fig. 1, see paragraph [0030];
forming an epitaxial semiconductor material region 103A, 103B in the fin adjacent the channel region 108, as shown in Fig. 1, see paragraphs [0031] and [0057];
depositing a first dielectric layer 1021/120/130 over the gate structure 102B and the gate spacer 1022, the first dielectric layer 1021/120/130 comprising a first dielectric material (1021 is silicon nitride, see paragraph [0030]), as shown in Fig. 3, see paragraphs [0030] and [0032]-[0039];
forming a contact plug 701 extending through the first dielectric layer and contacting the epitaxial semiconductor material region, wherein an air gap 801 separates the contact plug and the gate spacer, wherein the air gap exposes a top surface side of the epitaxial semiconductor material region 103A and 103B (A top surface side of the epitaxial semiconductor region 103A/103B is diffusion barrier 150, as shown in Fig. 5. The air gap 801 exposes diffusion barrier 150, as shown in Figs. 6 and 7. Hence, the air gap 801 exposes a top surface side of the epitaxial semiconductor region 103A and 103B.), see Figs. 5-8 and paragraphs [0040]-0044]; and
depositing a second dielectric layer 190 over the first dielectric layer 1021 and over the contact plug 701, comprising sealing a lower region of the air gap 801/200 with the second dielectric layer 190, wherein the second dielectric layer 190 comprises a second dielectric material different from the first dielectric material (190 is silicon dioxide, see paragraph [0045], see Fig. 9 and paragraph [0045].
Cheng et al. lack anticipation only of etching the second dielectric layer to expose the contact plug, wherein after etching the second dielectric layer, a remaining portion of the second dielectric layer seals the lower region of the air gap; and depositing a conductive material on the contact plug, comprising depositing the conductive material between the contact plug and the first dielectric material and on the remaining portion of the second dielectric layer. However, in the same field of endeavor, Varghese et al. disclose etching a second dielectric 120 comprising oxide (see paragraph [0044]) to expose a contact plug 106, as shown in Figs. 1-3, and depositing a conductive material 134 on the remaining portion of the second dielectric layer 120, as shown in Fig. 6, see paragraphs [0063]-[0064]. It is within the purview of the skilled artisan that contacts would have to be formed in the known method of Cheng et al. in order to obtain an operable finFET. Therefore, it would have been obvious to one of ordinary skill in the art to implement the etching and depositing steps taught by Varghese et al. into the known method of Cheng et al. in order to form a contact to the contact plug, thereby yielding a remaining portion of the second dielectric layer 120 that seals the lower region of the air gap 801/200 and conductive material between the contact plug 701 and the first dielectric material 1021 (equivalent to the gate cap 116 in the method of Varghese et al.) and on the remaining portion of the second dielectric layer 190.
With respect to claim 12, as shown in Fig. 9 of Cheng et al., an upper region of the air gap 200 separates the first dielectric layer 1021 and the contact plug 701.
With respect to claim 13, as shown in Fig. 9 of Cheng et al., a thickness of the remaining portion of the second dielectric layer 190 is less than a thickness of the first dielectric layer 1021.
With respect to claim 14, as shown in Fig. 9 of Cheng et al., the remaining portion of the second dielectric layer 190 is closer to the substrate 101 than a top surface of the first dielectric layer 1021.
With respect to claim 15, implementing the etching and depositing steps of Varghese et al. into the known method of Cheng et al. would result in depositing the conductive material 134 on a top surface of the first dielectric layer 1021 (equivalent to the gate cap 116 in the method of Varghese et al.), as shown in Fig. 6 of Varghese et al.
With respect to claim 16, as shown in Fig. 9 of Cheng et al., the remaining portion of the second dielectric layer 190 extends from the first dielectric layer 1021 to a spacer layer 150 on the contact plug 701, see Figs. 6-9.
With respect to claim 32, in the method of Cheng et al., a vertical height of the lower region of the air gap 801/200 is greater than a vertical height of the gate spacer which is covered by the second insulating layer 190, as shown in Annotated Fig. 9 below.
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Allowable Subject Matter
Claims 21 and 23-30 are allowable over the prior art of record.
The following is a statement of reasons for the indication of allowable subject matter: The closest prior art of record is Cheng et al., US 2019/0334011. However, Cheng et al. fail to teach or suggest recessing the second portion below a top surface of the ILD, as required in amended claim 21.
Claims 17-20 are allowable over the prior art of record.
The following is a statement of reasons for the indication of allowable subject matter: The newly-cited reference to Cheng et al., US 9,716,158, discloses a method Comprising the steps of depositing a first dielectric layer 31 over the gate stack and over the epitaxial source/drain region (see column 6, lines 6-38); forming an opening in the first dielectric layer to expose the epitaxial source/drain region, as shown in Figs. 1A and 1B; depositing a sacrificial material 36 within the opening, as shown in Figs. 4A and 4B; depositing a first conductive material 38 over the sacrificial material 36 within the opening, as shown in Figs. 6A and 6B; removing the sacrificial material 36 to form a gap 40, as shown in Figs. 7A and 7B; and depositing a second dielectric layer 42 over the first dielectric layer 31, over the conductive layer 38, over the gap 40, wherein the second dielectric layer 42 extends a first distance into the gap (see column 10, line 63-67, bridging column 11 to line 8; and column 11, lines 44-47), as shown in Figs. 8A and 8B. However, Cheng et al. do not teach or suggest etching the second dielectric layer to expose the first conductive material, wherein first portions of the second dielectric layer remain within the gap after the etching. Cheng et al. disclose that the second dielectric layer will fill only the uppermost portions of the air gaps 40 and do not show any portion of the second dielectric layer 42 in the air gaps 40 in the patent figures. Therefore, it would not have been obvious that etching the second dielectric layer 42 in the known method of Cheng et al. to expose the first conductive material would result in portions of the second dielectric layer remaining within the gap after the etching, as required in independent claim 17.
Response to Arguments
Applicant's arguments filed 03 March 2026 have been fully considered but they are not persuasive. Independent claim 11 has been amended to require “an air gap separates the contact plug and the gate spacer, wherein the air gap exposes a top surface side of the epitaxial semiconductor material region”. Applicant has argued that Cheng’s air gap 801 does not expose a top surface side of Cheng’s source/drain regions 103A/103B. Cheng et al. clearly teach that the source/drain regions are an epitaxial semiconductor material region, as disclosed in paragraph [0057] of Cheng et al. As clearly shown in Fig. 5 of Cheng et al., “a top surface side” of the epitaxial semiconductor material region 103A/103B is diffusion barrier 150. Since the air gap 801 exposes diffusion barrier 150, as shown in Figs. 6 and 7 of Cheng et al., Cheng et al. clearly teach an air gap separates the contact plug 701 and the gate spacer 1022, wherein the air gap exposes a top surface side of the epitaxial semiconductor material region 103A/103B.
As shown in Fig. 9, diffusion barrier 150 forms “a top surface side” of 103A/103B. Hence, diffusion barrier 150 is “a top surface side” of epitaxial semiconductor material region 103A/103B.. Claim 11 does not preclude diffusion barrier 150 from being mapped to “a top surface side” of epitaxial semiconductor material region 103A/103B. Hence, an air gap 801 of Cheng et al. exposes “a top surface side” of the epitaxial semiconductor material region 103A/103B, as required in amended claim 11. For this reason, the method of amended claim 11 is not deemed patentably distinct from the prior art method of Cheng et al. in view of Varghese et al. It is suggested that Applicant amend claim 11 to require “the air gap exposes the epitaxial semiconductor material of the epitaxial semiconductor material region” to patentably distinguish Applicant’s claimed method from that of Cheng et al.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additionally cited references disclose various methods of fabricating semiconductor devices comprising gate spacers and air gaps.
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MARY A. WILCZEWSKI
Primary Examiner
Art Unit 2898
/MARY A WILCZEWSKI/Primary Examiner, Art Unit 2898
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