DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 12 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20200044067 (Banerjee et al) in view of US 20080179694 (Nakazawa et al) and US 20160172474 (Miyake et al).
Referring to claim 12, Banerjee discloses a GaN HEMT device structure comprising (Figs. 1-5): a substrate (102); an epitaxial layer stack grown on the substrate, the epitaxial layer stack comprising a buffer layer (104) and a GaN heterostructure comprising a GaN layer (106) and an overlying AlxGa1-xN barrier layer (108) to form a 2DEG channel region ([0024]-[0025] and [0028]), wherein the AlxGa1-xN barrier layer comprise a first thickness . . . . (Fig. 2, note that layer 108 is etched so that the remaining portion of 108 in the gate area is a first thickness) and a second thickness . . . (Fig. 2, note that layer 108 is unetched in the region laterally between the gate region and the source and the gate region and the drain and therefore has a second thickness that is greater than the first etched thickness of layer 108 in the gate region), a passivation layer (110) formed on the AlxGa1-xN barrier layer (Fig. 2), a gate slot defined in a gate region (Fig. 2 [0030]), the gate slot extending through the passivation layer into the AlxGa1-xN barrier layer (Fig. 2), . . .first thickness of the AlxGa1-xN barrier layer within the gate slot (Fig. 2, note that the thickness of layer 108 is thinner in the gate region than the other formed regions); source and drain openings through the passivation layer defined on source and drain regions of the AlxGa1-xN barrier layer (Fig. 5 and [0047]); a p-doped GaN mesa (344) on said surface of the first thickness of the AlxGa1-xN barrier layer within the gate slot (Fig. 5 and [0041]); source and drain electrodes (522 and 526) formed on the source and drain regions (Fig. 5 and [0047]); a gate electrode (444) formed on the p-doped GaN mesa (Fig. 5 and [0043]); and wherein the AlxGa1-xN barrier layer comprises . . . first thickness in the gate region underlying the p-GaN mesa in the gate slot and comprises said first and second thicknesses in access regions extending between the gate region and the source region and between the gate region and the drain region (Fig. 5, note that layer 108 is unetched in the region laterally between the gate region and the source and the gate region and the drain and therefore has a second thickness that is greater than the first etched thickness of layer 108 in the gate region).
Banerjee does not disclose the first thickness having a first Al%, and a second thickness that is directly on the first thickness with no intervening layer and has a second Al% greater than the first Al%, the second Al% being 25% or less , the gate slot extending through the passivation layer, through the second thickness of the AlxGa1-xN barrier layer into the first thickness of the AlxGa1-xN the gate slot having substantially vertical sidewalls and a bottom of the gate slot being a planar surface defined by a planar surface of the AlxGa1-xN such that a remaining part of the first thickness of the AlxGa1-xN barrier layer is between the bottom of the gate slot and the GaN layer. However, Nakazawa discloses forming a GaN based transistor ([0002]) that has a barrier layer configuration (104) where in the barrier layer has a first thickness (lower portion of layer 104) having a first Al% ([0053]), and a second thickness (upper portion of layer 104) . . . having a second Al%, greater than the first Al% the second Al% being 25% or less ([0053], it is noted that the Al composition in an AlGaN layer (second nitride semiconductor layer 104) may also be varied in the thickness direction. The second nitride semiconductor layer 104 may be formed such that the Al composition value gradually increases from the interface with the first nitride semiconductor layer 103 with approach toward the upper surface of the second nitride semiconductor layer 104. Otherwise, the second nitride semiconductor layer 104 may also obtained by stacking two or more semiconductor layers having different Al composition values ) and the gate slot (110a) having substantially vertical sidewalls and a bottom of the gate slot being a planar surface such that a remaining part of the first thickness of the AlxGa1-xN barrier layer is between the bottom of the gate slot and the GaN layer (Fig. 14), wherein the AlxGa1-xN barrier comprises the remaining part of the first thickness in the gate region underlying the p-GaN mesa in the gate slot and comprises said first and second thicknesses in access regions extending between the gate region and the source region and between the gate region and the drain region (Fig. 14, note that a portion of the barrier layer 104 remains under the gate 117 with the thicknesses of these layers). Nakazawa discloses that the configuration provides the advantage that the two-dimensional electron gas layer 109 is not affected by the depletion layer resulting from surface states irrespective of whether the FET is in the OFF state or in the ON state. This allows suppression of the occurrence of the current collapse. ([0059]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to form a first thickness having a first Al%, and a second thickness having a second Al%, greater than the first Al% the second Al% being 25% or less or the gate slot having substantially vertical sidewalls and a bottom of the gate slot being a planar surface defined by a first thickness of the AlxGa1-xN as disclosed by Nakazawa in order to suppress the occurrence of the current collapse.
Additionally, Miyake discloses a GaN transistor device (Fig. 20) in which and nitride stack is grown on a substrate (S), the stack comprising a buffer layer (BUF) a GaN heterostructure comprising a GaN layer (CH) ([0126] and [0153] note that the channel layer is made of the same materials for all the disclosed embodiments) and an overlying AlxGa1-xN barrier layer (BA1 and BA2) to form a 2DEG channel region (DEG) (Fig. 20), wherein the AlxGa1-xN barrier layer comprise a first thickness (BA1) and a second thickness (BA2) that is directly on the first thickness with no intervening layer and has a second Al%, greater than the first Al ([0165]) and discloses that such configuration reduces access resistance between the drain and the gate ([0165]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to form the AlxGa1-xN barrier layer such that it has a first thickness and second thickness formed directly on the first thickness with no intervening layers and a second Al% greater than the first Al% in order to reduce access resistance between the drain and the gate as disclosed by Miyake.
Regarding claim 16, Banerjee in view Nakazawa and Miyake discloses wherein the first Al% is in the range from 15% to 18%, and the first thickness of the AlxGa1-xN barrier layer is in the range 15nm to 20nm, and the second Al% is in the range from 20% to 25% and the second thickness of the AlxGa1-xN barrier layer is in the range from 5nm to 10nm (Miyake [0153]).
Claim(s) 17 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20200044067 (Banerjee et al) in view of US 20080179694 (Nakazawa et al) and US 20160172474 (Miyake et al) as applied to claim 12 above, and further in view of US 10269947 (Moens et al).
Pertaining to claims 17 and 18, Banerjee in view Nakazawa and Miyake discloses the first Al% and the first thickness of the AlxGa1-xN barrier layer (Miyake [0153]).
Banerjee in view Nakazawa and Miyake does not disclose that it provides a specified threshold voltage of at least 0.9 V for E-mode operation or wherein the first Al% and the first thickness of the AlxGa1-xN barrier layer provide a specified threshold voltage for E-mode operation, and the second Al% and the second thickness of the AlxGa1-xN barrier layer provide a specified Rdson and dynamic Rdson of the GaN HEMT device structure. However, Moens discloses forming an enhancement-mode high electron mobility transistor (HEMT) that can have a threshold voltage greater than 1 V and allow for better control of the HEMT as compared to conventional enhancement-mode HEMTs. The HEMT can have an on-state resistance (RDson) that is similar to a depletion- mode HEMT having an unintentionally doped GaN channel layer and an AlGaN barrier layer overlying the channel layer and similar source-to-gate and gate-to-drain lengths (col. 2 lines 48- 56 and col. 6 lines 27-35). Therefore one of ordinary skill in the art before the effective filing date of the invention would have found it obvious to incorporate the teachings of Moens with respect to the AlxGa1-xN formed in the invention of Banerjee in view Nakazawa and Miyake in order to allow for better control of the HEMT as compared to conventional enhancement-mode HEMTs,
Claim(s) 13-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20200044067 (Banerjee et al) in view of US 20080179694 (Nakazawa et al) and US 20160172474 (Miyake et al) as applied to claim 12 above, and further in view of US 9796780 (Yamamoto et al).
Concerning claim 13, Banerjee in view Nakazawa and Miyake discloses wherein the passivation layer comprises at least a first layer of a dielectric material (Banerjee [0030], note that the examiner is interpreting that the passivation layer is made of the disclosed tri-layer of silicon nitride/aluminum nitride/silicon nitride).
Banerjee in view Nakazawa and Miyake does not explicitly disclose that the passivation layer of a thickness that forms a p-dopant diffusion barrier. However, Yamamoto discloses that AlN is known in the art as a suitable diffusion barrier for Mg (claim 1). Banerjee discloses the use of Mg as one of the p-dopants used in the p-GaN mesa ([0040]). The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See MPEP 2144.07. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the passivation layer of Banerjee in view Nakazawa and Miyake which includes AlN as a Mg (p-dopant) barrier layer because of its known suitable use as disclosed by Yamamoto.
Continuing to claim 14, Banerjee in view Nakazawa, Miyake, and Yamamoto discloses wherein said first layer of the dielectric material comprises at least one of a layer of dielectric oxide and a layer of a dielectric nitride (Banerjee [0030]).
Considering to claim 15, Banerjee in view Nakazawa, Miyake, and Yamamoto discloses wherein the p-dopant is magnesium (Mg) (Banerjee [0040]) and said first layer of dielectric material is a Mg diffusion barrier (Yamamoto claim 1).
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20200044067 (Banerjee et al) in view US 20080179694 (Nakazawa et al), US 20160172474 (Miyake et al), and US 20050145865 (Okuyama et al).
Referring to claim 19, Banerjee discloses a method of fabrication for the GaN HEMT device structure defined in claim 12 comprising (Figs. 1-5): providing a substrate (102); growing an epitaxial layer stack grown on the substrate, the epitaxial layer stack comprising a buffer layer (104) and a GaN heterostructure comprising a GaN layer (106) and an overlying AlxGa1-xN barrier layer (108) to form a 2DEG channel region ([0024]-[0025] and [0028]). . ., forming a passivation layer (110) over the AlxGa1-xN barrier layer ([0030] and Fig. 1, selectively removing the passivation layer in a gate region (Fig. 2 and [0030]) to expose a surface of the AlxGa1-xN barrier layer (Fig. 2 [0030]), . . . providing p-GaN mesa (344) within the gate slot (Fig. 4) on the planar surface of the first thickness of the AlxGa1-xN barrier layer . . . to form a p-GaN mesa within the gate slot (Fig. 5 and [0041]), defining openings through the passivation layer to source and drain regions and providing source and drain electrodes (522 and 526) thereon (Fig. 5 and [0047]); and providing a gate electrode (Banerjee 444) on the p-GaN mesa (Banerjee Fig. 5 and [0043]).
Banerjee does not disclose the first thickness having a first Al%, and a second thickness that is directly on the first thickness with no intervening layer and has a second Al% greater than the first Al%, the second Al% being 25% or less , the gate slot extending through the passivation layer, through the second thickness of the AlxGa1-xN barrier layer into the first thickness of the AlxGa1-xN the gate slot having substantially vertical sidewalls and a bottom of the gate slot being a planar surface defined by a planar surface of the AlxGa1-xN such that a remaining part of the first thickness of the AlxGa1-xN barrier layer is between the bottom of the gate slot and the GaN layer. However, Nakazawa discloses forming a GaN based transistor ([0002]) that has a barrier layer configuration (104) where in the barrier layer has a first thickness (lower portion of layer 104) having a first Al% ([0053]), and a second thickness (upper portion of layer 104) . . . having a second Al%, greater than the first Al% the second Al% being 25% or less ([0053], it is noted that the Al composition in an AlGaN layer (second nitride semiconductor layer 104) may also be varied in the thickness direction. The second nitride semiconductor layer 104 may be formed such that the Al composition value gradually increases from the interface with the first nitride semiconductor layer 103 with approach toward the upper surface of the second nitride semiconductor layer 104. Otherwise, the second nitride semiconductor layer 104 may also obtained by stacking two or more semiconductor layers having different Al composition values ) and the gate slot (110a) having substantially vertical sidewalls and a bottom of the gate slot being a planar surface such that a remaining part of the first thickness of the AlxGa1-xN barrier layer is between the bottom of the gate slot and the GaN layer (Fig. 14), wherein the AlxGa1-xN barrier comprises the remaining part of the first thickness in the gate region underlying the p-GaN mesa in the gate slot and comprises said first and second thicknesses in access regions extending between the gate region and the source region and between the gate region and the drain region (Fig. 14, note that a portion of the barrier layer 104 remains under the gate 117 with the thicknesses of these layers). Nakazawa discloses that the configuration provides the advantage that the two-dimensional electron gas layer 109 is not affected by the depletion layer resulting from surface states irrespective of whether the FET is in the OFF state or in the ON state. This allows suppression of the occurrence of the current collapse. ([0059]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to form a first thickness having a first Al%, and a second thickness having a second Al%, greater than the first Al% the second Al% being 25% or less or the gate slot having substantially vertical sidewalls and a bottom of the gate slot being a planar surface defined by a first thickness of the AlxGa1-xN as disclosed by Nakazawa in order to suppress the occurrence of the current collapse.
Additionally, Miyake discloses a GaN transistor device (Fig. 20) in which and nitride stack is grown on a substrate (S), the stack comprising a buffer layer (BUF) a GaN heterostructure comprising a GaN layer (CH) ([0126] and [0153] note that the channel layer is made of the same materials for all the disclosed embodiments) and an overlying AlxGa1-xN barrier layer (BA1 and BA2) to form a 2DEG channel region (DEG) (Fig. 20), wherein the AlxGa1-xN barrier layer comprise a first thickness (BA1) and a second thickness (BA2) that is directly on the first thickness with no intervening layer and has a second Al%, greater than the first Al ([0165]) and discloses that such configuration reduces access resistance between the drain and the gate ([0165]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to form the AlxGa1-xN barrier layer such that it has a first thickness and second thickness formed directly on the first thickness with no intervening layers and a second Al% greater than the first Al% in order to reduce access resistance between the drain and the gate as disclosed by Miyake.
Further, Okuyama discloses using a selective growth process in order to deposit a p-GaN at a temperature of 900 ºC ([0186]) and that this process enables the growth of sufficiently Mg-doped and low resistant p-type GaN layer ([0186]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to form the p-GaN by a selective growth process such as the one disclosed by Okuyama in order to form a sufficiently Mg-doped and low resistant p-type GaN layer.
Claim(s) 20-22 and 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20200044067 (Banerjee et al) in view of US 20080179694 (Nakazawa et al), US 20160172474 (Miyake et al), and US 20050145865 (Okuyama et al) as applied to claim 19 above, and further in view of US 10269947 (Moens et al).
Regarding claims 20-22, Banerjee in view Nakazawa, Miyake, and Okuyama discloses . . .wherein the first Al% is in the range from 15% to 18% and the first thickness of the AlxGa1-xN barrier layer is in the range 15 nm to 20 nm (Miyake [0153]). . . and the second Al% is in the range from 20% to 25% and the second thickness of the AlxGa1-xN barrier layer is in the range from 5nm to 10nm (Miyake [0153]).
Banerjee in view Nakazawa, Miyake, and Okuyama does not disclose that the thicknesses are to provide a specified threshold voltage for E-mode operation, to provide a specified Rdson and dynamic Rdson of the GaN HEMT or to provides a specified threshold voltage of at least 0.9 V for E-mode operation, wherein the first Al% and the first thickness of the AlxGa1-xN barrier layer provide a specified threshold voltage for E-mode operation, and the second Al% and the second thickness of the AlxGa1-xN barrier layer provide a specified Rdson and dynamic Rdson of the GaN HEMT device structure, or wherein the first Al% and the first thickness of the AlxGay-xN barrier layer provides a specified threshold voltage of in a range of 1.3V to 1.6 V for E- mode operation. However, Moens discloses forming an enhancement-mode high electron mobility transistor (HEMT) that can have a threshold voltage greater than 1 V and allow for better control of the HEMT as compared to conventional enhancement-mode HEMTs. The HEMT can have an on-state resistance (Rpson) that is similar to a depletion- mode HEMT having an unintentionally doped GaN channel layer and an AlGaN barrier layer overlying the channel layer and similar source-to-gate and gate-to-drain lengths (col. 2 lines 48- 56, col. 6 lines 27-35, and col. 8 lines 46-54). Therefore one of ordinary skill in the art before the effective filing date of the invention would have found it obvious to incorporate the teachings of Moens with respect to the AlxGa1-xN formed in the invention of Banerjee in view Nakazawa, Miyake, and Okuyama in order to allow for better control of the HEMT as compared to conventional enhancement-mode HEMTs,
Claim(s) 23- 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20200044067 (Banerjee et al) in view of US 20080179694 (Nakazawa et al), US 20160172474 (Miyake et al), and US 20050145865 (Okuyama et al) as applied to claim 19 above, and further in view of US 9796780 (Yamamoto et al).
Concerning claim 23, Banerjee in view Nakazawa, Miyake, and Okuyama discloses where providing the passivation layer comprises providing at least a first layer of a dielectric material of a thickness (Banerjee [0030], note that the examiner is interpreting that the passivation layer is made of the disclosed tri-layer of silicon nitride/aluminum nitride/silicon nitride) . . . , and wherein selectively providing a p-GaN mesa in the gate slot comprises selective area growth of p-GaN within the gate slot, using a low temperature growth process at a temperature below 950C (Okuyama [0186]).
Banerjee in view Nakazawa, Miyake, and Okuyama does not explicitly disclose that the passivation layer of a thickness that forms a p-dopant diffusion barrier. However, Yamamoto discloses that AlN is known in the art as a suitable diffusion barrier for Mg (claim 1). Banerjee discloses the use of Mg as one of the p-dopants used in the p-GaN mesa ([0040]). The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See MPEP 2144.07. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the passivation layer of Banerjee in view Nakazawa, Miyake, and Okuyama which includes AlN as a Mg (p-dopant) barrier layer because of its known suitable use as disclosed by Yamamoto.
Continuing to claim 24, Banerjee in view Nakazawa, Miyake, and Okuyama discloses wherein the passivation layer comprises at least a first layer of a dielectric material (Banerjee [0030], note that the examiner is interpreting that the passivation layer is made of the disclosed tri-layer of silicon nitride/aluminum nitride/silicon nitride).
Banerjee in view Nakazawa, Miyake, and Okuyama does not explicitly disclose that the passivation layer forms a p-dopant diffusion barrier. However, Yamamoto discloses that AlN is known in the art as a suitable diffusion barrier for Mg (claim 1). Banerjee discloses the use of Mg as one of the p-dopants used in the p-GaN mesa ([0040]). The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See MPEP 2144.07. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the passivation layer of Banerjee in view Nakazawa, Miyake, and Okuyama and Okuyama which includes AlN as a Mg (p-dopant) barrier layer because of its known suitable use as disclosed by Yamamoto.
Considering claim 25, Banerjee in view Nakazawa, Miyake, Okuyama, and Yamamoto discloses wherein said first layer of the dielectric material comprises at least one of a layer of dielectric oxide and a layer of a dielectric nitride (Banerjee [0030]).
Referring to claim 26, Banerjee in view Nakazawa, Miyake, Okuyama, and Yamamoto discloses wherein the p-dopant is magnesium (Mg) (Banerjee [0040]) and said first layer of dielectric material is a Mg diffusion barrier (Yamamoto claim 1).
Regarding claims 27 and 28 (with these claims being similar in scope), Banerjee in view Nakazawa, Miyake, and Okuyama disclose forming a p-GaN (Banerjee [0040]) and a passivation layer over the AlxGa1-xN (Banerjee [0030], note that the examiner is interpreting the passivation is the disclosed tri-layer of silicon nitride/aluminum nitride/silicon nitride).
Banerjee in view Nakazawa, Miyake, and Okuyama does not explicitly disclose wherein an out-diffused p-dopant content in the access regions of the AlxGa1-xN barrier layer, said access regions extending between the gate region and the source region and between the gate region and the drain region, is less than an out-diffused p-dopant content in the gate region of the AlxGa1-xN barrier layer. However, Yamamoto discloses that AlN is known in the art as a suitable diffusion barrier for Mg (claim 1). Banerjee discloses the use of Mg as one of the p-dopants used in the p-GaN mesa ([0040]). The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See MPEP 2144.07. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the passivation layer of Banerjee in view Nakazawa, Miyake, and Okuyama which includes AlN as a Mg (p-dopant) barrier layer because of its known suitable use as disclosed by Yamamoto. Thus the p-dopant diffusion barrier is formed over the access regions and not over the gate slot region and therefore the examiner is interpreting that the out-diffusion in the region without the p-dopant diffusion barrier would be higher than the region that contains the p-dopant diffusion barrier.
Response to Arguments
Applicant’s arguments, see pages 7-14, filed 01/22/26, with respect to the rejection(s) of claim(s) 12 and 19 under 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of US 20080179694 (Nakazawa et al) and US 20160172474 (Miyake et al).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VALERIE N NEWTON whose telephone number is (571)270-5015. The examiner can normally be reached M-F 8-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD DICKE can be reached on (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/VALERIE N NEWTON/Examiner, Art Unit 2897 03/06/26
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897