DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are not found persuasive.
Applicant argues on pages 6-7, reiterating that Examiner’s position that the proposed rejection does not need to concern itself with the recited feature of “a fourth semiconductor die with a data transfer date less than the first semiconductor die” of claim 1, 8, and 15 because “apparatus claims cover what a device is, not what a device does, therefore the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus,” citing MPEP2114(ii).
Applicant repeats previous remarks, particularly, that citing MPEP 2114 is in error since claim 1 is to a method claim that can clearly recite steps that need to be addressed by the office action, and this section of the MPEP is clear that “an apparatus may be recited…functionally” and in order to ignore functional recitations, the office action must illustrate that the prior art discloses “all of the structural limitations of the claim.”
To this point, again, Examiner takes the position that the prior art apparatus has shown the structural limitations of the claim. Examiner has shown how the structure has been taught by the prior art since the apparatus can be recited in the claim either structurally or functionally (MPEP 2114(i)); and since apparatus claims cover what a device is, not what a device does (MPEP 2114(ii)), the recitation of the claim “with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus.”
To prove Examiner’s point, the claimed method could possibly be indefinite, and further introduce new matter with Applicant’s interpretation. Since there is no data transfer between the claimed dies of claims 1, 8, and 15 during the manufacturing process, since power, ground, and control signals are not provided to the dies while the package is being assembled and encapsulated, all the transfer rates of all the dies would be the same. Therefore, if the claim requires the functional limitations to be present, if the present claims were patented, the claims would only cover the process where data transfer is happening during the manufacturing steps, which is nearly impossible and is not supported in the originally filed specification.
Applicant argues on page 8 that MPEP 2114 does not apply to claim 1 because claim 1 is not an apparatus claim, and all the recited method steps should be considered in the rejection.
Examiner respectfully disagrees. Each of the dies recited in the claims is a device and adds structural context to the method claim. Since the claim functional limitations are directed to the structural and functional aspect of the device, MPEP 2114 is appliable to this method claim.
The above remarks are applicable to the arguments set forward by Applicant for claims 8 and 15. Applicant is invited to request an Examiner interview if further discussion is desired.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7, and 15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Marimuthu et al. (US PGPub 2010/0133704; hereinafter “Marimuthu”) in view of Pagaila et al. (US PGPub 2011/0068478; hereinafter “Pagaila”).
Re claim 1: Marimuthu teaches (e.g. fig. 9i) a method comprising: electrically connecting a first semiconductor die (542; e.g. paragraph 83) to first through vias (514 within die 506; hereinafter “1TV”) extending through a second semiconductor die (die 506; e.g. paragraph 78), the second semiconductor die (506) being encapsulated (518) with a third semiconductor die (502) by an encapsulant (518), the encapsulant (518) comprising a single material in physical contact with multiple sides of the second semiconductor die (506) and multiple sides of the third semiconductor die (502); and electrically connecting the second semiconductor die (506) and the third semiconductor die (502) to an overlying package (560); wherein the overlying package (560) comprises a fourth semiconductor die (bottom-most die of 560; hereinafter “4SD”) with a data transfer rate (apparatus claims cover what a device is, not what a device does, therefore a manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus, see MPEP 2114(ii)) less than the first semiconductor die (542).
Marimuthu is silent as to explicitly teaching electrically connecting the second semiconductor die and the third semiconductor die to an overlying package with second through vias extending through and in physical contact with the encapsulant.
Pagaila teaches (e.g. fig. 2) electrically connecting the second semiconductor die (506 of Marimuthu) and the third semiconductor die (502 of Marimuthu) to an overlying package (560 of Marimuthu which is equivalent to 200 of Pagaila) with second through vias (226) extending through and in physical contact with the encapsulant (210).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the signal routing structure between packages as taught by Pagaila in the device of Marimuthu in order to have the predictable result of using an alternate method of routing which does not require through silicon vias in the first semiconductor dies so that robustness of using available dies which do not have through silicon vias can also be utilized in the overall device.
Re claim 2: Marimuthu teaches the method of claim 1, further comprising bonding a fifth semiconductor die (534) over the third semiconductor die (502).
Re claim 3: Marimuthu in view of Pagaila teaches the method of claim 2, wherein the third semiconductor die (502) does not have through vias (vias 532 are not separate from 1TV and is connected) separate from the first through vias (1TV) and the second through vias (226 of Pagaila) extending through the third semiconductor die (502).
Re claim 4: Marimuthu teaches the method of claim 3, wherein a sixth semiconductive die (chip within 560 above 4SD; hereinafter “6SD”) is bonded to the first semiconductor die (542).
Re claim 5: Marimuthu teaches the method of claim 1, wherein a fifth semiconductive die (chip within 560 above 4SD; hereinafter “5SD”) is bonded to the first semiconductor die (542).
Re claim 6: Marimuthu teaches the method of claim 1, wherein the third semiconductor die (502) is formed with a different technology node (506 are dummy dies and devices thereon are not the same node technology as ICs in 502; e.g. paragraph 78) than the second semiconductor die (506).
Re claim 7: Marimuthu teaches the method of claim 1, wherein the third semiconductor die (502) is formed with a same technology node (502 and 506 has vias formed with the same spacing as contacts for 534 so the electrical contacts are formed using the same node technology) as the second semiconductor die (506).
Re claim 15: Marimuthu teaches (e.g. figs. 9f-9i) a method comprising: plating a conductive material (522) onto a seed layer (514) over an encapsulant (518, 554), wherein immediately after the plating the conductive material (522) electrically interconnects a first semiconductor die (506), a second semiconductor die (534), and a first through via (left 514 in 506; hereinafter “1TV”), the first through via (1TV) having a height at least as large as the first semiconductor die (506); and sandwiching a third semiconductor die (542) between the first semiconductor die (506) and a packaging substrate (564), the third semiconductor die (542) being electrically connected to a second through via (right 514 in 506; hereinafter “2TV”) extending through the first semiconductor die (506), wherein a third semiconductor die (lowest chip within 560; hereinafter “3SD”) attached to the packaging substrate (564) has a data transfer rate less than (apparatus claims cover what a device is, not what a device does, therefore a manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus, see MPEP 2114(ii)) the first semiconductor die (506).
It may be considered that Marimuthu is silent as to explicitly teaching the first through via having a height at least as large as the first semiconductor die.
Pagaila teaches (e.g. fig. 2) teaching the first through via (226) having a height at least as large as the first semiconductor die (208).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the signal routing structure between packages having vias and solder balls as taught by Pagaila in the device of Marimuthu in order to have the predictable result of using an alternate method of routing which does not require through silicon vias in the first semiconductor dies so that robustness of using available dies which do not have through silicon vias can also be utilized in the overall device.
Re claim 16: Marimuthu teaches the method of claim 15, wherein the second semiconductor die (534) is free from vias separate from the first through via (1TV of Marimuthu or 32 of Pagaila) and the second through via (2TV of Marimuthu).
Re claim 17: Marimuthu teaches the method of claim 15, further comprising attaching a fourth semiconductor die (second from bottom-most chip in 560; hereinafter “4SD”) over the second semiconductor die (534).
Re claim 18: Marimuthu teaches the method of claim 15, further comprising a fourth semiconductor die (second from bottom-most chip in 560; hereinafter “4SD”) and a fifth semiconductor die (top-most chip in 560; hereinafter “5SD”) bonded to the packaging substrate (564).
Re claim 19: Marimuthu teaches the method of claim 18, wherein the third semiconductor die (3SD of Marimuthu) is a wide I/0 RAM (memory, memory chips; e.g. paragraphs 38, 43, 85), the fourth semiconductor die (4SD) is a LPDDR memory device (memory, memory chips; e.g. paragraphs 38, 43, 85), and the fifth semiconductor die (5SD) is a NAND flash memory device (memory, memory chips; e.g. paragraphs 38, 43, 85).
Re claim 20: Marimuthu teaches the method of claim 15. wherein the first semiconductor die (506) is a memory control unit (controller; e.g. paragraph 38) for the third semiconductor die (3SD).
Claim(s) 8-10, and 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Marimuthu et al. (US PGPub 2010/0133704; hereinafter “Marimuthu”) in view of Weng et al. (US PGPub 2011/0117700; hereinafter “Weng”).
Re claim 8: Marimuthu teaches a method comprising: encapsulating a first semiconductor device (506) and a second semiconductor device (502) in an encapsulant (518), the first semiconductor device (506) and the second semiconductor device (502) both comprising active devices (dies 102, 104, 106 may include semiconductor devices and ICs, in some embodiments 104 and 106 may be dummy dies; e.g. paragraph 38; this teaching shows that 506 is disclosed as being an active IC chip); after the encapsulating, connecting the first semiconductor device (506) and the second semiconductor device (502) with a first redistribution layer (522) on a first side (bottom side of 506) of the first semiconductor device (506); after the connecting, bonding a third semiconductor device (542) to the first semiconductor device (506), wherein after the bonding the third semiconductor device (542) is electrically connected to the second semiconductor device (502) using through vias (514) that extend through the first semiconductor device (506); and after the bonding the third semiconductor device (542), bonding a fourth semiconductor device (560) with a solder material (562) to through vias (514 within 504); wherein after the bonding the fourth semiconductor device (4SD) the third semiconductor device (534) is located between the first semiconductor device (506) and the fourth semiconductor device (4SD), and wherein a semiconductor die (middle chip in 560; hereinafter “4SD”) within the fourth semiconductor device (560) has a data transfer rate (apparatus claims cover what a device is, not what a device does, therefore a manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus, see MPEP 2114(ii)) less than the third semiconductor device (534).
Marimuthu is silent as to explicitly teaching bonding a fourth semiconductor device with a solder material to through vias extending through the encapsulant, wherein the solder material has a height that is greater than a height of the third semiconductor device.
Weng teaches (e.g. fig. 5) bonding a fourth semiconductor device (4SD of Marimuthu/516 of Weng) with a solder material (528a-d) to through vias (218a-d) extending through the encapsulant (224), wherein the solder material (528a-d) has a height that is greater than a height of the third semiconductor device (208).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the signal routing structure between packages having vias and solder balls as taught by Weng in the device of Marimuthu in order to have the predictable result of using an alternate method of routing which does not require through silicon vias in the first semiconductor dies so that robustness of using available dies which do not have through silicon vias can also be utilized in the overall device.
Re claim 9: Marimuthu in view of Weng teaches the method of claim 8, further comprising electrically connecting a fifth semiconductor device (top-most chip in 560 of Marimuthu; hereinafter “5SD”) to the through vias (528a-d of Weng), wherein after the electrically connecting the fifth semiconductor device (5SD), the fourth semiconductor device (4SD) is located between the fifth semiconductor device (5SD) and the first semiconductor device (502).
Re claim 10: Marimuthu teaches the method of claim 9, wherein the electrically connecting the fifth semiconductor device (5SD of Marimuthu) is performed at least in part with a wire bonding process (wirebonds as shown in fig. 9i of Marimuthu).
Re claim 13: Marimuthu teaches the method of claim 8, wherein the second semiconductor device (506) is a digital logic device (dies 102, 104, 106 (which correspond to 502, 504, 506) may include semiconductor devices which provide various functions such as memory, controller, ASICs, processor, microcontroller, or combinations thereof; e.g. paragraph 38).
Re claim 14: Marimuthu teaches the method of claim 8, wherein the first semiconductor device (502) comprises a digital region and an analog region (dies 102, 104, 106 (which correspond to 540, 502) may include semiconductor devices which provide various functions such as memory, controller, ASICs, processor, microcontroller, or combinations thereof; e.g. paragraph 38; DACs and ADCs are elements within processors and microcontrollers).
Claim(s) 11, 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Marimuthu et al. (US PGPub 2010/0133704; hereinafter “Marimuthu”) in view of Weng, as applied to claim 8, and further in view of Lin et al. (US PGPub 2010/0140779; hereinafter “Lin”).
Re claim 11: Marimuthu teaches substantially the entire method as recited in claim 8 except explicitly teaching the method wherein the second semiconductor device (506) is free from through vias.
Lin teaches (e.g. fig. 6) the second semiconductor device (432) is free from through vias.
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the signal routing structure using a chip without TSVs as taught by Lin in the device of Marimuthu in order to have the predictable result of routing signals as needed in an application which does not require TSVs.
Re claim 12: Marimuthu teaches the method of claim 11, further comprising bonding a fifth semiconductor device (top-most chip in 560; hereinafter “5SD”) over the second semiconductor device (534).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JESSE Y MIYOSHI whose telephone number is (571)270-1629. The examiner can normally be reached M-F, 8:30AM-5:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached on 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898