DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Reopening of Prosecution
In view of the arguments of the pre-appeal conference request filed on 6/16/2026, PROSECUTION IS HEREBY REOPENED. A new ground of rejection is set forth below.
To avoid abandonment of the application, appellant must exercise one of the following two options:
(1) file a reply under 37 CFR 1.111 (if this Office action is non-final) or a reply under 37 CFR 1.113 (if this Office action is final); or,
(2) initiate a new appeal by filing a notice of appeal under 37 CFR 41.31 followed by an appeal brief under 37 CFR 41.37. The previously paid notice of appeal fee and appeal brief fee can be applied to the new appeal. If, however, the appeal fees set forth in 37 CFR 41.20 have been increased since they were previously paid, then appellant must pay the difference between the increased fees and the amount previously paid.
A Supervisory Patent Examiner (SPE) has approved of reopening prosecution by signing below:
/JESSICA S MANNO/SPE, Art Unit 2898
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot in view of new grounds of rejection.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The specification lacks written description as to how claim 1 generically claims “a method” which recites limitations to both a method of making a semiconductor device and a method of operating the device since the last portion of the claim recites “a fourth semiconductor die with a data transfer rate less than the first semiconductor die.” The specification lacks written description as to how one would make and use the device at the same time, since this would require providing power, ground, and operating signals to the devices working at different transfer rates while simultaneously manufacturing the packaged device.
Claims 8 and 15 recite identical limitations and would have the same issues of lack of written description as claim 1.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, and the dependent claims which inherit the same issues, is indefinite since the claim generically is to “a method” and it is unclear as to whether is to a method of making a semiconductor device or to a method of operating a device since the last portion of the claim recites “a fourth semiconductor die with a data transfer rate less than the first semiconductor die.” If this claim is to both method of making and method of operating, it is unclear how the device would be able to be operated while making the device. If the claim is to the method of making the device, then the method of operating the device would not be given patentable weight. If the claim is to the method of operating the device, then the method of making the device would not be given patentable weight.
Claims 8 and 15 recite identical limitations and would have the same indefiniteness issues as claim 1. For examination purposes, both types of methods are being considered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7, and 15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Marimuthu et al. (US PGPub 2010/0133704; hereinafter “Marimuthu”) in view of Pagaila et al. (US PGPub 2011/0068478; hereinafter “Pagaila”) and Akiba et al. (US PGPub 2008/0006947; hereinafter “Akiba”).
Re claim 1: Marimuthu teaches (e.g. fig. 9i) a method comprising: electrically connecting a first semiconductor die (542; e.g. paragraph 83) to first through vias (514 within die 506; hereinafter “1TV”) extending through a second semiconductor die (die 506/106 function as memory dies; e.g. paragraphs 38 and 78), the second semiconductor die (506) being encapsulated (518) with a third semiconductor die (502) by an encapsulant (518), the encapsulant (518) comprising a single material in physical contact with multiple sides of the second semiconductor die (506) and multiple sides of the third semiconductor die (502); and electrically connecting the second semiconductor die (506) and the third semiconductor die (502) to an overlying package (package 560 provided with processors; e.g. paragraph 85); wherein the overlying package (560) comprises a fourth semiconductor die (bottom-most die of 560; hereinafter “4SD”) with a data transfer rate (apparatus claims cover what a device is, not what a device does, therefore a manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus, see MPEP 2114(ii); further since the structure of the method is substantially identical to that of the claims, claimed functions are presumed to be present, see MPEP 2112.01(i)) less than the first semiconductor die (542).
Marimuthu is silent as to explicitly teaching electrically connecting the second semiconductor die and the third semiconductor die to an overlying package with second through vias extending through and in physical contact with the encapsulant.
Pagaila teaches (e.g. fig. 2) electrically connecting the second semiconductor die (506 of Marimuthu) and the third semiconductor die (502 of Marimuthu) to an overlying package (560 of Marimuthu which is equivalent to 200 of Pagaila) with second through vias (226) extending through and in physical contact with the encapsulant (210).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the signal routing structure between packages as taught by Pagaila in the device of Marimuthu in order to have the predictable result of using an alternate method of routing which does not require through silicon vias in the first semiconductor dies so that robustness of using available dies which do not have through silicon vias can also be utilized in the overall device.
It may be considered that Marimuthu in view of Pagaila is is silent as to explicitly teaching the overlying package comprises a fourth semiconductor die with a data transfer rate less than the first semiconductor die.
Akiba teaches (e.g. fig. 11) the overlying package (microcomputer chip 45 of package 1 of Akiba; e.g. paragraph 102; 560 of Marimuthu) comprises a fourth semiconductor die (45 of Akiba/4SD of Marimuthu) with a data transfer rate less (microcomputer chip 45 does not require such a high-speed processing as required by high-speed memory chips 2, 6 does which has twice the transfer rate; e.g. paragraph 85, 94 and 97 of Akiba) than the first semiconductor die (memory chips 2, 6 of Akiba; e.g. paragraph 85; 542 of Marimuthu)
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the slower transfer of the microcomputer when compared to the high speed memory chips as taught by Akiba in the device of Marimuthu in view of Pagaila in order to have the predictable result of using a faster memory chip with faster transfer rates so that overall device performance speed can be improved.
Re claim 2: Marimuthu teaches the method of claim 1, further comprising bonding a fifth semiconductor die (534) over the third semiconductor die (502).
Re claim 3: Marimuthu in view of Pagaila teaches the method of claim 2, wherein the third semiconductor die (502) does not have through vias (vias 532 are not separate from 1TV and is connected) separate from the first through vias (1TV) and the second through vias (226 of Pagaila) extending through the third semiconductor die (502).
Re claim 4: Marimuthu teaches the method of claim 3, wherein a sixth semiconductive die (chip within 560 above 4SD; hereinafter “6SD”) is bonded to the first semiconductor die (542).
Re claim 5: Marimuthu teaches the method of claim 1, wherein a fifth semiconductive die (chip within 560 above 4SD; hereinafter “5SD”) is bonded to the first semiconductor die (542).
Re claim 6: Marimuthu teaches the method of claim 1, wherein the third semiconductor die (502) is formed with a different technology node (506 are dummy dies and devices thereon are not the same node technology as ICs in 502; e.g. paragraph 78) than the second semiconductor die (506).
Re claim 7: Marimuthu teaches the method of claim 1, wherein the third semiconductor die (502) is formed with a same technology node (502 and 506 has vias formed with the same spacing as contacts for 534 so the electrical contacts are formed using the same node technology) as the second semiconductor die (506).
Re claim 15: Marimuthu teaches (e.g. figs. 9f-9i) a method comprising: plating a conductive material (522) onto a seed layer (514) over an encapsulant (518, 554), wherein immediately after the plating the conductive material (522) electrically interconnects a first semiconductor die (die 506/106 function as memory dies; e.g. paragraphs 38 and 78), a second semiconductor die (534), and a first through via (left 514 in 506; hereinafter “1TV”), the first through via (1TV) having a height at least as large as the first semiconductor die (506); and sandwiching a third semiconductor die (542) between the first semiconductor die (506) and a packaging substrate (564), the third semiconductor die (542) being electrically connected to a second through via (right 514 in 506; hereinafter “2TV”) extending through the first semiconductor die (506), wherein a third semiconductor die (lowest chip within 560 provided with processors; e.g. paragraph 85; e.g. paragraph 85; hereinafter “3SD”) attached to the packaging substrate (564) has a data transfer rate less than (apparatus claims cover what a device is, not what a device does, therefore a manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus, see MPEP 2114(ii); further since the structure of the method is substantially identical to that of the claims, claimed functions are presumed to be present, see MPEP 2112.01(i)) the first semiconductor die (506).
It may be considered that Marimuthu is silent as to explicitly teaching the first through via having a height at least as large as the first semiconductor die.
Pagaila teaches (e.g. fig. 2) teaching the first through via (226) having a height at least as large as the first semiconductor die (208).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the signal routing structure between packages having vias and solder balls as taught by Pagaila in the device of Marimuthu in order to have the predictable result of using an alternate method of routing which does not require through silicon vias in the first semiconductor dies so that robustness of using available dies which do not have through silicon vias can also be utilized in the overall device.
It may be considered that Marimuthu in view of Pagaila is is silent as to explicitly teaching the overlying package comprises a fourth semiconductor die with a data transfer rate less than the first semiconductor die.
Akiba teaches (e.g. fig. 11) the overlying package (microcomputer chip 45 of package 1 of Akiba; e.g. paragraph 102; 560 of Marimuthu) comprises a fourth semiconductor die (45 of Akiba/4SD of Marimuthu) with a data transfer rate less (microcomputer chip 45 does not require such a high-speed processing as required by high-speed memory chips 2, 6 does which has twice the transfer rate; e.g. paragraph 85, 94 and 97 of Akiba) than the first semiconductor die (memory chips 2, 6 of Akiba; e.g. paragraph 85; 542 of Marimuthu)
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the slower transfer of the microcomputer when compared to the high speed memory chips as taught by Akiba in the device of Marimuthu in view of Pagaila in order to have the predictable result of using a faster memory chip with faster transfer rates so that overall device performance speed can be improved.
Re claim 16: Marimuthu teaches the method of claim 15, wherein the second semiconductor die (534) is free from vias separate from the first through via (1TV of Marimuthu or 32 of Pagaila) and the second through via (2TV of Marimuthu).
Re claim 17: Marimuthu teaches the method of claim 15, further comprising attaching a fourth semiconductor die (second from bottom-most chip in 560; hereinafter “4SD”) over the second semiconductor die (534).
Re claim 18: Marimuthu teaches the method of claim 15, further comprising a fourth semiconductor die (second from bottom-most chip in 560; hereinafter “4SD”) and a fifth semiconductor die (top-most chip in 560; hereinafter “5SD”) bonded to the packaging substrate (564).
Re claim 19: Marimuthu teaches the method of claim 18, wherein the third semiconductor die (3SD of Marimuthu) is a wide I/0 RAM (memory, memory chips; e.g. paragraphs 38, 43, 85), the fourth semiconductor die (4SD) is a LPDDR memory device (memory, memory chips; e.g. paragraphs 38, 43, 85), and the fifth semiconductor die (5SD) is a NAND flash memory device (memory, memory chips; e.g. paragraphs 38, 43, 85).
Re claim 20: Marimuthu teaches the method of claim 15. wherein the first semiconductor die (506) is a memory control unit (controller; e.g. paragraph 38) for the third semiconductor die (3SD).
Claim(s) 8-10, and 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Marimuthu et al. (US PGPub 2010/0133704; hereinafter “Marimuthu”) in view of Weng et al. (US PGPub 2011/0117700; hereinafter “Weng”). and Akiba et al. (US PGPub 2008/0006947; hereinafter “Akiba”)
Re claim 8: Marimuthu teaches a method comprising: encapsulating a first semiconductor device (die 506/106 function as memory dies; e.g. paragraphs 38 and 78) and a second semiconductor device (502) in an encapsulant (518), the first semiconductor device (506) and the second semiconductor device (502) both comprising active devices (dies 102, 104, 106 may include semiconductor devices and ICs, in some embodiments 104 and 106 may be dummy dies; e.g. paragraph 38; this teaching shows that 506 is disclosed as being an active IC chip); after the encapsulating, connecting the first semiconductor device (506) and the second semiconductor device (502) with a first redistribution layer (522) on a first side (bottom side of 506) of the first semiconductor device (506); after the connecting, bonding a third semiconductor device (542) to the first semiconductor device (506), wherein after the bonding the third semiconductor device (542) is electrically connected to the second semiconductor device (502) using through vias (514) that extend through the first semiconductor device (506); and after the bonding the third semiconductor device (542), bonding a fourth semiconductor device (package 560 provided with processors; e.g. paragraph 85) with a solder material (562) to through vias (514 within 504); wherein after the bonding the fourth semiconductor device (4SD) the third semiconductor device (534) is located between the first semiconductor device (506) and the fourth semiconductor device (4SD), and wherein a semiconductor die (middle chip in 560; hereinafter “4SD”) within the fourth semiconductor device (560) has a data transfer rate (apparatus claims cover what a device is, not what a device does, therefore a manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus, see MPEP 2114(ii); further since the structure of the method is substantially identical to that of the claims, claimed functions are presumed to be present, see MPEP 2112.01(i)) less than the third semiconductor device (534).
Marimuthu is silent as to explicitly teaching bonding a fourth semiconductor device with a solder material to through vias extending through the encapsulant, wherein the solder material has a height that is greater than a height of the third semiconductor device.
Weng teaches (e.g. fig. 5) bonding a fourth semiconductor device (4SD of Marimuthu/516 of Weng) with a solder material (528a-d) to through vias (218a-d) extending through the encapsulant (224), wherein the solder material (528a-d) has a height that is greater than a height of the third semiconductor device (208).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the signal routing structure between packages having vias and solder balls as taught by Weng in the device of Marimuthu in order to have the predictable result of using an alternate method of routing which does not require through silicon vias in the first semiconductor dies so that robustness of using available dies which do not have through silicon vias can also be utilized in the overall device.
It may be considered that Marimuthu in view of Weng is silent as to explicitly teaching the overlying package comprises a fourth semiconductor die with a data transfer rate less than the first semiconductor die.
Akiba teaches (e.g. fig. 11) the overlying package (microcomputer chip 45 of package 1 of Akiba; e.g. paragraph 102; 560 of Marimuthu) comprises a fourth semiconductor die (45 of Akiba/4SD of Marimuthu) with a data transfer rate less (microcomputer chip 45 does not require such a high-speed processing as required by high-speed memory chips 2, 6 does which has twice the transfer rate; e.g. paragraph 85, 94 and 97 of Akiba) than the first semiconductor die (memory chips 2, 6 of Akiba; e.g. paragraph 85; 542 of Marimuthu)
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the slower transfer of the microcomputer when compared to the high speed memory chips as taught by Akiba in the device of Marimuthu in view of Pagaila in order to have the predictable result of using a faster memory chip with faster transfer rates so that overall device performance speed can be improved.
Re claim 9: Marimuthu in view of Weng and Akiba teaches the method of claim 8, further comprising electrically connecting a fifth semiconductor device (top-most chip in 560 of Marimuthu; hereinafter “5SD”) to the through vias (528a-d of Weng), wherein after the electrically connecting the fifth semiconductor device (5SD), the fourth semiconductor device (4SD) is located between the fifth semiconductor device (5SD) and the first semiconductor device (502).
Re claim 10: Marimuthu teaches the method of claim 9, wherein the electrically connecting the fifth semiconductor device (5SD of Marimuthu) is performed at least in part with a wire bonding process (wirebonds as shown in fig. 9i of Marimuthu).
Re claim 13: Marimuthu teaches the method of claim 8, wherein the second semiconductor device (506) is a digital logic device (dies 102, 104, 106 (which correspond to 502, 504, 506) may include semiconductor devices which provide various functions such as memory, controller, ASICs, processor, microcontroller, or combinations thereof; e.g. paragraph 38).
Re claim 14: Marimuthu teaches the method of claim 8, wherein the first semiconductor device (502) comprises a digital region and an analog region (dies 102, 104, 106 (which correspond to 540, 502) may include semiconductor devices which provide various functions such as memory, controller, ASICs, processor, microcontroller, or combinations thereof; e.g. paragraph 38; DACs and ADCs are elements within processors and microcontrollers).
Claim(s) 11, 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Marimuthu et al. (US PGPub 2010/0133704; hereinafter “Marimuthu”) in view of Weng and Akiba, as applied to claim 8, and further in view of Lin et al. (US PGPub 2010/0140779; hereinafter “Lin”).
Re claim 11: Marimuthu teaches substantially the entire method as recited in claim 8 except explicitly teaching the method wherein the second semiconductor device (506) is free from through vias.
Lin teaches (e.g. fig. 6) the second semiconductor device (432) is free from through vias.
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the signal routing structure using a chip without TSVs as taught by Lin in the device of Marimuthu in order to have the predictable result of routing signals as needed in an application which does not require TSVs.
Re claim 12: Marimuthu teaches the method of claim 11, further comprising bonding a fifth semiconductor device (top-most chip in 560; hereinafter “5SD”) over the second semiconductor device (534).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JESSE Y MIYOSHI whose telephone number is (571)270-1629. The examiner can normally be reached M-F, 8:30AM-5:00PM.
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/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898
Prosecution Insights