Attorney’s Docket Number: 103585-US-PA
Filing Date: 4/12/2021
Inventors: Chen et al.
Examiner: Marcos D. Pizarro
DETAILED ACTION
This Office action responds to the amendment filed on 6/11/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination (RCE) under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after the final rejection in paper no. 16, mailed on 3/13/2026. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 6/11/2026 has been entered.
Amendment Status
The RCE submission filed on 6/11/2026 as an amendment in reply to the Office action in paper no. 16 has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1 and 3-21.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 4, 5, 16, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Huo (US 2017/0047340) in view of Lee (NPL).
Regarding claim 1, Huo (see, e.g., figs. 10-11) shows most aspects of the instant invention including a memory device comprising:
A substrate 1
A stacked structure on the substrate and comprising a plurality of alternating insulating and conductive 6B layers
A hole 2TP in the stacked structure
A channel layer 5 in the hole and comprising a first part comprising poly-Si and a second part formed on the first part and comprising Si
A charge storage structure (CT) 6A between the first part and the conductive layers
wherein the first part is sandwiched between the CT and the second part, and the second part is isolated from the CT by the first part.
Regarding claim 1, Huo (fig. 11,¶0041) shows that the channel layer 5 is a poly-Si layer. A portion of the channel layer corresponds to the claimed first part, while another portion corresponds to the claimed second part. Huo, however, fails to show that the second part comprises epitaxial Si. Lee, in a similar device to Huo, teaches that a channel layer comprising an epi-Si formed on a poly-Si contributes to improving the device performance. See Lee: p.H780/col.1/ll.32-35.
It would have been obvious at the time of filing the invention to have the first and second parts of Huo comprising the poly-Si and epi-Si layers of Lee to improve the performance of the device.
Regarding claim 4, Huo (see, e.g., fig. 11) shows that the CT 6A is between the insulating 2B and conductive 6B layers.
Regarding claim 5, Huo (fig.10, ¶0041) shows the device further comprising a filling layer in the hole 2TP and covering a sidewall of the second part.
Regarding claim 16, Huo (figs. 10-11) shows that the sidewalls of the second part are only in contact with the filling layer 2TPand the first part.
Regarding claim 19, Lee shows that the first and second part have an interface. See Lee: p.H779/col.2/l.23.
Regarding claim 20, Lee shows that the second part is formed by hot-wire CVD using SiH4 in Ar at a temperature of 400-450°C and under a pressure of 1x10-2 to 1 Torr. See Lee: p.H779/col.1/ll.1-10.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Huo/Lee in view of Sharangpani (US 2017/0373079).
Regarding claim 3, Huo/Lee shows most aspects of the instant invention (see paragraphs 7-9 above), except for showing that the thickness of the second part is 75-95% the overall thickness of the channel layer. Like Huo, Sharangpani (see, e.g., fig. 12B) discloses a memory array including a channel 60 formed in a memory hole through a stack of conductive 46 and insulating 32 layers, the channel comprising a first silicon layer 601 and a second 602 silicon layer. Sharangpani (¶¶0091,0095) further teaches that each of the first and second silicon layers may have a thickness of 2–10 nm, and that lesser or greater thicknesses may also be employed.
Although Sharangpani does not expressly disclose that the second silicon layer constitutes 75–95% of the overall thickness of the channel, the relative thicknesses of the first and second silicon layers would have been recognized as parameters subject to adjustment in forming the channel. In view of Sharangpani’s teaching that the thicknesses of the respective silicon layers may be varied, it would have been obvious to one of ordinary skill in the art to adjust the respective thicknesses of the first and second silicon layers to obtain a desired relative thickness therebetween, including a second silicon layer constituting 75–95% of the overall thickness of the channel.
The selection of particular thickness proportions for the respective silicon layers represents a change in proportion or degree of known structural features. Such optimization would have been within the ordinary skill in the art, particularly where the prior art expressly contemplates varying the thicknesses of the respective layers. See MPEP § 2144.05; In re Aller, 220 F.2d 454, 456 (CCPA 1955) (where the general conditions are disclosed in the prior art, it is not inventive to discover optimum or workable ranges by routine experimentation).
Moreover, the present specification does not establish any criticality associated with the particular 75–95% proportion. Although the specification (¶0017) attributes reduced read-current variation to the lower grain-boundary density of the epitaxial silicon layer, it does not demonstrate that the claimed 75–95% proportion, as opposed to other relative thicknesses, produces an unexpected result or a difference in kind. Accordingly, absent evidence that the claimed proportion is critical or produces an unexpected result, the particular selection of the relative thicknesses would have been a matter of routine optimization of known parameters.
Therefore, it would have been obvious to one of ordinary skill in the art to select the thicknesses of the first and second silicon layers such that the second silicon layer constitutes 75–95% of the overall thickness of the channel.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Huo/Lee in view of Purayath (US 2020/0051994).
Regarding claim 21, Lee teaches that the intersection points between grain boundaries are reduced or eliminated (Lee: p.H778/col.1/ll.33-36). Huo/Lee, however, fail to teach etching the first part to reduce the thickness of the poly-Si to 1-5 nm. Purayath (¶0048) teaches doing so to increase carrier mobility.
Accordingly, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to etch the first part to reduce the thickness of the poly-Si layer, as suggested by Purayath, to increase carrier mobility.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Huo/Lee in view of Rabkin (US 2015/0076586).
Regarding claim 17, Huo (fig. 10, ¶0041) discloses a semiconductor structure including a core dielectric 2TP. Although Huo does not identify the particular material of the core dielectric, Rabkin (fig. 1N, ¶0069) discloses a similar structure including a core dielectric 62 and identifies silicon oxide as one of a plurality of dielectric materials that may be used for the core dielectric.
It would have been obvious to one of ordinary skill in the art to select silicon oxide as the material of the core dielectric of Huo in view of the teachings of Rabkin. The selection of silicon oxide from among the known dielectric materials identified by Rabkin represents the use of a known material for its known purpose and would have yielded predictable results.
Accordingly, the combination of Huo and Rabkin teaches or suggests a semiconductor structure including a core dielectric comprising silicon oxide.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Marcos D. Pizarro at (571) 272-1716 and between the hours of 9:00 AM to 7:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Marcos.Pizarro@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/Marcos D. Pizarro/Primary Examiner, Art Unit 2814
MDP/mdp
September 3, 2026
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