Attorney’s Docket Number: 103585-US-PA
Filing Date: 4/12/2021
Inventors: Chen et al.
Examiner: Marcos D. Piza, 3rro
DETAILED ACTION
This Office action responds to the amendment filed on 11/14/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1, 3-5, 16, 17 and 19 are rejected under 35 U.S.C. 112(a) as failing to comply with the enablement requirement.
The claims contain subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention without undue experimentation.
The specification does not enable a person skilled in the art to which it pertains, or with which it is most nearly connected, to make the invention commensurate in scope with these claims.
Claim 1 recites a channel layer comprising a first material layer of polycrystalline silicon and a second material layer of epitaxial silicon, wherein a number of grain boundaries of the second material layer is less than a number of grain boundaries of the first material layer. The specification discloses that the second material layer may be deposited by HWCVD using SiH₄ in Ar at a temperature of 400–550°C and under a pressure of 10⁻² - 1 Torr (see par. 0017), and further asserts that the epitaxial silicon layer has fewer grain boundaries than the polycrystalline silicon layer. The specification further discloses forming the channel layer, including both the polycrystalline silicon first part and the epitaxial silicon second part, on the sidewall of a hole penetrating through an alternating stack of insulating and conductive layers in a 3D NAND structure (see par. 0023). However, while the specification discloses the structural context of the claimed invention and certain HWCVD process parameters, it does not provide sufficient guidance to enable a person of ordinary skill in the art to actually achieve the claimed reduction in grain boundaries between the two distinct layers without undue experimentation. Specifically, the specification discloses only generically that an annealing process is performed on an amorphous silicon layer to form the polycrystalline silicon layer (see par. 0015), without specifying any particular crystallization method, annealing conditions, or resulting poly-Si film characteristics necessary to serve as a suitable template for the growth of an epi-Si layer having fewer grains.
In determining whether undue experimentation would be required, the factors set forth in In re Wands, 858 F.2d 731, 737 (Fed. Cir. 1988), have been considered:
Breadth of claims: The claims cover any epitaxial silicon second material layer having fewer grain boundaries than the polycrystalline silicon first material layer, without limitation as to the crystallization process used to form the polycrystalline silicon layer or other specific process conditions beyond those disclosed.
Nature of the invention: The invention concerns controlling crystallinity during semiconductor deposition in a complex three-dimensional geometry involving an alternating stack of insulating and conductive layers, an unpredictable art.
State of the prior art: It is a well-established principle of semiconductor physics that when epitaxial silicon is grown on a polycrystalline silicon substrate, the epitaxial layer inherits the grain structure of the substrate, each grain in the poly-Si serves as a nucleation site and the epitaxial layer extends the existing grains coherently. As a consequence, the grain boundaries in the epitaxial layer will be located at the same lateral positions as those in the underlying poly-Si layer. This principle is consistent with and confirmed by Lee, the literature by the applicant, as discussed further below. The prior art, therefore, does not establish that an epitaxial silicon layer grown on a polycrystalline silicon layer will have fewer grain boundaries than the underlying polycrystalline silicon layer when the two are considered as distinct layers, which is what the claims require.
Level of ordinary skill: High; workers in this art are highly skilled.
Predictability of the art: Low; achieving a reduction in grain boundaries in an epitaxial silicon layer grown on a polycrystalline silicon layer, such that the two distinct layers have different grain boundary densities, is contrary to the well-established principle that epitaxial growth on a polycrystalline substrate replicates the grain structure of that substrate. The specification provides no guidance as to how this expected behavior is overcome.
Amount of direction provided: Partial; while the disclosure does provide certain HWCVD process parameters including gas composition, temperature, and pressure ranges (see par. 0017), it provides only a generic reference to annealing to form the polycrystalline silicon layer (see par. 0015). The disclosure fails to provide guidance as to the specific crystallization method or conditions necessary to yield a polysilicon layer that, together with subsequent HWCVD epitaxial growth, would result in the claimed grain boundary reduction between the two distinct layers.
Presence of working examples: None; no data or examples are provided to demonstrate that the epitaxial silicon layer has fewer grain boundaries than the underlying polycrystalline silicon layer as distinct layers in the claimed three-dimensional memory device context.
Quantity of experimentation required: Substantial; achieving the claimed result, an epitaxial silicon layer with fewer grain boundaries than the distinct underlying polycrystalline silicon layer, runs counter to the well-established behavior of epitaxial growth on polycrystalline substrates, and one of ordinary skill would need to engage in extensive experimentation to determine whether and how the claimed result could be achieved, without any meaningful guidance from the specification.
Considering these factors, the specification fails to provide sufficient guidance to enable the claimed invention without undue experimentation.
Furthermore, the literature relied upon by the applicant, Lee, does not teach the specific claim limitation for which it is being cited, namely that the epitaxial silicon second material layer will have fewer grain boundaries than the underlying polycrystalline silicon first material layer when the two are considered as distinct layers. The HRTEM analysis of Figures 3 and 4 in Lee et al. shows that the epi-Si layer grows fully coherently on the underlying poly-Si grains, with no abrupt change in contrast at the epi-Si/poly-Si interface and with identical planar lattice distances on both sides of the interface. Lee explicitly states that there is no epitaxy breakdown, and that the crystallinity of the poly-Si seed film is maintained up to the surface of the epitaxial Si. See, e.g., p.H779/col2/ll.13,14, 22-24,27-30. The plan-view TEM and SADP analysis of Figure 5 further shows that the grain orientation of the underlying poly-Si seed film is fully consistent with that of the upper epi-Si layer, with no ring pattern indicative of a distinct polycrystalline phase in the epi-Si/poly-Si structure. See, e.g., p.H780/col.1/ll.4-8. This is fully consistent with the well-established scientific principle that epitaxial growth on a polycrystalline substrate replicates the grain structure of that substrate.
What Lee actually teaches is that the epi-Si layer grows coherently on and extends the crystal structure of the underlying poly-Si grains, such that the combined epi-Si/poly-Si structure behaves as a single thicker silicon layer with uniform crystalline properties throughout. The reported increase in grain size and reduction in grain boundary density are properties of the combined epi-Si/poly-Si structure, as a whole, relative to the original poly-Si seed film alone. This is attributable to either the merging of adjacent grains with low angle boundaries in the seed film or the preferential epitaxial growth of grains with a particular orientation during the HWCVD process. See, e.g., p.H780/col.1/ll.24-30. It is not a property that distinguishes the epi-Si layer from the underlying poly-Si layer as two distinct layers with different grain boundary densities. Lee, therefore, does not teach that the epitaxial silicon layer itself has fewer grain boundaries than the underlying polycrystalline silicon layer when the two are considered as distinct layers, which is precisely what the claims require. Accordingly, even taking Lee into account, a person of ordinary skill in the art would not be reasonably guided by either the specification or Lee to achieve the specific claimed result without undue experimentation.
Claims 1, 3-5, 16, 17 and 19 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement.
The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor, or a joint inventor, at the time the application was filed, had possession of the claimed invention.
Claim 1 recites a channel layer comprising a first material layer of polycrystalline silicon and a second material layer of epitaxial silicon, wherein the number of grain boundaries of the second material layer is less than the number of grain boundaries of the first material layer. While the specification states that an epitaxial layer grown by HWCVD using SiH₄ in Ar will have fewer grain boundaries than an underlying polysilicon layer (see par. 0017), and while the specification does disclose forming the channel layer in the context of a hole penetrating through an alternating stack of insulating and conductive layers (see par. 0023), the specification does not describe any specific structure, method, or mechanism by which the claimed reduction in grain boundaries between the two distinct layers is actually achieved. The specification discloses only generically that an annealing process is performed on an amorphous silicon layer to form the polycrystalline silicon layer (see par. 0015), without specifying any particular crystallization method or conditions. Furthermore, it is a well-established principle of semiconductor physics that epitaxial growth on a polycrystalline silicon substrate replicates the grain structure of that substrate, as the epitaxial layer grows coherently from and extends the existing grains of the polycrystalline layer. This principle is confirmed by the Lee, submitted by applicant, which shows, through HRTEM, SADP and SEM analysis, that the epi-Si and poly-Si layers in fact behave as a single uniform layer with consistent crystalline properties throughout, a result that is inconsistent with the claim requirement that the two distinct layers have different grain boundary densities from one another. See, e.g., figures 3-7, p.H779/col.2/ll.8-10,13,14,22-24,27-30, and p.H780/col.1/ll.4-8,24-27. The absence of any disclosure in the specification describing a specific process or mechanism by which the epitaxial silicon layer is made to have fewer grain boundaries than the distinct underlying polycrystalline silicon layer means the specification does not reasonably convey to those skilled in the art that the inventors had possession of the claimed invention. The disclosure therefore amounts to a conclusory statement of a desired outcome, without demonstrating that the inventors possessed a process or structure that actually achieves that outcome. Ariad Pharmaceuticals, Inc. v. Eli Lilly and Co., 598 F.3d 1336 (Fed. Cir. 2019) (en banc).
Response to Arguments
The applicant argues:
Claim 1 recites that the number of grains of the second layer is less than the number of grains in the first layer. This feature is easily known to any person skilled in the art in accordance with Lee. Lee teaches that having a lower number of grains in the epi-Si layer than in the poly-Si layer is conventional, which means that the disclosure includes sufficient guidance to enable one skill in the art to achieve that result without undue experimentation. Similarly, the specification contains a full, clear, and concise written description of the invention to enable any person skill in the art to make and use the invention.
The examiner responds:
The applicant argues that Lee (Journal of The Electrochemical Society, 154(9) H778-H781, 2007), demonstrates that the claimed reduction in grain boundaries is conventional knowledge known to a person of ordinary skill in the art, and that the 112(a) rejections should therefore be withdrawn. This argument is not persuasive for the following reasons.
First, while the examiner acknowledges that the specification does disclose forming the channel layer in the context of a hole penetrating through an alternating stack (see par. 0023), and further acknowledges that the specification does provide certain HWCVD process parameters including gas composition, temperature, and pressure ranges (see par. 0017). The specification, nonetheless, fails to provide sufficient process guidance to enable the claimed grain boundary reduction between the two distinct layers. Specifically, the specification discloses, only generically, that an annealing process is performed on an amorphous silicon layer to form the polycrystalline silicon layer (see par. 0015). The specification fails to specify any particular crystallization method or conditions necessary to yield a polysilicon layer suitable for achieving the claimed result. Furthermore, it is a well-established principle of semiconductor physics that epitaxial growth on a polycrystalline silicon substrate replicates the grain structure of that substrate, as the epitaxial layer grows coherently from and extends the existing grains of the polycrystalline layer. The specification provides no guidance as to how this expected behavior is overcome to yield an epitaxial silicon layer with fewer grain boundaries than the distinct underlying polycrystalline silicon layer, as the claims require.
Second, and most critically, a careful reading of Lee reveals that it does not teach the specific claim limitation for which it is being cited. The claims require that the epitaxial silicon second material layer have fewer grain boundaries than the polycrystalline silicon first material layer, with the two being distinct layers having different grain boundary densities from one another. However, the HRTEM analysis of Figures 3 and 4 of Lee shows that the epi-Si layer grows fully coherently on, and extends the crystal structure of the underlying poly-Si grains, with no abrupt change in contrast at the epi-Si/poly-Si interface, and with identical planar lattice distances on both sides of the interface. The authors of Lee explicitly state that there is no epitaxy breakdown, and that the crystallinity of the poly-Si seed film is maintained up to the surface of the epitaxial Si. See, e.g., p.H779/col.2/ll.13-30. The plan-view TEM and SADP analysis of Figure 5 further confirms that the grain orientation of the underlying poly-Si seed film is fully consistent with that of the upper epi-Si layer, with no ring pattern indicative of a distinct polycrystalline phase in the epi-Si layer. See, e.g., p.H780/col.1/ll.4-8. This behavior is fully consistent with the well-established scientific principle that epitaxial growth on a polycrystalline substrate replicates the grain structure of that substrate. What Lee actually teaches is that the epi-Si and poly-Si layers behave as a single thicker silicon layer with uniform crystalline properties throughout. Lee’s reported increase in grain size and reduction in grain boundary density are properties of the combined structure as a whole relative to the original poly-Si seed film alone. This is attributable to either the merging of adjacent grains with low angle boundaries in the seed film or the preferential epitaxial growth of grains with a particular orientation during the HWCVD process. See, e.g., par.H780/col.1/ll.17-28. Nowhere does Lee teach that the epi-Si layer has larger grains than the underlying poly-Si layer, or that they are two distinct layers with different grain boundary densities. Lee, therefore, fails to teach that the epitaxial silicon layer itself has fewer grain boundaries than the underlying polycrystalline silicon layer when considered as distinct layers, which is precisely what the claims require. Applicant’s reliance on Lee as evidence supporting the claimed limitation is, therefore, misplaced, as the reference does not support that limitation and, to the contrary, is consistent with the well-established scientific principle that epitaxial growth on a polycrystalline substrate replicates rather than reduces the grain boundary density of that substrate.
Finally, Lee is extrinsic to the specification and cannot cure the specification’s own failure to provide sufficient guidance. The question of enablement and written description is assessed based on what the specification itself teaches as of the filing date, not what an external reference may suggest. Accordingly, the rejections under 35 U.S.C. 112(a) are maintained.
Conclusion
Applicant's amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, this action is made final. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire three months from the mailing date of this action. In the event a first reply is filed within two months of the mailing date of this final action and the advisory action is not mailed until after the end of the three-month shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Marcos D. Pizarro at (571) 272-1716 and between the hours of 9:00 AM to 7:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Marcos.Pizarro@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/Marcos D. Pizarro/Primary Examiner, Art Unit 2814
MDP/mdp
March 11, 2026