DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on Nov. 6th, 2025 has been entered. Claims 1-2, 4-11, 21-23, 25-27 and 31-34 remain pending in the application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 9-11 and 32 are rejected under 35 U.S.C. 103 as being unpatentable over Yi et al. (US 20180182810) in view of Yang et al. (US 20180358547), Lee et al. (US 20050090119) and Chu et al. (US 20180158728).
Regarding claim 9, Yi teaches a method (abstract), comprising:
forming a dielectric layer (fig. 4b, second upper dielectric layer 150; para. 0044) over a substrate (fig. 2a, substrate 105; para. 0015), wherein the substrate (105) has a cell region (second region 110b may be referred to as the memory region; para. 0014) and a logic region (first region 110a may be referred to as the logic region; para. 0014) adjacent to the cell region (110b);
forming a generic bottom electrode (fig. 4b, bottom electrode 162; para. 0040) over the cell region of the substrate (110b);
forming a magnetic tunnel junction (MTJ) layer (fig. 4b, MTJ stack 164; para. 0041);
forming a top electrode (fig. 4b, top electrode 166; para. 0040) over the MTJ layer (164); and
forming a top electrode via (fig. 4e, via contact 184, metal line 185; para. 0046) over the exposed top surface of the memory layer (164) such that the top electrode via (184, 185) is electrically connected to the memory layer (electrically connected to 164 through 166).
Yi fails to teach etching the top electrode to expose a top surface of the MTJ layer; and the top electrode via is in direct contact with the MTJ layer.
However, Yang teaches etching the top electrode (Yang: fig. 9-11, etch mask 108 with material of top electrode; para. 0032, similar to 166 of Yi) to expose a top surface of the MTJ layer (Yang: selector film stack 102, intermediate electrode film stack 106, magnetic memory element films stack 100 as the MTJ structure; para. 0031, similar to 164 of Yi); and the top electrode via (Yang: fig. 11, second conductive line 116; para. 0040, similar to 184, 185 of Yi) is in direct contact with the MTJ layer (Yang: 102, 106, 100).
Yang and Yi are considered to be analogous to the claimed invention because they are in the same field of electrodes of MTJ devices.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed method to add etching the top electrode to expose a top surface of the memory layer as taught by Yang into Yi.
Doing so would realize top electrode via directly connect the memory layer and a manufacturing method that can reliably produce magnetic memory cells with high yield (Yang: para. 0010).
In addition, Yi in view of Yang fails to teach forming an etch stop layer over the cell region and in direct contact with the MTJ layer.
However, Lee teaches forming an etch stop layer (Lee: fig. 9, patterned portion 25 p of the first mask layer 25; para. 0042) over the cell region (Lee: memory cell; para. 0002) and in direct contact with the MTJ layer (Lee: layers 30 of magnetic tunnel junction stack; para. 0043, similar to 164 of Yi).
Lee, Yang and Yi are considered to be analogous to the claimed invention because they are in the same field of electrodes of MTJ devices.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed method to add etch stop layer as taught by Lee into Yi in view of Yang.
Doing so would realize a mask layer to protect the MTJ stack and for a self-aligned via with advantage to the method to avoid a misalignment (Lee: para. 0055, 0043).
In addition, Yi in view of Yang and Lee fails to teach forming a bottom electrode layer
forming a magnetic tunnel junction (MTJ) layer over the bottom electrode layer;
patterning the bottom electrode layer at least using the MTJ layer as an etch mask to form a bottom electrode to form the generic bottom electrode.
However, Chu teaches forming a bottom electrode layer (Chu: fig. 10, bottom electrode layer 165; para. 0038);
forming a magnetic tunnel junction (MTJ) layer (Chu: resistance switching element 175; para. 0038, similar to 164 of Yi) over the bottom electrode layer (Chu: 165);
patterning the bottom electrode layer (Chu: fig. 11, 12, patterning 165) at least using the MTJ layer (Chu: 175) as an etch mask (Chu: 175 as mask to etch 165) to form a bottom electrode (Chu: bottom electrode 167; para. 0038, similar to 162 of Yi) to form the generic bottom electrode (Yi: 162).
Chu, Lee, Yang and Yi are considered to be analogous to the claimed invention because they are in the same field of electrodes of MTJ devices.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed method to add forming a bottom electrode layer and patterning the bottom electrode layer at least using the MTJ layer as an etch mask as taught by Chu.
Doing so would forming the bottom electrode and the spacer together to save manufacture step and realize a BEVA structure bottom electrode to improve the adhesion to the plug for connection (Chu: para. 0026).
Regarding claim 10, Yi in view of Yang and Lee and Chu further teaches forming a spacer (Yi: fig. 4c, vertical dielectric spacers 287; para. 0051) lining with sidewalls of the MTJ layer (Yi: 164) and the top electrode (Yi: 166) after forming the top electrode (Yi: 166).
Regarding claim 11, Yi in view of Yang and Lee and Chu further teaches forming the spacer (Yi: fig. 4c, 287) is performed such that a sidewall of the bottom electrode (Yi: side wall of 162) is free of the spacer (Yi: 287).
Regarding claim 32, Yi in view of Yang and Lee and Chu further teaches the method of claim 9, further comprising:
forming a bottom electrode via (Chu: fig. 12, bottom electrode via of lining metal layer 140; para. 0014) over the cell region of the substrate (Yi: 110b with the MTJ structure), wherein the bottom electrode via (Chu: 140) has a bottom width (Chu: bottom width of 140) smaller than a bottom width of the bottom electrode (Chu: bottom width of 165).
Allowable Subject Matter
Claims 1-2, 4-8, 21-23, 25-27, 31 and 33-34 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 1 would be allowable for disclosing “depositing a dielectric material over the dielectric layer on the cell region and the logic region;
etching the dielectric material to form a second spacer extending upwards from the dielectric layer and lining with sidewalls of the bottom electrode and the first spacer and to remove the dielectric material entirely from the logic region, wherein the second spacer is made of the dielectric material and has a bottom surface lower than a top surface of the bottom electrode;
etching the top electrode to expose a top surface of the memory layer and an inner sidewall of the first spacer, wherein after etching the top electrode, the exposed top surface of the memory layer is lower than the exposed inner sidewall of the first spacer”.
Claim 2, 4-8 and 31 would be also allowable because they are dependent on claim 1.
Claim 21 would be allowable for disclosing “the top electrode via is in direct contact with the MTJ layer, wherein forming the top electrode via over the MTJ layer comprises:
etching the top electrode such that a recess is formed on the MTJ layer; and
after etching the top electrode, depositing a second dielectric layer covering the MTJ layer and the first spacer, wherein the second dielectric layer is disposed in the recess”
Claim 22-23, 25-27 and 33-34 would be also allowable because they are dependent on claim 21.
Response to Arguments
Applicant’s arguments with respect to claims 9-11 and 32 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHIJUN XU whose telephone number is (571)270-3447. The examiner can normally be reached Monday-Thursday 9am-5pm ET.
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/ZHIJUN XU/Examiner, Art Unit 2818
/BRIAN TURNER/Examiner, Art Unit 2818