DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
As to claim 1, Applicant's arguments filed 02/11/2026 have been fully considered but they are not persuasive. Applicant states in the middle of Page 13 that Yamazaki does not teach each of the first layer 104a and second layer 104b as an insulator “since each of them expressly disclose conductive materials (or conductive alloys)”. Applicant further goes on to state “Even if some may be easily bonded to oxygen…nothing suggests that the resultant final product as a first layer or second layer is an insulator having insulating properties, absent speculation or impermissible hindsight”. Examiner disagrees, Yamazaki in view of Tanaka teaches the oxidation of Yamazaki’s comparative first layer and second layer. One of ordinary skill in the art would understand that when conductors are oxidized, they form a surface oxide layer that increases electrical resistance, and creates an insulating barrier at contact points thus acting as insulator.
Applicant’s arguments with respect to claim(s) 5 and 6 have been considered but are
moot in view of new grounds of rejection.
Claim Rejections - 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 22, 28 and 32 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki et al. (US 2016/0190273 A1), hereafter “Yamazaki”, in view of Tanaka (US 2019/0006451 A1), hereafter “Tanaka”.
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As to claim 1, Yamazaki teaches a semiconductor device comprising a metal oxide (⁋ [0237], 103c, Fig. 3B), an insulating layer (⁋ [0111], 106, Fig. 3B), a first conductive layer (⁋ [0111], 164a), a second conductive layer (164b), a third conductive layer (⁋ [0114], 107a), a first layer (⁋ [0110], 104a), and a second layer (104b),
wherein the metal oxide (103c) comprises a first region, a second region, and a third region (see annotated Fig. 3B above),
wherein the first conductive layer (164a) overlaps with the first region (103c) (see annotated Fig. 1 above),
wherein the second conductive layer (164b) overlaps with the second region (103c) (see annotated Fig. 3B above),
wherein the third conductive layer (107a) overlaps with the third region (103c) with the insulating layer (106) interposed therebetween (see annotated Fig. 3B above),
wherein the first layer (104a) is positioned between the first region (103c) and the first conductive layer (164a) (see annotated Fig. 3B above),
wherein the second layer (104b) is positioned between the second region (103c) and the second conductive layer (164b) (see annotated Fig. 3B above),
wherein the insulating layer (106) is positioned between the first layer (104a) and the second layer (104b) (see annotated Fig. 3B above),
wherein the first layer (104a) is in contact with a top surface of the first region (103c) (see annotated Fig. 3B above),
wherein the first conductive layer (164a) is in contact with a top surface of the first layer (110a) (Fig. 1),
wherein the second layer (110b) is in contact with a top surface of the second region (103c) (see annotated Fig. 3B above),
wherein the second conductive layer (164b) is in contact with a top surface of the second layer (104b) (Fig. 3B), and
wherein a resistance of the third region is higher than a resistance of the first region and a resistance of the second region (⁋ [0020]).
Yamazaki fails to teach wherein each of the first layer and second layer is an insulator.
Tanaka teaches a similar oxide semiconductor device with a layer (⁋ [0115], 108a, Fig. 1) and another layer (108b) made of similar material (“Tantalum”, ⁋ [0136]) as Yamazaki’s first and second layers (⁋ [0118], 104a+104b) and in contact with an oxide semiconductor layer (112, ⁋ [0113]), wherein the surfaces are oxidized (⁋ [0136]) and the unlabeled surface oxide layers of 108a and 108b are considered to be "the first layer" and “the second layer” and are insulators.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize the layers as taught by Tanaka into the semiconductor device taught by Yamazaki to form a good contact with the oxide semiconductor layer (⁋ [0136]).
As to claim 22, Yamazaki teaches wherein each of the first layer (104a) and the second layer (104b) comprises tantalum, nitrogen, and oxygen or comprise tantalum and oxygen (⁋ [0118], “a conductive material which is easily bonded to oxygen”). Tantalum is the conductive material used to which the oxygen from 103 becomes bonded to resulting in “the concentration of oxygen is reduced in part of the stack 103”. As a result, the first and second layer are comprised of tantalum and an insulator, oxygen.
Yamazaki fails to teach wherein each of the first conductive layer and the second conductive layer comprises tantalum nitride.
Tanaka teaches a similar oxide semiconductor device wherein the first conductive layer (⁋ [0115], 108a, Fig. 1) and the second conductive layer (108b) each comprise tantalum nitride (⁋ [0122]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to substitute the material as taught by Tanaka into the semiconductor device taught by Yamazaki to yield the predictable result of improved conductivity and guaranteed stability (⁋ [0122]).
As to claim 28, Yamazaki teaches wherein the metal oxide comprises indium, an element M, and zinc, and wherein M is aluminum, gallium, yttrium, or tin (⁋ [0032]).
As to claim 32, Yamazaki in view of Tanaka teach the semiconductor device according to claim 28,
Yamazaki further teaches wherein each of the first layer (104a) and the second layer (104b) comprises a second metal oxide (aluminum oxide) comprising the element M (Tanaka teaches the oxidation of the Tantalum, shown to be interchangeable with aluminum, metal layer of Yamazaki; see claim 6), and
wherein a concentration of the element M (aluminum) in the second metal oxide is higher than a concentration of the element M in the first metal oxide (⁋ [0032], Yamazaki teaches various combinations excluding aluminum but using the other element of M, i.e. gallium, yttrium, or tin).
Claims 5, 6, and 30-31 are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka further in view of Zhang et al. (US 2016/0247830 A1), hereafter Zhang.
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As to claim 5, Tanaka teaches a semiconductor device comprising a transistor, wherein the transistor comprises a first metal oxide (⁋⁋ [0113], [0118], 112, Fig.1), a first insulating layer (⁋ [0113], 106, Fig. 1), a second insulating layer (⁋ [0113], 114, Fig. 1), a first conductive layer (⁋ [0115], 108a), a second conductive layer (108b), a third conductive layer (⁋ [0113], 104), a fourth conductive layer (116), a first layer (⁋ [0116], 110a), and a second layer (110b),
wherein the second insulating layer (114) is provided over the fourth conductive layer (116),
wherein the first metal oxide (112) is provided over the second insulating layer (114),
wherein the first insulating layer (106) is provided over the first metal oxide (112),
wherein the third conductive layer (104) is provided over the first insulating layer (106),
wherein the first metal oxide comprises a first region, a second region, and a third region (see annotated Fig. 1 above),
wherein the first region overlaps with the first conductive layer (108a) (see annotated Fig. 1 above),
wherein the second region overlaps with the second conductive layer (108b) (see annotated Fig. 1 above),
wherein the third region overlaps with the third conductive layer (104) with the first insulating layer (106) interposed therebetween,
wherein the first layer (110a) is provided between the first region and the first conductive layer (108a) (see annotated Fig. 1 above),
wherein the second layer (110b) is provided between the second region and the second conductive layer (108b) (see annotated Fig. 1 above),
wherein the first insulating layer (106) is positioned between the first layer (110a) and the second layer (110b) (see annotated Fig. 1 above),
wherein the first layer (110a) is in contact with a top surface of the first region (see annotated Fig. 1 above),
wherein the first conductive layer (108a) is in contact with a top surface of the first layer (110a),
wherein the second layer (110b) is in contact with a top surface of the second region (see annotated Fig. 1 above),
wherein the second conductive layer (108b) is in contact with a top surface of the second layer (110b),
wherein an off-state current of the transistor is lower than or equal to 1 aA at a temperature higher than or equal to 180 °C and lower than or equal to 220 °C, Tanaka teaches all the structural limitations and therefore would be capable of performing the functional limitation.
wherein the first metal oxide comprises indium, an element M, and zinc (⁋ [0118]), and
wherein M is aluminum, gallium (⁋ [0118]), yttrium, or tin.
Tanaka fails to teach wherein each of the first layer and the second layer is an insulator.
Zhang teaches a similar oxide semiconductor device with a layer (⁋ [0037], 5, Fig. 2) and another layer (6) made of similar material (“Aluminum”, ⁋ [0051]) as Tanaka’s first and second layers (⁋ [0126], 110a+110b) and in contact with an oxide semiconductor layer (4, ⁋ [0038]), wherein the surfaces are oxidized (⁋ [0051]) and are insulators.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize the insulators as taught by Zhang into the semiconductor device taught by Tanaka to improve conductivity of the active layer (⁋ [0097]).
As to claim 6, Tanaka teaches a semiconductor device comprising a transistor, wherein the transistor comprises a first metal oxide (⁋⁋ [0113], [0118], 112, Fig.1), a first insulating layer (⁋ [0113], 106, Fig. 1), a second insulating layer (⁋ [0113], 114, Fig. 1), a first conductive layer (⁋ [0115], 108a), a second conductive layer (108b), a third conductive layer (⁋ [0113], 104), a fourth conductive layer (116), a first layer (⁋ [0116], 110a), and a second layer (110b),
wherein the second insulating layer (114) is provided over the fourth conductive layer (116),
wherein the first metal oxide (112) is provided over the second insulating layer (114),
wherein the first insulating layer (106) is provided over the first metal oxide (112),
wherein the third conductive layer (104) is provided over the first insulating layer (106),
wherein the first metal oxide comprises a first region, a second region, and a third region (see annotated Fig. 1 above),
wherein the first region overlaps with the first conductive layer (108a) (see annotated Fig. 1 above),
wherein the second region overlaps with the second conductive layer (108b) (see annotated Fig. 1 above),
wherein the third region overlaps with the third conductive layer (104) with the first insulating layer (106) interposed therebetween,
wherein the first layer (110a) is provided between the first region and the first conductive layer (108a) (see annotated Fig. 1 above),
wherein the second layer (110b) is provided between the second region and the second conductive layer (108b) (see annotated Fig. 1 above),
wherein the first insulating layer (106) is positioned between the first layer (110a) and the second layer (110b) (see annotated Fig. 1 above),
wherein the first layer (110a) is in contact with a top surface of the first region (see annotated Fig. 1 above),
wherein the first conductive layer (108a) is in contact with a top surface of the first layer (110a),
wherein the second layer (110b) is in contact with a top surface of the second region (see annotated Fig. 1 above),
wherein the second conductive layer (108b) is in contact with a top surface of the second layer (110b),
wherein an off-state current per micrometer in a channel width of the transistor is lower than or equal to 10 aA/pm at a temperature higher than or equal to 180 °C and lower than or equal to 220 °C, Tanaka teaches all the structural limitations and therefore would be capable of performing the functional limitation.
wherein the first metal oxide comprises indium, an element M, and zinc (⁋ [0118]), and
wherein M is aluminum, gallium (⁋ [0118]), yttrium, or tin.
Tanaka fails to teach wherein each of the first layer and the second layer is an insulator.
Zhang teaches a similar oxide semiconductor device with a layer (⁋ [0037], 5, Fig. 2) and another layer (6) made of similar material (“Aluminum”, ⁋ [0051]) as Tanaka’s first and second layers (⁋ [0126], 110a+110b) and in contact with an oxide semiconductor layer (4, ⁋ [0038]), wherein the surfaces are oxidized (⁋ [0051]) and are insulators.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize the insulators as taught by Zhang into the semiconductor device taught by Tanaka to improve conductivity of the active layer (⁋ [0097]).
As to claim 30, Tanaka in view of Zhang teach the semiconductor device according to claim 5,
wherein each of Tanaka’s the first layer (110a) and the second layer (110b) comprise a second metal oxide (aluminum oxide) comprising the element M (Zhang teaches the oxidation of the aluminum metal layer of Tanaka; see claim 5), and
Tanaka further teaches wherein a concentration of the element M in the second metal oxide (Aluminum) is higher than a concentration of the element M in the first metal oxide (⁋ [0118], Tanaka teaches various combinations excluding aluminum but using the other elements of M, i.e. gallium, yttrium, or tin).
As to claim 31, Tanaka in view of Zhang teach the semiconductor device according to claim 6,
wherein each of Tanaka’s the first layer (110a) and the second layer (110b) comprise a second metal oxide (aluminum oxide) comprising the element M (Zhang teaches the oxidation of the aluminum metal layer of Tanaka; see claim 5), and
Tanaka further teaches wherein a concentration of the element M in the second metal oxide (Aluminum) is higher than a concentration of the element M in the first metal oxide (⁋ [0118], Tanaka teaches various combinations excluding aluminum but using the other elements of M, i.e. gallium, yttrium, or tin).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki in view of Tanaka, as applied to claim 1, and further in view of Yeo et al. (US 2017/0194442 A1), hereafter “Yeo”.
As to claim 18, Yamazaki fails to teach wherein a thickness of each of the first layer and the second layer is greater than or equal to 0.5 nm and less than or equal to 3 nm.
Yeo teaches a device in a similar field of endeavor (⁋ [0013]) with a conduction layer 108 which acts as a dielectric located between the source/drain contacts 116 and the semiconductor material of 106 and 104 with a thickness of 1nm or thinner (Fig. 14, ⁋ [0041])
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize the thickness taught by Yeo into the semiconductor device taught by Yamazaki and Tanaka to help reduce Fermi-level pinning effects between a metallic material and a semiconductor material and allow a high current density to flow across without a large voltage drop (⁋ [0041]).
Additionally, in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art”, a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ 2d 1934 (Fed. Cir. 1990). MPEP 2144.05.
Claims 20 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka in view of Zhang, as applied to claims 5 and 6, and further in view of Yeo.
As to claim 20, Tanaka fails to teach wherein a thickness of each of the first layer and the second layer is greater than or equal to 0.5 nm and less than or equal to 3 nm.
Yeo teaches a device in a similar field of endeavor (⁋ [0013]) with a conduction layer 108 which acts as a dielectric located between the source/drain contacts 116 and the semiconductor material of 106 and 104 with a thickness of 1nm or thinner (Fig. 14, ⁋ [0041])
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize the thickness taught by Yeo into the semiconductor device taught by Tanaka and Zhang to help reduce Fermi-level pinning effects between a metallic material and a semiconductor material and allow a high current density to flow across without a large voltage drop (⁋ [0041]).
Additionally, in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art”, a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ 2d 1934 (Fed. Cir. 1990). MPEP 2144.05.
As to claim 21, Tanaka fails to teach wherein a thickness of each of the first layer and the second layer is greater than or equal to 0.5 nm and less than or equal to 3 nm.
Yeo teaches a device in a similar field of endeavor (⁋ [0013]) with a conduction layer 108 which acts as a dielectric located between the source/drain contacts 116 and the semiconductor material of 106 and 104 with a thickness of 1nm or thinner (Fig. 14, ⁋ [0041])
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize the thickness taught by Yeo into the semiconductor device taught by Tanaka and Zhang to help reduce Fermi-level pinning effects between a metallic material and a semiconductor material and allow a high current density to flow across without a large voltage drop (⁋ [0041]).
Additionally, in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art”, a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ 2d 1934 (Fed. Cir. 1990). MPEP 2144.05.
Claims 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka in view of Zhang, as applied to claims 5 and 6, and further in view of Tezuka et al. (US 2016/0322503 A1), hereafter “Tezuka”.
As to claim 13, Tanaka teaches wherein each of the first conductive layer and the second conductive layer comprises tantalum nitride (⁋ [0122]).
Tanaka and Zhang fail to teach wherein each of the first layer and the second layer comprises an insulator, and wherein each of the first layer and the second layer comprises tantalum, nitrogen, and oxygen or comprise tantalum and oxygen.
Tezuka teaches a similar oxide semiconductor device with a first and second conductive layer (429+431) and a first and second layer (⁋ [0110], 416a1+416a2, Fig. 1B) which contain tantalum and oxygen (⁋ [0138]). Oxygen is considered to be an insulator.
It would have been obvious to one of ordinary skill in the art before the effective filing date to substitute tantalum and oxygen as taught by Tezuka into the semiconductor device of Tanaka and Zhang as Tezuka shows tantalum and oxygen comparable to the aluminum and copper material utilized in Tanaka (⁋ [0138] of Tezuka).
As to claim 14, Tanaka teaches wherein each of the first conductive layer and the second conductive layer comprises tantalum nitride (⁋ [0122]), and
Tanaka and Zhang fail to teach wherein each of the first layer and the second layer comprises an insulator, and wherein each of the first layer and the second layer comprises tantalum, nitrogen, and oxygen or comprise tantalum and oxygen.
Tezuka teaches a similar oxide semiconductor device with a first and second conductive layer (429+431) and a first and second layer (⁋ [0110], 416a1+416a2, Fig. 1B) which contain tantalum and oxygen (⁋ [0138]). Oxygen is considered to be an insulator.
It would have been obvious to one of ordinary skill in the art before the effective filing date to substitute tantalum and oxygen as taught by Tezuka into the semiconductor device of Tanaka and Zhang as Tezuka shows tantalum and oxygen comparable to the aluminum and copper material utilized in Tanaka (⁋ [0138] of Tezuka).
Indication of Allowable Subject Matter
Claims 2, 19, 23, 29 and 33 are indicated allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 2, Tanaka is the closest prior art and does not teach a carrier concentration of the first region and the second region.
Claims 15-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CARNELL HUNTER whose telephone number is (571)270-1796. The examiner can normally be reached Monday - Friday 7:30 am - 4:30pm.
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/CARNELL HUNTER III/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893