DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim and Specification Status
The Examiner acknowledges the amendments to claims 1 and 12 in the Applicant’s response dated 6 March 2026. The claim amendments have been addressed below.
The Examiner acknowledges the addition of new claims 20-24 in the Applicant’s response dated 6 March 2026. The new claims have been addressed below.
The Examiner acknowledges the cancellation of claims 4 and 16 in the Applicant’s response dated 6 March 2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-9, 11, 18, 20-21 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki et al. (US 2017/0236844 A1; hereinafter “Yamazaki”), in view of Tutt et al. (US 2012/0178225 A1; hereinafter “Tutt”), and in further view of Yamakawa et al. (US 2016/0020327 A1; hereinafter “Yamakawa”), and in further view of Miyairi (US 9530856 B2; hereinafter “Miyairi”).
Regarding Claim 1, Yamazaki teaches a semiconductor device comprising:
a semiconductor layer (108, Fig. 15A, para [0275] describes an oxide semiconductor film 108);
a first insulating layer over and in contact with the semiconductor layer (110, Fig. 15A, para [0268] describes an insulating film 110 which can be seen as over and in contact with semiconductor layer 108 in Fig. 15A and Fig. 15B);
a metal oxide layer over and in contact with the first insulating layer (112_1, Fig. 15A, para [0268] describes a metal oxide layer 112_1 which is over and in contact with the first insulating layer 110),
a conductive layer in contact with the metal oxide layer(112_2, Fig. 15A, para [0268] describes a conductive film 112_2 which is describes as over the metal oxide layer 112_1 and is shown as being in contact with the metal oxide layer 112_1 in Fig. 15A and Fig. 15B);
a second insulating layer over and in contact with the first insulating layer and the conductive layer (116, Fig. 15A, para [0139] describes a second insulating film layer 116 wherein Fig. 15A and Fig. 15B depicts the second insulating layer 116 is over the first insulating layer 110 and in contact with at least a side portion of the first insulating layer 110 and wherein the second insulating layer is over and in contact with the conductive layer 112_2); and
wherein the second insulating layer covers the first insulating layer and a top surface and a side surface of the conductive layer (116, Fig. 15A, para [0139] describes the second insulating film layer 116 wherein Fig. 15A and Fig. 15B depicts wherein the second insulating layer 116 covers at least side surfaces of the first insulating layer 110 and a top surface and a side surface of the conductive layer 112_2),
wherein the conductive layer is over the first insulating layer (Fig. 15A, para [0268] describes wherein conductive layer 112_2 is over insulating layer 110),
wherein the metal oxide layer is between the first insulating layer and the conductive layer (Fig. 15A, para [0268] describes metal oxide layer 112_1 over insulating layer 110 and further wherein conductive layer 112_2 is over metal oxide layer 112_1),
wherein the semiconductor layer comprises a first region (108i, Fig. 15A, para [0275] describes a channel region 108i), a pair of second regions (108f, Fig. 15A, para [0275] describes regions 108f between channel region 108i and source and drain regions 108s and 108d), and a pair of third regions (108s and 108d, Fig. 15A, para [0275] describes source region 108s and drain region 108d),
wherein the first region overlaps with the metal oxide layer and the conductive layer (Fig. 15A, para [0139] describes wherein channel region 108i overlaps with conductive film 112 comprising metal oxide layer 112_1 and conductive layer 112_2),
wherein the pair of third regions sandwich the first region and the pair of second regions and do not overlap with the conductive layer (Fig. 15A, para [0275]-[0276] describes regions 108f between channel region 108i and source and drain regions 108s and 108d wherein source and drain regions do not overlap with conductive layer 112_2),
wherein the third regions each comprise a portion having lower resistance than the first region (para [0277] describes wherein third regions 108d and 108s have lower resistance than the first region 108i),
wherein the second regions each comprise a portion having higher resistance than the third regions (paras [0276]-[0277] describes wherein second regions 108f have higher resistance than third regions 108d and 108s), and
wherein the metal oxide layer comprises the same material as the semiconductor layer (112_1 and 108, Fig. 15A, para [0268] describes wherein the metal oxide layer 112_1 may comprise an oxide conductive film containing indium, gallium and zinc and para [0310] describes wherein the semiconductor layer 108 may be an oxide semiconductor film formed using a metal oxide comprising indium, gallium and zinc wherein both the metal oxide layer 112_1 and the semiconductor layer 108 may be comprised of the same indium, gallium and zinc material layers).
Yamazaki fails to disclose wherein an end portion of the metal oxide layer is on an inner side than an end portion of the conductive layer.
However, Tutt teaches a transistor, wherein an end portion of the metal oxide layer (120, Fig. 1, para [0026] and [0034], describes a first electrically conductive material layer which can be comprised of metal oxide materials including indium) is on an inner side than an end portion of the conductive layer (130, 180, Fig. 1, para [0026], [0028], and [0034], describes a second electrically conductive material layer, functioning as a gate electrode, which can be comprised of any suitable gate materials including indium, wherein the overhang 180 demonstrates the end portion of the second metal oxide layer 120 is on an inner side than an end portion of the second conductive layer 130).
Tutt further discloses wherein said end portion of the metal oxide layer being on an inner side of an end portion of the conductive layer creates an overhang. This overhang shortens the channel path and provides the advantage of reducing or preventing ungated regions in the transistor (para [0020] and para [0026]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Yamazaki with Tutt to include the end portion of the metal oxide layer being on an inner side of an end portion of the conductive layer in order to provide the advantage of enabling an overhang which provides the advantage of reducing or preventing ungated regions in a transistor (Tutt, para [0020] and para [0026]).
The combination of Yamazaki and Tutt fail to disclose an insulating region, wherein the insulating region is adjacent to the metal oxide layer, between the first insulating layer and the conductive layer, and between the metal oxide layer and the second insulating layer, wherein the pair of second regions sandwich the first region and overlap with the insulating region and the conductive layer.
However, Yamakawa teaches a semiconductor device comprising:
an insulating region (23, 23T and IR, Fig. 19, annotated Fig. 19, para [0122] describes an insulating film 23 wherein an upper portion 23T of the insulating film 23 comprises an insulating region IR),
wherein the insulating region is adjacent to the metal oxide layer (IR, annotated Fig. 19, depicts wherein upon modifying Yamazaki with Yamakawa to add the insulating region IR as shown in annotated Fig. 19, Yamazaki’s metal oxide’s width will be reduced to an inner side than an end portion of the conductive layer wherein the insulating region IR will be adjacent to the metal oxide layer 112_1 of Yamazaki) between the first insulating layer and the conductive layer (see annotated Fig. 19 below), and between the metal oxide layer and the second insulating layer (15 and IR, annotated Fig. 19 depicts wherein upon modifying Yamazaki with Yamakawa to add the insulating region IR as shown in annotated Fig. 19, Yamazaki’s metal oxide’s width will be reduced to an inner side than an end portion of the conductive layer and the insulating region IR will be on either side of the metal oxide layer 112_1 of Yamazaki putting it between the high-resistance film 15 constituting a second insulating film of Yamakawa as described in para [0070] and between the metal oxide layer 112_1 and second insulating layer 116 of Yamazaki),
wherein the pair of second regions sandwich the first region and overlap with the insulating region and the conductive layer (IR, annotated Fig. 19, wherein the modified region will be above the second region, overlapping).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Yamazaki and Tutt with Yamakawa to further disclose a gate insulating film comprising a thick-film corner section comprising an insulating region, wherein the insulating region is adjacent to a metal oxide layer, between the first insulating layer and a conductive layer, and between the metal oxide layer and a second insulating layer, wherein the pair of second regions sandwich the first region and overlap with the insulating region and the conductive layer in order to provide the advantage of providing a “U” shaped insulator as disclosed by Yamakawa to suppress the electric field on the active layer, improving reliability of the thin film transistor (Yamakawa, para [0005], [0107] and [0111]).
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Furthermore, the combination of Yamazaki, Tutt, and Yamakawa fails to disclose wherein the first insulating layer covers a top surface and a side surface of the semiconductor layer in a channel length direction.
Yamazaki does disclose a wherein the first insulating layer covers a top surface and a side surface of the semiconductor layer (110, Fig. 15B depicts wherein first insulating layer 110 covers the top and side of semiconductor layer portion 108i).
However, Miyairi teaches a semiconductor device comprising, a first insulating layer (160, Fig. 2B, column 24, lines 57-59, describe a gate insulating film) covers a top surface and a side surface of the semiconductor layer (130, Fig. 2B, column 8, lines 53-56, describe an oxide semiconductor 130 comprised of three layers 131, 132, 133) in a channel length direction (Fig. 2B, and Fig. 2C, column 8, lines 43-44, and column 24, lines 57-59, describe a gate insulating film 160 covering the oxide semiconductor 133 on a top and side surface in a channel length direction).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Yamazaki and Tutt and Yamakawa with Miyairi to further disclose a first insulating layer covering a top surface and a side surface of the semiconductor layer in a channel length direction in order to provide the advantage of preventing impurity elements from reaching the semiconductor layers, improving reliability of the semiconductor device (Miyairi, Column 9, lines 16-20).
Regarding Claim 2, the combination of Yamazaki, Tutt, Yamakawa, and Miyairi teach the semiconductor device according to claim 1, further comprising wherein the insulating region (Yamakawa, 33L, Fig. 21, para [0125], wherein the insulating region is described as a low-dielectric constant section) has a relative dielectric constant different from a relative dielectric constant of the first insulating layer (Yamakawa, para [0126] and para [0129], describes the differing dielectric constant relaxes the electric field of the device, improving reliability).
Regarding Claim 3, the combination of Yamazaki, Tutt, Yamakawa, and Miyairi teach the semiconductor device according to claim 1, further comprising wherein the insulating region comprises a gap (Yamakawa, 33L, Fig. 21, para [0126] and para [0129], describes that the low-dielectric constant section 33L of the gate insulating film 33 may be formed of, air, in other words, an air gap, which relaxes the electric field of the device, improving reliability).
Regarding Claim 5, the combination of Yamazaki, Tutt, Yamakawa, and Miyairi teach the semiconductor device according to claim 1, wherein the first insulating layer comprises an oxide or a nitride (Yamazaki, para [0236] describes wherein first insulating layer 110 may be comprised of an oxide or nitride), and wherein the second insulating layer comprises an oxide or a nitride (Yamazaki, para [0246] describes wherein the second insulating layer may comprise silicon nitride oxide).
Regarding Claim 6, the combination of Yamazaki, Tutt, Yamakawa, and Miyairi teach the semiconductor device according to claim 1, wherein the first insulating layer comprises silicon and oxygen (Yamazaki, para [0236] describes wherein first insulating layer 110 may comprise a silicon oxide film), and wherein the second insulating layer comprises silicon and oxygen (Yamazaki, para [0246] describes wherein second insulating layer 116 may comprise silicon oxynitride).
Regarding Claim 7, the combination of Yamazaki, Tutt, Yamakawa, and Miyairi teach the semiconductor device according to claim 1, wherein the first insulating layer comprises silicon and oxygen (Yamazaki, para [0236] describes wherein first insulating layer 110 may comprise a silicon oxide film), and wherein the second insulating layer comprises silicon and nitrogen (Yamazaki, para [0246] describes wherein second insulating layer 116 may comprise silicon oxynitride).
Regarding Claim 8, the combination of Yamazaki, Tutt, Yamakawa, and Miyairi teach the semiconductor device according to claim 1, further comprising a third insulating layer (Yamazaki, 118, Fig. 15A, para [0141] describes a third insulating film 118), wherein the third insulating layer is in contact with a top surface of the second insulating layer (Yamazaki, Fig. 15A depicts wherein third insulating layer 118 is in contact with a top surface of the second insulating layer 116), and wherein the third insulating layer comprises a nitride (Yamazaki, para [0247] describes wherein third insulating film 118 may be comprised of silicon nitride oxide).
Regarding Claim 9, the combination of Yamazaki, Tutt, Yamakawa, and Miyairi teach the semiconductor device according to claim 8, wherein the third insulating layer comprises silicon and nitrogen (Yamazaki, para [0247] describes wherein third insulating film 118 may be comprised of silicon nitride oxide).
Regarding Claim 11, the combination of Yamazaki, Tutt, Yamakawa, and Miyairi teach the semiconductor device according to claim 1, wherein each of the semiconductor layer and the metal oxide layer comprises indium (Yamazaki, 112_1 and 108, Fig. 15A, para [0268] describes wherein the metal oxide layer 112_1 may comprise an oxide conductive film containing indium, gallium and zinc and para [0310] describes wherein the semiconductor layer 108 may be an oxide semiconductor film formed using a metal oxide comprising indium, gallium and zinc).
The combination of Yamazaki, Tutt, Yamakawa, and Miyairi fail to explicitly disclose wherein the semiconductor layer has an indium content percentage that is substantially equal to an indium content percentage of the metal oxide layer.
However, Yamazaki does describe changing the atomic ratio of indium in the semiconductor layer 108 in para [0310] and para [0311].
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to try different atomic ratios of indium in the semiconductor layer form a finite number of possible atomic ratios resulting in a semiconductor device wherein the semiconductor layer has an indium content percentage that is substantially equal to an indium content percentage of the metal oxide layer in order to provide the well-known advantage match work functions which facilitates efficient charge injection and control of the transistor’s operation, as well as simplifying materials required for fabrication.
Regarding Claim 18, the combination of Yamazaki, Tutt, Yamakawa, and Miyairi teach the semiconductor device according to claim 1, wherein the metal oxide layer (Yamazaki, 112_1) is less likely to transmit oxygen and hydrogen than the first insulating layer (Yamazaki, 112_1 and 110, Fig. 15A, para [0236] describes a first insulating layer 110 wherein the first insulating layer may be comprised of silicon oxide such as described for the first insulating layer of the instant application and wherein para [0268] describes the second metal oxide layer may comprise a metal oxide material such as the metal oxide layer of the instant application wherein the structure recited in Yamazaki is substantially identical to that of the claims, therefore claimed properties or functions are presumed to be present (please see MPEP 2112.01 (I))).
Regarding Claim 20, the combination of Yamazaki, Tutt, Yamakawa, and Miyairi teach the semiconductor device according to claim 1, wherein the metal oxide layer comprises a crystallinity (Yamazaki, 112_1, Fig. 15A, para [0268] and para [0112] describes a crystal structure of a metal oxide such as found in metal oxide layer 112_1 wherein said crystal structure will comprise a crystallinity).
Regarding Claim 21, the combination of Yamazaki, Tutt, Yamakawa, and Miyairi teach the semiconductor device according to claim 1, wherein the third regions each comprise a first element (Yamazaki, 108s and 108d, Fig. 15A, para [0146] describes source and drain regions 108s and 108d comprising a first element), and wherein the first element is one or more selected from boron, phosphorus, aluminum, and magnesium (Yamazaki, 108s and 108d, Fig. 15A, para [0146] describes wherein source and drain regions 108s and 108d comprise a first element such as boron or phosphorous).
Regarding Claim 24, the combination of Yamazaki, Tutt, Yamakawa, and Miyairi discloses all the limitations of claim 1.
Yamazaki fails to explicitly disclose the semiconductor device according to claim 1, wherein a lower end portion of the metal oxide layer is on an inner side than an upper end portion of the metal oxide layer.
However, Miyairi teaches a similar semiconductor device wherein a lower end portion of the metal oxide layer (171 and LEP, annotated Fig. 2B, column 9, lines 7-20 describe wherein a metal oxide layer is formed between conductive film 170 and surrounding gate insulating film 160 and insulating film 180 wherein said metal oxide layer would comprise a lower end portion LEP as shown in annotated Fig. 2B) is on an inner side than an upper end portion of the metal oxide layer (171 and UEP, annotated Fig. 2B, column 9, lines 7-20 describe wherein a metal oxide layer is formed between conductive film 170 and surrounding gate insulating film 160 and insulating film 180 wherein said metal oxide layer would comprise an upper end portion LEP as shown in annotated Fig. 2B wherein lower end portion LEP is on an inner side than an upper end portion UEP of the metal oxide layer).
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Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Yamazaki, Tutt, and Yamakawa with Miyairi to further disclose a semiconductor device comprising lower end portions of a metal oxide layer on an inner side of upper end portions of a metal oxide layer in order to provide the advantage of providing a metal oxide layer that conforms to the shape of a gate conductive film so as to prevent Cu in the Cu-X gate conductive film from reaching the oxide semiconductor layer through surrounding insulating films which would decrease the semiconductor device reliability (Miyairi, column 9, lines 7-20).
Claims 12, 14-15, 17, 19 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki et al. (US 2017/0236844 A1; hereinafter “Yamazaki”) in view of Yamakawa et al. (US 2016/0020327 A1; hereinafter “Yamakawa”), in further view of Tutt et al. (US 2012/0178225 A1; hereinafter “Tutt”).
Regarding Claim 12, Yamazaki discloses a method for manufacturing a semiconductor device comprising:
forming a semiconductor layer (108, Fig. 15A, para [0139] describes an oxide semiconductor film 108 which is formed);
forming a first insulating layer over and in contact with the semiconductor layer (110, Fig. 15A, para [0145] describes forming an insulating film 110 over the semiconductor layer 108 wherein insulating film 110 can be seen in contact with semiconductor layer 108 in Fig. 15A and Fig. 15B);
forming a first metal oxide layer over and in contact with the first insulating layer (112_1, Fig. 15A, para [0268] describes forming a metal oxide layer 112_1 wherein first metal oxide layer 112_1 can be seen in contact with first insulating film 110 in Fig. 15A and Fig. 15B);
forming a first conductive layer over and in contact with the first metal oxide layer (112_2, Fig. 15A, para [0274] describes forming a first conductive film 112_2 over metal oxide layer 112_1 wherein first conductive layer 112_2 can be seen in contact with first metal oxide layer 112_1 in Fig. 15A and Fig. 15B); and
etching the first metal oxide layer and the first conductive layer to form a second metal oxide layer, a second conductive layer (para [0274] describes etching first metal oxide layer 112_1 and first conductive layer 112_1); and
forming a second insulating layer over and in contact with the first insulating layer and a top surface and a side surface of the second conductive layer (116, Fig. 15A, para [0139] describes forming a second insulating film layer 116 wherein Fig. 15A and Fig. 15B depicts the second insulating layer 116 is over the first insulating layer 110 and in contact with at least a side portion of the first insulating layer 110 and wherein the second insulating layer 116 is over and in contact with a top surface and a side surface of the second conductive layer 112_2),
wherein the first metal oxide layer comprises the same material as the semiconductor layer (112_1 and 108, Fig. 15A, para [0268] describes wherein the metal oxide layer 112_1 may comprise an oxide conductive film containing indium, gallium and zinc and para [0310] describes wherein the semiconductor layer 108 may be an oxide semiconductor film formed using a metal oxide comprising indium, gallium and zinc wherein both the metal oxide layer 112_1 and the semiconductor layer 108 may be comprised of the same indium, gallium and zinc material layers).
Yamazaki fails to explicitly disclose a method for manufacturing a semiconductor device comprising an insulating region.
However, Yamakawa teaches a method for forming a semiconductor device comprising an insulating region (33L, Fig. 27, para [0129] describes a low-dielectric constant section 33L forming an insulating region).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Yamazaki with Yamakawa to further disclose a method for manufacturing a semiconductor device comprising an insulating region in order to provide the advantage of relaxing the electric field generated in a portion close to the low-dielectric constant section (Yamakawa, para [0129]).
The combination of Yamazaki and Yamakawa fail to explicitly disclose the method for manufacturing a semiconductor device, wherein an etching rate of the first metal oxide layer is higher than an etching rate of the first conductive layer and wherein an end portion of the second metal oxide layer is on an inner side than an end portion of the second conductive layer.
However, Tutt teaches a method of producing a transistor, wherein an etching rate of the first metal oxide layer (120, Fig. 2, para [0026] and [0034], describes a first electrically conductive material layer which can be comprised of metal oxide materials including indium) is higher than an etching rate of the first conductive layer (130, Fig. 2, para [0026], [0028], and [0034], describes a second electrically conductive material layer, functioning as a gate electrode, which can be comprised of any suitable gate materials including indium, wherein the etching rate of the first electrically conductive material layer (first metal oxide layer) is faster than the second electrically conductive material layer (first conductive layer)), and
Wherein an end portion of the second metal oxide layer (120, Fig. 1, para [0026] and [0034], describes a first electrically conductive material layer which can be comprised of metal oxide materials including indium, wherein the first electrically conductive layer 120 as seen in figure 1 is a result of the etching process yielding a second metal oxide layer) is on an inner side than an end portion of the second conductive layer (130, 180, Fig. 1, para [0026], [0028], and [0034], describes a second electrically conductive material layer, functioning as a gate electrode, which can be comprised of any suitable gate materials including indium, wherein the second electrically conductive layer 130 as seen in figure 1 is a result of the etching process yielding a second conductive layer, wherein the overhang 180 demonstrates the end portion of the second metal oxide layer 120 is on an inner side than an end portion of the second conductive layer 130).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Yamazaki and Yamakawa with Tutt to further disclose a method for manufacturing a semiconductor device wherein an etching rate of the first metal oxide layer is higher than an etching rate of the first conductive layer and wherein an end portion of the second metal oxide layer is on an inner side than an end portion of the second conductive layer in order to provide the advantage of providing an etch rate used to create a reentrant profile resulting in an end portion of the metal oxide layer being on an inner side of an end portion of the second conductive layer creating an overhang which shortens the channel path and provides the advantage of reducing or preventing ungated regions in the transistor (Tutt, para [0020] and para [0026]).
Regarding Claim 14, the combination of Yamazaki, Yamakawa, and Tutt teach the method for manufacturing a semiconductor device according to claim 12, wherein the insulating region has a relative dielectric constant different from a relative dielectric constant of the first insulating layer (Yamakawa, 33L, Fig. 27, para [0128] describes an insulating region 33L described as a low-dielectric constant section compared to the gate insulating film 33 functioning as a first insulating layer).
Regarding Claim 15, the combination of Yamazaki, Yamakawa, and Tutt teach the method for manufacturing a semiconductor device according to claim 12, wherein the insulating region comprises a gap (Yamakawa, 33L, Fig. 27, para [0128] describes forming an air gap in the insulating region 33L called the low-dielectric constant section).
Regarding Claim 17, the combination of Yamazaki, Yamakawa, and Tutt teach the method for manufacturing a semiconductor device according to claim 12, further comprising, forming a third insulating layer (Yamazaki, 118, Fig. 15A, para [0141] describes providing a third insulating layer 118) in contact with a top surface of the second insulating layer (Yamazaki, 118, Fig. 15A depicts third insulating layer 118 in contact with a top surface of the second insulating layer 116), wherein the third insulating layer comprises a nitride (Yamazaki, 118, Fig. 15A, para [0247] describes wherein third insulating layer 118 may comprise silicon nitride oxide).
Regarding Claim 19, the combination of Yamazaki, Yamakawa, and Tutt teach the method for manufacturing a semiconductor device according to claim 12, wherein the second metal oxide layer (Yamazaki, 112_1, Fig. 15A, para [0268] describes a second metal oxide layer 112_1 after an etching process) is less likely to transmit oxygen and hydrogen than the first insulating layer (Yamazaki, 112_1 and 110, Fig. 15A, para [0236] describes a first insulating layer 110 wherein the first insulating layer may be comprised of silicon oxide such as described for the first insulating layer of the instant application and wherein para [0268] describes the second metal oxide layer may comprise a metal oxide material such as the metal oxide layer of the instant application wherein the structure recited in Yamazaki is substantially identical to that of the claims, therefore claimed properties or functions are presumed to be present (please see MPEP 2112.01 (I))).
Regarding Claim 22, the combination of Yamazaki, Yamakawa, and Tutt teach the method for manufacturing a semiconductor device according to claim 12, wherein the first metal oxide layer comprises a crystallinity (Yamazaki, 112_1, Fig. 15A, para [0268] and para [0112] describes a crystal structure of a metal oxide such as found in metal oxide layer 112_1 wherein said crystal structure will comprise a crystallinity).
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki et al. (US 2017/0236844 A1; hereinafter “Yamazaki”) in view of Yamakawa et al. (US 2016/0020327 A1; hereinafter “Yamakawa”), in further view of Tutt et al. (US 2012/0178225 A1; hereinafter “Tutt”), and further in view of Ishikawa et al. (US 2016/0299376 A1; hereinafter “Ishikawa”).
Regarding Claim 23, the combination of Yamazaki, Yamakawa, and Tutt disclose all the limitations of claim 12.
Yamazaki, Yamakawa and Tutt fail to explicitly disclose the method for manufacturing a semiconductor device according to claim 12, further comprising: adding a first element to the semiconductor layer through the first insulating layer after etching the first metal oxide layer and the first conductive layer, wherein the first element is one or more selected from boron, phosphorus, aluminum, and magnesium.
However, Ishikawa discloses a similar method for manufacturing a semiconductor device, further comprising:
adding a first element to the semiconductor layer (23, Fig. 1, para [0081] describes a semiconductor layer 23 which is doped with a first impurity element) through the first insulating layer after etching the first metal oxide layer and the first conductive layer (23 and 24, Fig. 1, para [0081] describes doping the first impurity element in to the semiconductor layer 23 through a first insulating layer 24 wherein the step of doping the semiconductor layer may occur after an etching process wherein the etching process may comprise the etching process of the first metal oxide layer and first conductive layer of Yamazaki),
wherein the first element is one or more selected from boron, phosphorus, aluminum, and magnesium (para [0081] describes wherein the first element may be boron).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Yamazaki, Yamakawa and Tutt with Ishikawa to further disclose a method for manufacturing a semiconductor device wherein the first semiconductor layer is doped with an impurity element such as boron in order to provide the advantage of providing an efficient means of doping the semiconductor layer with boron in order to control a threshold voltage of the TFT (Ishikawa, para [0081]).
Claims 1-3, 5-9, 11, 18 and 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over Bae (US 5742363 A; hereinafter “Bae”), in view of Liao et al. (US 2010/0133544 A1; hereinafter “Liao”), and in further view of Yamazaki et al. (US 2017/0236844 A1; hereinafter “Yamazaki”).
Regarding Claim 1, Bae discloses a semiconductor device comprising:
a semiconductor layer (3a, Fig. 5A and Fig. 5H, column 4, lines 33-37, describe an active layer 3a with source and drain regions);
a first insulating layer over and in contact with the semiconductor layer (4, Fig. 5A and Fig. 5H, column 4, line 61-64 describe a gate insulating layer 4 which can be seen as over and in contact with semiconductor layer 3a in Fig. 3);
a metal layer over and in contact with the first insulating layer (5a, Fig. 5C and Fig. 5H, column 4, line 38, describe a lower gate electrode 5a which can be seen as over and in contact with the first insulating layer 4 in Fig. 5C);
a conductive layer in contact with the metal layer (5b, Fig. 5C and Fig. 5H, column 4, line 38, describe an upper gate electrode 5b which can be seen in contact with metal layer 5a in Fig. 3);
a second insulating layer over and in contact with the first insulating layer and the conductive layer (7, Fig. 5E and Fig. 5H, column 4, lines 38-41 describe an interlayer insulating layer 7 which is over and in contact with the first insulating layer 4a and the conductive layer 5b as shown in Fig. 3); and
wherein the first insulating layer covers a top surface and a side surface of the semiconductor layer in a channel length direction (4, Fig. 5A and Fig. 5H, column 4, line 61-64 describe a gate insulating layer 4 which can be seen covering a top surface and a side surface of the semiconductor layer 3a in a channel length direction as shown in Fig. 5H), and
wherein the second insulating layer covers the first insulating layer and a top surface and a side surface of the conductive layer (7, Fig. 5E and Fig. 5H, column 4, lines 38-41 describe the interlayer insulating layer 7 which covers at least a top surface and a side surface of the first insulating layer 4 and a top surface and a side surface of the conductive layer 5b as shown in Fig. 3),
wherein the conductive layer is over the first insulating layer (5b, Fig. 5C and Fig. 5H, column 4, lines 37-39, describes a first insulating layer 4, then a lower gate electrode 5a, and then upper gate electrode 5b being sequentially formed resulting in the conductive layer 5a being over the first insulating layer 4)
wherein the metal layer is between the first insulating layer and the conductive layer (5a, Fig. 5C and Fig. 5H, column 4, lines 37-39 describe wherein the metal layer 5a is between the first insulating layer 4 and the conductive layer 5b),
wherein an end portion of the metal layer is on an inner side than an end portion of the conductive layer (5b, Fig. 5C and Fig. 5H, column 4, lines 46-51, describes the conductive layer 5b, being wider than the metal layer 5a, thus resulting in an end portion of the metal layer 5a being on an inner side than an end portion of the conductive layer 5b as seen in Fig. 3).
wherein the semiconductor layer comprises a first region (FR and 3a, annotated Fig. 5H, column 4, lines 34-37, describe a channel region 3a comprising a first region FR), a pair of second regions (10, Fig. 3, column 4, lines 34-37, describe an offset region 10), and a pair of third regions (TR and 3a, annotated Fig. 5H, column 4, lines 34-37, describe a source and drain region of the semiconductor layer 3a comprising third regions TR),
wherein the first region overlaps with the metal layer and the conductive layer (FR, annotated Fig. 5H depicts wherein first region FR overlaps with metal layer 5a and conductive layer 5b),
wherein the pair of second regions sandwich the first region and overlap with the conductive layer (10, Fig. 3 depicts wherein offset regions 10 comprising a pair of second regions sandwich the first region and overlap with the conductive layer 5b
wherein the pair of third regions are sandwich the first region and the pair of second regions (TR, annotated Fig. 5H depicts wherein the pair of third regions TR sandwich the first region FR and pair of second regions 10) and do not overlap with the conductive layer (TR and 5b, annotated Fig. 5H, column 7, lines 14-19, describes the second region 10 being the width of the difference between the conductive layer 5b and metal layer 5a, resulting in the third region TR not overlapping with conductive layer 5b),
wherein the third regions each comprise a portion having lower resistance than the first region (TR, annotated Fig. 5H, column 5, lines 36-39, describes the third regions TR being source and drain regions formed though ion-doping, wherein it is known in the art that the source and drain regions would have lower resistance than the first region, or channel region), and
wherein the second regions each comprise a portion having higher resistance than the third regions (10, Fig. 3, column 8, lines 26-30, describes the offset regions 10 as LDD or lightly doped drain regions, which are well known in the art to have a higher resistance than the source and drain regions).
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Bae fails to explicitly disclose an insulating region, and wherein the insulating region is adjacent to the metal oxide layer, between the first insulating layer and the conductive layer, and between the metal oxide layer and the second insulating layer, and wherein the pair of second regions overlap with the insulating region, and wherein the metal layer comprises a metal oxide.
However, Liao teaches a similar semiconductor device
an insulating region (C, Fig. 2E, para [0040], describes recesses R that become cavities C, wherein the cavities are vacuum cavities with a dielectric constant substantially equal to 1, acting as an insulating region)
wherein the insulating region (C, Fig. 2E, para [0040]) is adjacent to the metal oxide layer (240b, Fig. 2E, para [0030] describes a first conductive layer 240a that may be comprised of a metal oxide ITO), between the first insulating layer (230, Fig. 2E, para [0043] describes a gate insulating layer 230), and the conductive layer (240b, Fig. 2E, para [0033] describes a second conductive layer 240b wherein Fig. 2E depicts the insulating region C being adjacent to the metal oxide layer 240a, and between the first insulating layer 230 and the second conductive layer 240b), and between the metal oxide layer and the second insulating layer (250, Fig. 2E, para [0039] describes a dielectric layer 250 wherein the insulating region C is between the metal oxide layer 240a and the second insulating layer 250), and
wherein the second regions are configured to put the first region therebetween and to overlap with the insulating region and the conductive layer (upon modifying Bae with the insulating region of Liao, the region of the insulating layer 7 that overlaps with the offset region 10 of Bae, will be comprised of the insulating region C of Liao, overlapping the insulating region C of Liao with the offset region 10 of Bae), and
wherein the metal comprises a metal oxide (240a, Fig. 2E, para [0030], describes the first conductive layer 240a is made of ITO (indium tin oxide) which is a metal oxide).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Bae with Liao to disclose a semiconductor device comprising an insulating region, and wherein the insulating region is adjacent to a metal oxide layer, between a first insulating layer and a conductive layer, and between the metal oxide layer and a second insulating layer, and wherein a pair of second regions overlap with the insulating region in order to provide the advantage of providing an insulating region which may resolve the problem of the short channel effect by reducing leakage current in the TFT device (Liao, para [0009] and para [0021]) and to further disclose wherein a metal layer comprises a metal oxide in order to provide the advantage of providing an etch selectivity with respect to a metal oxide layer and an overlying conductive layer so that a recess may be formed to provide an insulating region (Liao, para [0031]).
The combination of Bae and Liao fail to explicitly disclose wherein the metal oxide layer comprises the same material as the semiconductor layer.
However, Yamazaki teaches a similar semiconductor device wherein the metal oxide layer comprises the same material as the semiconductor layer (112_1 and 108, Fig. 15A, para [0268] describes wherein the metal oxide layer 112_1 may comprise an oxide conductive film containing indium, gallium and zinc and para [0310] describes wherein the semiconductor layer 108 may be an oxide semiconductor film formed using a metal oxide comprising indium, gallium and zinc wherein both the metal oxide layer 112_1 and the semiconductor layer 108 may be comprised of the same indium, gallium and zinc material layers).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Bae and Liao with Yamazaki to disclose a semiconductor device wherein the metal oxide layer comprises the same material as the semiconductor layer in order to provide the well-known advantage of providing a same material for multiple layers in a semiconductor device simplifying a device manufacturing process and reducing manufacturing costs through the reduction of materials needed during manufacturing,
Regarding Claim 2, the combination of Bae, Liao and Yamazaki teach the semiconductor device according to claim 1, further comprising wherein the insulating region has a relative dielectric constant different from a relative dielectric constant of the first insulating layer (Liao, C, Fig. 2E para [0046], describes the dielectric constant of the insulating region C, to be substantially equal to one, while the first insulating layer 230, has a relatively high dielectric constant).
Regarding Claim 3, the combination of Bae, Liao and Yamazaki teach the semiconductor device according to claim 1, further comprising wherein the insulating region comprises a gap (Liao, C, Fig. 2E, para [0046], describes wherein the dielectric constant of the insulating region C is substantially equal to one, wherein the dielectric constant of air is substantially equal to one, therefore the insulating region of Liao comprises a gap).
Regarding Claim 5, the combination of Bae, Liao and Yamazaki teach the semiconductor device according to claim 1, wherein the first insulating layer comprises an oxide or a nitride (Bae, Fig. 5H, column 6, lines 16-17, describes wherein the first insulating layer 4 may comprise a silicon oxide), and wherein the second insulating layer comprises an oxide or a nitride (Bae, 7, Fig. 5H, column 6, lines 16-17, describes the second insulating layer 7 may comprise a silicon nitride).
Regarding Claim 6, the combination of Bae, Liao and Yamazaki teach the semiconductor device according to claim 1, wherein the first insulating layer comprises silicon and oxygen (Bae, 4, Fig. 5H, column 6, lines 16-17, describes wherein the first insulating layer 4 may comprise a silicon oxide).
Bae fails to explicitly disclose wherein the second insulating layer comprises silicon and oxygen.
However, Yamazaki teaches a similar semiconductor device, wherein the second insulating layer comprises silicon and oxygen (Yamazaki, para [0246] describes wherein second insulating layer 116 may comprise silicon oxynitride).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Bae and Liao with Yamazaki to explicitly disclose wherein the second insulating layer may comprise silicon and oxygen in order to provide the advantage of increasing the carrier density in the source and drain regions in contact with the second insulating layer (Yamazaki, para [0246]).
Regarding Claim 7, the combination of Bae, Liao and Yamazaki teach the semiconductor device according to claim 1, wherein the first insulating layer comprises silicon and oxygen (Bae, 4, Fig. 5H, column 6, lines 16-17, describes wherein the first insulating layer 4 may comprise a silicon oxide), and wherein the second insulating layer comprises silicon and nitrogen (Bae, 7, Fig. 5H, column 6, lines 16-17, describes the second insulating layer 7 may comprise a silicon nitride).
Regarding Claim 8, the combination of Bae, Liao and Yamazaki teach the semiconductor device according to claim 1, further comprising a third insulating layer (Yamazaki, 118, Fig. 15A, para [0141] describes a third insulating layer 118), wherein the third insulating layer is in contact with a top surface of the second insulating layer (Yamazaki, Fig. 15A depicts third insulating layer 118 in contact with a top surface of second insulating layer 116), and wherein the third insulating layer comprises a nitride (Yamazaki, para [0247] describes wherein third insulating layer 118 may comprise a silicon nitride oxide).
Regarding Claim 9, the combination of Bae, Liao and Yamazaki teach the semiconductor device according to claim 8, wherein the third insulating layer comprises silicon and nitrogen (Yamazaki, para [0247] describes wherein third insulating layer 118 may comprise a silicon nitride oxide).
Regarding Claim 11, the combination of Bae, Liao and Yamazaki teach the semiconductor device according to claim 1, wherein each of the semiconductor layer and the metal oxide layer comprises indium (Yamazaki, 112_1 and 108, Fig. 15A, para [0268] describes wherein the metal oxide layer 112_1 may comprise an oxide conductive film containing indium, gallium and zinc and para [0310] describes wherein the semiconductor layer 108 may be an oxide semiconductor film formed using a metal oxide comprising indium, gallium and zinc).
The combination of Bae, Liao and Yamazaki fail to explicitly disclose wherein the semiconductor layer has an indium content percentage that is substantially equal to an indium content percentage of the metal oxide layer.
However, Yamazaki does describe changing the atomic ratio of indium in the semiconductor layer 108 in para [0310] and para [0311].
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to try different atomic ratios of indium in the semiconductor layer form a finite number of possible atomic ratios resulting in a semiconductor device wherein the semiconductor layer has an indium content percentage that is substantially equal to an indium content percentage of the metal oxide layer in order to provide the well-known advantage match work functions which facilitates efficient charge injection and control of the transistor’s operation, as well as simplifying materials required for fabrication.
Regarding Claim 18, the combination of Bae, Liao and Yamazaki teach the semiconductor device according to claim 1, wherein the metal oxide layer (Yamazaki, 112_1) is less likely to transmit oxygen and hydrogen than the first insulating layer (Yamazaki, 112_1 and 110, Fig. 15A, para [0236] describes a first insulating layer 110 wherein the first insulating layer may be comprised of silicon oxide such as described for the first insulating layer of the instant application and wherein para [0268] describes the second metal oxide layer may comprise a metal oxide material such as the metal oxide layer of the instant application wherein the structure recited in Yamazaki is substantially identical to that of the claims, therefore claimed properties or functions are presumed to be present (please see MPEP 2112.01 (I))).
Regarding Claim 20, the combination of Bae, Liao and Yamazaki teach the semiconductor device according to claim 1, wherein the metal oxide layer comprises a crystallinity (Yamazaki, 112_1, Fig. 15A, para [0268] and para [0112] describes a crystal structure of a metal oxide such as found in metal oxide layer 112_1 wherein said crystal structure will comprise a crystallinity).
Regarding Claim 21, the combination Bae, Liao and Yamazaki disclose all the limitations of claim 1.
Bae fails to explicitly disclose wherein the third regions each comprise a first element, and wherein the first element is one or more selected from boron, phosphorus, aluminum, and magnesium.
However, Yamazaki teaches a similar semiconductor device wherein the third regions each comprise a first element (Yamazaki, 108s and 108d, Fig. 15A, para [0146] describes source and drain regions 108s and 108d comprising a first element), and wherein the first element is one or more selected from boron, phosphorus, aluminum, and magnesium (Yamazaki, 108s and 108d, Fig. 15A, para [0146] describes wherein source and drain regions 108s and 108d comprise a first element such as boron or phosphorous).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Bae and Liao with Yamazaki to explicitly disclose wherein the third regions comprise one or more of boron, phosphorus, aluminum, and magnesium in order to provide the advantage of cutting a bond between a metal element and oxygen in the semiconductor layer or oxygen is bonded to the impurity element so that an oxygen vacancy is formed, creating a higher carrier density and increasing conductivity in the semiconductor device (Yamazaki, para [0148]).
Claims 12, 14-15, 17, 19 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Bae (US 5742363 A; hereinafter “Bae”), in view of Liao et al. (US 2010/0133544 A1; hereinafter “Liao”), in further view of Yamazaki et al. (US 2017/0236844 A1; hereinafter “Yamazaki”).
Regarding Claim 12, Bae teaches a method for manufacturing a semiconductor device comprising:
forming a semiconductor layer (3, Fig. 5A, column 6, lines 49-52, describe forming a semiconductor layer 3);
forming a first insulating layer over and in contact with the semiconductor layer (4, Fig. 5B, column 6, line 53-57, describes forming an insulating layer 4 over and in contact with the semiconductor layer 3);
forming a first metal layer over and in contact with the first insulating layer (5c, Fig. 5B, column 6, line 55-57 describes forming a first metal layer 5c over and in contact with the first insulating layer 4);
forming a first conductive layer over and in contact with the first metal oxide layer (5d, Fig. 5B, column 6, line 55-57 describes forming a first conductive layer 5d over and in contact with the first metal layer 5c); and
etching the first metal oxide layer and the first conductive layer to form a second metal oxide layer (5a, Fig. 5C, column 6, lines 60-67 describe etching the first metal layer 5c to form a second metal layer 5a), and a second conductive layer (5b, Fig. 5C, column 6, lines 60-67 describe etching the first conductive layer 5d to form a second conductive layer 5b); and
forming a second insulating layer over and in contact with the first insulating layer and a top surface and a side surface of the second conductive layer (7, Fig. 5E, column 7, lines 22-32 describe forming a second insulating layer 7 over and in contact with the first insulating layer 4 and a top surface and a side surface of the second conductive layer 5b),
wherein an end portion of the second metal layer is on an inner side than an end portion of the second conductive layer (5a, Fig. 5C, column 6, lines 58-67 describe the process of etching wherein the resulting shape is shown in Fig. 5C, wherein an end portion of the second metal layer 5a is on an inner side than an end portion of the second conductive layer 5b).
Bae fails to disclose wherein the metal layer is comprised of a metal oxide, and further fails to disclose etching an insulating region, and wherein an etching rate of the first metal oxide layer is higher than an etching rate of the first conductive layer.
However, Liao teaches in Fig. 2E and related text, a related thin film transistor comprising:
wherein the metal layer is comprised of a metal oxide (240a, Fig. 2E, para [0030] describes wherein the first conductive layer 240a is made of ITO (indium tin oxide) which is a metal oxide), and
etching an insulating region (C, Fig. 2E, para [0040], describes etching recesses R that become cavities C, wherein the cavities are vacuum cavities with a dielectric constant substantially equal to 1 forming an insulating region) and,
wherein an etching rate of the first metal oxide layer is higher than an etching rate of the first conductive layer (para [0013], describes where an etching rate of the first metal oxide layer 240a is at least twice an etching rate of the first conductive layer 240b).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Bae with Liao to disclose a method for manufacturing a semiconductor device comprising etching an insulating region, and wherein an etching rate of the first metal oxide layer is higher than an etching rate of the first conductive layer in order to provide the advantage of providing an insulating region which may resolve the problem of the short channel effect by reducing leakage current in the TFT device (Liao, para [0009] and para [0021]) and to further disclose wherein a metal layer comprises a metal oxide in order to provide the advantage of providing an etch selectivity with respect to a metal oxide layer and an overlying conductive layer so that a recess may be formed to provide an insulating region (Liao, para [0031]).
The combination of Bae and Liao fail to explicitly disclose wherein the metal oxide layer comprises the same material as the semiconductor layer.
However, Yamazaki teaches a similar semiconductor device wherein the metal oxide layer comprises the same material as the semiconductor layer (112_1 and 108, Fig. 15A, para [0268] describes wherein the metal oxide layer 112_1 may comprise an oxide conductive film containing indium, gallium and zinc and para [0310] describes wherein the semiconductor layer 108 may be an oxide semiconductor film formed using a metal oxide comprising indium, gallium and zinc wherein both the metal oxide layer 112_1 and the semiconductor layer 108 may be comprised of the same indium, gallium and zinc material layers).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Bae and Liao with Yamazaki to disclose a semiconductor device wherein the metal oxide layer comprises the same material as the semiconductor layer in order to provide the well-known advantage of providing a same material for multiple layers in a semiconductor device simplifying a device manufacturing process and reducing manufacturing costs through the reduction of materials needed during manufacturing.
Regarding Claim 14, the combination of Bae, Liao and Yamazaki teach the method for manufacturing a semiconductor device according to claim 12, wherein the insulating region (Liao, C, Fig. 2E, para [0040] describes an insulating region C), has a relative dielectric constant different from a relative dielectric constant of the first insulating layer (Liao, C and 230, Fig. 2E, para [0046] describes wherein the dielectric constant in the gate insulating layer 230 is relatively high, while the dielectric constant in the insulating region C, is substantially equal to one).
Regarding Claim 15, the combination of Bae, Liao and Yamazaki teach the method for manufacturing a semiconductor device according to claim 12, wherein the insulating region comprises a gap (Liao, C, Fig. 2E, para [0046], describes wherein the dielectric constant of the insulating region C is substantially equal to one, wherein the dielectric constant of air is substantially equal to one, therefore the insulating region C of Liao comprises a gap).
Regarding Claim 17, the combination of Bae, Liao and Yamazaki teach the method for manufacturing a semiconductor device according to claim 12, further comprising:
forming a third insulating layer (Yamazaki, 118, para [0141] describes providing a third insulating layer 118) in contact with a top surface of the second insulating layer (Yamazaki, 118 and 116 Fig. 15A depicts third insulating layer 118 in contact with a top surface of a second insulating layer 116),
wherein the third insulating layer comprises a nitride (Yamazaki, para [0247] describes wherein third insulating layer 118 may comprise silicon nitride oxide).
Regarding Claim 19, the combination of Bae, Liao and Yamazaki teach the method for manufacturing a semiconductor device according to claim 12, wherein the second metal oxide layer (Yamazaki, 112_1) is less likely to transmit oxygen and hydrogen than the first insulating layer (Yamazaki, 112_1 and 110, Fig. 15A, para [0236] describes a first insulating layer 110 wherein the first insulating layer may be comprised of silicon oxide such as described for the first insulating layer of the instant application and wherein para [0268] describes the second metal oxide layer may comprise a metal oxide material such as the metal oxide layer of the instant application wherein the structure recited in Yamazaki is substantially identical to that of the claims, therefore claimed properties or functions are presumed to be present (please see MPEP 2112.01 (I))).
Regarding Claim 22, the combination of Bae, Liao and Yamazaki teach the semiconductor device according to claim 12, wherein the first metal oxide layer comprises a crystallinity (Yamazaki, 112_1, Fig. 15A, para [0268] and para [0112] describes a crystal structure of a metal oxide such as found in metal oxide layer 112_1 wherein said crystal structure will comprise a crystallinity).
Claims 23 is rejected under 35 U.S.C. 103 as being unpatentable over Bae (US 5742363 A; hereinafter “Bae”), in view of Liao et al. (US 2010/0133544 A1; hereinafter “Liao”), in further view of Yamazaki et al. (US 2017/0236844 A1; hereinafter “Yamazaki”) and in further view Ishikawa et al. (US 2016/0299376 A1; hereinafter “Ishikawa”).
Regarding Claim 23, the combination of Bae, Liao and Yamazaki teach the semiconductor device according to claim 12, wherein a first element is one or more selected from boron, phosphorous, aluminum, and magnesium (para [0146] describes wherein source and drain regions 108s and 108d of semiconductor layer 108 comprise a first element such as boron or phosphorous).
Bae, Liao and Yamazaki fail to explicitly disclose adding a first element to the semiconductor layer through the first insulating layer after etching the first metal oxide layer and the first conductive layer.
However, Ishikawa discloses a similar method for manufacturing a semiconductor device, further comprising:
adding a first element to the semiconductor layer (23, Fig. 1, para [0081] describes a semiconductor layer 23 which is doped with a first impurity element) through the first insulating layer after etching the first metal oxide layer and the first conductive layer (23 and 24, Fig. 1, para [0081] describes doping the first impurity element in to the semiconductor layer 23 through a first insulating layer 24 wherein the step of doping the semiconductor layer may occur after an etching process wherein the etching process may comprise the etching process of the first metal oxide layer and first conductive layer of Bae),
wherein the first element is one or more selected from boron, phosphorus, aluminum, and magnesium (para [0081] describes wherein the first element may be boron).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Yamazaki, Yamakawa and Tutt with Ishikawa to further disclose a method for manufacturing a semiconductor device wherein the first semiconductor layer is doped with an impurity element such as boron in order to provide the advantage of providing an efficient means of doping the semiconductor layer with boron in order to control a threshold voltage of the TFT (Ishikawa, para [0081]).
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Bae (US 5742363 A; hereinafter “Bae”), in view of Liao et al. (US 2010/0133544 A1; hereinafter “Liao”), in further view of Yamazaki et al. (US PgPub 2017/0236844 A1) and in further view of Miyairi (US 9530856 B2; hereinafter “Miyairi”).
Regarding Claim 24, the combination of Bae, Liao and Yamazaki discloses all the limitations of claim 1.
Bae, Liao and Yamazaki fail to explicitly disclose the semiconductor device according to claim 1, wherein a lower end portion of the metal oxide layer is on an inner side than an upper end portion of the metal oxide layer.
However, Miyairi teaches a similar semiconductor device wherein a lower end portion of the metal oxide layer (171 and LEP, annotated Fig. 2B, column 9, lines 7-20 describe wherein a metal oxide layer is formed between conductive film 170 and surrounding gate insulating film 160 and insulating film 180 wherein said metal oxide layer would comprise a lower end portion LEP as shown in annotated Fig. 2B) is on an inner side than an upper end portion of the metal oxide layer (171 and UEP, annotated Fig. 2B, column 9, lines 7-20 describe wherein a metal oxide layer is formed between conductive film 170 and surrounding gate insulating film 160 and insulating film 180 wherein said metal oxide layer would comprise an upper end portion LEP as shown in annotated Fig. 2B wherein lower end portion LEP is on an inner side than an upper end portion UEP of the metal oxide layer).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Yamazaki, Tutt, and Yamakawa with Miyairi to further disclose a semiconductor device comprising lower end portions of a metal oxide layer on an inner side of upper end portions of a metal oxide layer in order to provide the advantage of providing a metal oxide layer that conforms to the shape of a gate conductive film so as to prevent Cu in the Cu-X gate conductive film from reaching the oxide semiconductor layer through surrounding insulating films which would decrease the semiconductor device reliability (Miyairi, column 9, lines 7-20).
Response to Arguments
Applicant's arguments filed 6 March 2026 have been fully considered but they are not persuasive.
The Applicant argues on page 10, lines 1-7 of the remarks that the combination of Yamazaki, Tutt, Yamanaka and Miyairi have not been shown to teach or suggest the clarified combination of features in independent claims 1 and 12 and further argues on page 11, lines 1-8 of the remarks that the combination of Bae, Liao, Yamazaki and Ishikawa have not been shown to teach or suggest the clarified combination of features in independent claims 1 and 12. The clarified combination can be found on page 7, lines 24-30 and page 8, lines 1-5 of the remarks disclosing the amendments to claim 1, wherein the first insulating layer is over and in contact with the semiconductor layer; the metal oxide layer is over and in contact with the first insulating layer; the conductive layer is in contact with the metal oxide layer; the second insulating layer is over and in contact with the first insulating layer and the conductive layer; the second insulating layer covers the first insulating layer and a top surface and a side surface of the conductive layer; the insulating region is adjacent to the metal oxide layer, between the first insulating layer and the conductive layer, and between the metal oxide layer and the second insulating layer; and the metal oxide layer comprises the same material as the semiconductor layer and page 8, lines 8-18 of the remarks disclosing the amendments to claim 12, wherein forming a first insulating layer over and in contact with the semiconductor layer; forming a first metal oxide layer over and in contact with the first insulating layer; forming a first conductive layer over and in contact with the first metal oxide layer; etching to form a second metal oxide layer, a second conductive layer, and an insulating region; forming a second insulating layer over and in contact with the first insulating layer and a top surface and a side surface of the second conductive layer; and wherein the first metal oxide layer comprises the same material as the semiconductor layer.
The Examiner respectfully disagrees. As indicated above, Yamazaki teaches a first insulating layer over and in contact with the semiconductor layer (110, Fig. 15A, para [0268] describes an insulating film 110 which can be seen as over and in contact with semiconductor layer 108 in Fig. 15A and Fig. 15B); a metal oxide layer over and in contact with the first insulating layer (112_1, Fig. 15A, para [0268] describes a metal oxide layer 112_1 which is over and in contact with the first insulating layer 110), a conductive layer in contact with the metal oxide layer(112_2, Fig. 15A, para [0268] describes a conductive film 112_2 which is describes as over the metal oxide layer 112_1 and is shown as being in contact with the metal oxide layer 112_1 in Fig. 15A and Fig. 15B); a second insulating layer over and in contact with the first insulating layer and the conductive layer (116, Fig. 15A, para [0139] describes a second insulating film layer 116 wherein Fig. 15A and Fig. 15B depicts the second insulating layer 116 is over the first insulating layer 110 and in contact with at least a side portion of the first insulating layer 110 and wherein the second insulating layer is over and in contact with the conductive layer 112_2); wherein the second insulating layer covers the first insulating layer and a top surface and a side surface of the conductive layer (116, Fig. 15A, para [0139] describes the second insulating film layer 116 wherein Fig. 15A and Fig. 15B depicts wherein the second insulating layer 116 covers at least side surfaces of the first insulating layer 110 and a top surface and a side surface of the conductive layer 112_2); and wherein the metal oxide layer comprises the same material as the semiconductor layer (112_1 and 108, Fig. 15A, para [0268] describes wherein the metal oxide layer 112_1 may comprise an oxide conductive film containing indium, gallium and zinc and para [0310] describes wherein the semiconductor layer 108 may be an oxide semiconductor film formed using a metal oxide comprising indium, gallium and zinc wherein both the metal oxide layer 112_1 and the semiconductor layer 108 may be comprised of the same indium, gallium and zinc material layers).
Yamakawa further teaches wherein the insulating region is adjacent to the metal oxide layer (IR, annotated Fig. 19, depicts wherein upon modifying Yamazaki with Yamakawa to add the insulating region IR as shown in annotated Fig. 19, Yamazaki’s metal oxide’s width will be reduced to an inner side than an end portion of the conductive layer wherein the insulating region IR will be adjacent to the metal oxide layer 112_1 of Yamazaki) between the first insulating layer and the conductive layer (see annotated Fig. 19 below), and between the metal oxide layer and the second insulating layer (15 and IR, annotated Fig. 19 depicts wherein upon modifying Yamazaki with Yamakawa to add the insulating region IR as shown in annotated Fig. 19, Yamazaki’s metal oxide’s width will be reduced to an inner side than an end portion of the conductive layer and the insulating region IR will be on either side of the metal oxide layer 112_1 of Yamazaki putting it between the high-resistance film 15 constituting a second insulating film of Yamakawa as described in para [0070] and between the metal oxide layer 112_1 and second insulating layer 116 of Yamazaki).
Furthermore, Bae teaches wherein a first insulating layer over and in contact with the semiconductor layer (4, Fig. 5A and Fig. 5H, column 4, line 61-64 describe a gate insulating layer 4 which can be seen as over and in contact with semiconductor layer 3a in Fig. 3); a metal layer over and in contact with the first insulating layer (5a, Fig. 5C and Fig. 5H, column 4, line 38, describe a lower gate electrode 5a which can be seen as over and in contact with the first insulating layer 4 in Fig. 5C); a conductive layer in contact with the metal layer (5b, Fig. 5C and Fig. 5H, column 4, line 38, describe an upper gate electrode 5b which can be seen in contact with metal layer 5a in Fig. 3); a second insulating layer over and in contact with the first insulating layer and the conductive layer (7, Fig. 5E and Fig. 5H, column 4, lines 38-41 describe an interlayer insulating layer 7 which is over and in contact with the first insulating layer 4a and the conductive layer 5b as shown in Fig. 3); and wherein the second insulating layer covers the first insulating layer and a top surface and a side surface of the conductive layer (7, Fig. 5E and Fig. 5H, column 4, lines 38-41 describe the interlayer insulating layer 7 which covers at least a top surface and a side surface of the first insulating layer 4 and a top surface and a side surface of the conductive layer 5b as shown in Fig. 3).
Liao further teaches wherein the insulating region (C, Fig. 2E, para [0040]) is adjacent to the metal oxide layer (240b, Fig. 2E, para [0030] describes a first conductive layer 240a that may be comprised of a metal oxide ITO), between the first insulating layer (230, Fig. 2E, para [0043] describes a gate insulating layer 230), and the conductive layer (240b, Fig. 2E, para [0033] describes a second conductive layer 240b wherein Fig. 2E depicts the insulating region C being adjacent to the metal oxide layer 240a, and between the first insulating layer 230 and the second conductive layer 240b), and between the metal oxide layer and the second insulating layer (250, Fig. 2E, para [0039] describes a dielectric layer 250 wherein the insulating region C is between the metal oxide layer 240a and the second insulating layer 250).
Conclusion
Applicant's amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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