Prosecution Insights
Last updated: July 17, 2026
Application No. 17/302,054

DEEP TRENCH ISOLATION STRUCTURE IN A PIXEL SENSOR

Non-Final OA §103
Filed
Apr 22, 2021
Examiner
HRNJIC, ADIN
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
7 (Non-Final)
66%
Grant Probability
Favorable
7-8
OA Rounds
0m
Est. Remaining
73%
With Interview

Examiner Intelligence

Grants 66% — above average
66%
Career Allowance Rate
38 granted / 58 resolved
-2.5% vs TC avg
Moderate +8% lift
Without
With
+7.8%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
27 currently pending
Career history
102
Total Applications
across all art units

Statute-Specific Performance

§103
93.3%
+53.3% vs TC avg
§102
3.5%
-36.5% vs TC avg
§112
3.2%
-36.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 58 resolved cases

Office Action

§103
Detailed Action This office action is in response to the request for continued examination filed on February 6th, 2026. Claims 1-3, 6-7, 14-21, and 25-31 are pending. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on February 6th, 2026, has been entered. Information Disclosure Statement The information disclosure statement (IDS) submitted on February 6th, 2026, was filed prior to the mailing date of the non-final rejection. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Response to Arguments Applicant's arguments filed February 6th, 2026, have been fully considered but they are not persuasive. Applicant argues (pgs. 10-12, “Remarks”) that Sze, Kim, and the other cited references fail to teach the limitations presented in amended Claims 1, 14, and 21. However, as seen below, Claims 1 and 14 are rejected by the combination of Sze, Lee, and Lim. Claim 21 is rejected by the combination of Sze and Lim. Therefore, applicant’s arguments are not persuasive and are moot in view of the new grounds of rejection. Applicant’s amendments have overcome the 35 U.S.C. 112(b) rejection of the previous office action. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Rejection Note: Italicized claim limitations indicate that the corresponding limitations are addressed with a secondary reference/embodiment in an obviousness analysis. Claims 1, 6-7, 14-16, 18, and 30-31 are rejected under 35 U.S.C. 103 as being unpatentable over Sze (U.S. 2020/0105812 A1; hereinafter Sze) in view of Lee (2009/0065831 A1; hereinafter Lee) and Lim et al. (2020/0119072 A1; hereinafter Lim). Regarding Claim 1, Sze (see fig. 16) teaches: A pixel sensor ([0073], 1600), comprising: a substrate ([0022], 103); a photodiode ([0031], 110) in the substrate (103); a drain region ([0028], 140) in the substrate (103); a deep trench isolation (DTI) structure ([0027], 156, 158) that extends through the substrate (103) on a first side of the substrate (bottom of 103, see fig. 16) and on a second side of the substrate (top of 103, see fig. 16), wherein the DTI structure (156, 158) surrounds (see fig. 16, 156 and 158 are on both sides of 110 and 140) the photodiode (110) and the drain region (140); a first dielectric layer ([0061], 134) on a coplanar surface (see fig. 8) of the first side of the substrate (bottom of 103) and on a first end of the DTI structure (bottom of 156, 158); a first oxide layer ([0064], 132) on the first dielectric layer (134); a second dielectric layer ([0029], 119, [0058], 610) over (fig. 16 is rotated by 180 degrees when compared to the claimed invention, so 119 and 610 can be interpreted to be over 132) the first oxide layer (132); a plurality of conductive structures ([0029], 126, [0058], 602, 604), spaced from each other (see fig. 16), in the second dielectric layer (119, 610); a plurality of absorption layers ([0038], [0017], 124 may be tantalum nitride, tantalum nitride absorbs light in a first wavelength range), spaced from each other (see fig. 16), in the second dielectric layer (119, 610), wherein a surface of the plurality of conductive structures and a surface of the plurality of absorption layers have a same length and reside coextensively on each other; a second oxide layer on a coplanar surface of the second side of the substrate and on a second end of the DTI structure, wherein the second end of the DTI structure is opposite from the first end of the DTI structure; a grid structure extending directly from the second oxide layer and aligned with the second end of the DTI structure wherein the grid structure comprises a first portion of the second oxide layer, wherein the first portion of the second oxide layer extends laterally from a second portion of the second oxide layer; and a third dielectric layer on the second oxide layer and around the grid structure, wherein the third dielectric layer resides directly on a top surface and side surfaces of the grid structure. Sze doesn’t explicitly teach a surface of the plurality of conductive structures and a surface of the plurality of absorption layers have a same length and reside coextensively on each other. However, Lee (fig. 6) teaches, in a similar image sensor, a surface of the plurality of conductive structures ([0015], 30 includes a bulk conductive layer made of aluminum or copper) and a surface of the plurality of absorption layers ([0015], 30 includes barrier layers made of tantalum nitride) have a same length and reside coextensively on each other (see fig. 6). Lee teaches that the interconnection structures may change shape while maintaining the function of electrically connecting the photodiode to the rest of the device. One of ordinary skill in the art could have substituted the interconnect structure of Lee for the interconnect structure of Sze and yielded the predictable results of electrically connecting different features of the device. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the conductive structures and absorption layers of Lee for the conductive structures and absorption layers of Sze, since simple substitution of conductive structures and absorption layers for another is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). Sze doesn’t teach a second oxide layer on a coplanar surface of the second side of the substrate and on a second end of the DTI structure, wherein the second end of the DTI structure is opposite from the first end of the DTI structure; a grid structure extending directly from the second oxide layer and aligned with the second end of the DTI structure wherein the grid structure comprises a first portion of the second oxide layer, wherein the first portion of the second oxide layer extends laterally from a second portion of the second oxide layer; and a third dielectric layer on the second oxide layer and around the grid structure, wherein the third dielectric layer resides directly on a top surface and side surfaces of the grid structure. However, Lim (figs. 5-6) teaches a second oxide layer ([0024], [0049], 30, 41) on a coplanar surface (30 is coplanar with 10) of the second side of the substrate ([0019], top of 10) and on a second end of the DTI structure ([0022], top of 13), wherein the second end of the DTI structure (top of 13) is opposite from the first end of the DTI structure (bottom of 13); a grid structure ([0039], 41, 42) extending directly from the second oxide layer (41 extends directly from 30, see fig. 6) and aligned (see fig. 6) with the second end of the DTI structure (top of 13), wherein the grid structure (41, 42) comprises a first portion (41) of the second oxide layer (30, 41), wherein the first portion (41) of the second oxide layer (30, 41) extends laterally (41 extends outward from 30) from a second portion (30) of the second oxide layer (30, 41); and a third dielectric layer ([0019], 50) on the second oxide layer (30, 41) and around the grid structure (41, 42), wherein the third dielectric layer (50) resides directly on a top surface (50 resides directly on the top surface of 42, see fig. 6) and side surfaces (50 resides on the side surfaces of 41 and 42, see fig. 6) of the grid structure (41, 42). Lim also teaches that the grid structure helps reflect incident light obliquely incident on the substrate, thereby causing more incident light to reach the photodiode and reducing or preventing crosstalk ([0029]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the pixel sensor of Sze to include the grid pattern of Lim to reduce or prevent crosstalk. Regarding Claim 6, while Sze (see fig. 16) doesn’t explicitly teach which metals comprise the other conductive portions (602, 604), it would have been obvious to use aluminum or copper as it was used for the other conductive features ([0071], 122, 126) disclosed by Sze. In the same way that the aluminum or copper conductive structures disclosed by Applicant’s filed specification reflect a visible light component ([0064]), one skilled in the art would understand that the conductive portions (126) of Sze, also made of aluminum or copper, reflect light in the same manner as Applicant’s aluminum or copper conductive structures. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that Sze teaches the pixel sensor of claim 1, wherein the plurality of conductive structures (126, 602, 604) are configured to reflect incident light toward the photodiode (110). Regarding Claim 7, Sze (see fig. 16) teaches the pixel sensor of claim 1, wherein the plurality of absorption layers (124) are configured to absorb an infrared light component of incident light ([0038], [0017], 124 may be tantalum nitride). Regarding Claim 14, Sze (see fig. 16) teaches: A pixel array ([0027], numerous image sensor devices may be disposed), comprising: a substrate ([0022], 103); a plurality of pixel sensors ([0031], 110) in the substrate (103); a deep trench isolation (DTI) ([0027], 156, 158) structure in the substrate (103) between the plurality of pixel sensors (110); a first oxide layer ([0064], 132) on a first end of the DTI structure (bottom of 156, 158) and on a first side (bottom of 103, see fig. 16) of the substrate (103); a plurality of conductive structures ([0029], 126, [0058], 602, 604), spaced from each other (see fig. 16), in a dielectric layer ([0029], 119, [0058], 610) over (fig. 16 is rotated by 180 degrees when compared to the claimed invention, so 119 and 610 can be interpreted to be over 132) the first oxide layer (132), wherein the plurality of conductive structures are configured to reflect a visible light component of incident light toward photodiodes of the plurality of pixel sensors in the substrate; a plurality of absorption layers ([0038], 124 may be tantalum nitride, tantalum nitride absorbs light in a first wavelength range), spaced from each other (see fig. 16), in the dielectric layer (119, 610), wherein a surface of the plurality of conductive structures and a surface of the plurality of absorption layers have a same length and reside coextensively on each other; and a second oxide layer on a second side of the substrate and on a second end of the DTI structure, wherein the second end of the DTI structure is opposite from the first end of the DTI structure; a grid structure on the second oxide layer and aligned with the DTI structure; and a third dielectric layer on the second oxide layer and around the grid structure, wherein the third dielectric layer resides directly on a top surface and side surfaces of the grid structure. Sze doesn’t explicitly teach that the plurality of conductive structures are configured to reflect a visible light component of incident light toward photodiodes of the plurality of pixel sensors in the substrate. While Sze doesn’t explicitly teach which metals comprise the other conductive portions (602, 604), it would have been obvious to use aluminum or copper as it was used for the other conductive features ([0071], 122, 126) disclosed by Sze. In the same way that the aluminum or copper conductive structures disclosed by Applicant’s filed specification reflect a visible light component ([0064]), one skilled in the art would understand that the conductive portions (126) of Sze, also made of aluminum or copper, reflect light in the same manner as Applicant’s aluminum or copper conductive structures. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that Sze teaches that the plurality of conductive structures (126, 602, 604) are configured to reflect a visible light component of incident light toward the photodiodes (110) of the plurality of pixel sensors in the substrate (103). Sze doesn’t explicitly teach a surface of the plurality of conductive structures and a surface of the plurality of absorption layers have a same length and reside coextensively on each other. However, Lee (fig. 6) teaches, in a similar image sensor, a surface of the plurality of conductive structures ([0015], 30 includes a bulk conductive layer made of aluminum or copper) and a surface of the plurality of absorption layers ([0015], 30 includes barrier layers made of tantalum nitride) have a same length and reside coextensively on each other (see fig. 6). Lee teaches that the interconnection structures may change shape while maintaining the function of electrically connecting the photodiode to the rest of the device. One of ordinary skill in the art could have substituted the interconnect structure of Lee for the interconnect structure of Sze and yielded the predictable results of electrically connecting different features of the device. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the conductive structures and absorption layers of Lee for the conductive structures and absorption layers of Sze, since simple substitution of conductive structures and absorption layers for another is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). Sze doesn’t teach a second oxide layer on a second side of the substrate and on a second end of the DTI structure, wherein the second end of the DTI structure is opposite from the first end of the DTI structure; a grid structure on the second oxide layer and aligned with the DTI structure; and a third dielectric layer on the second oxide layer and around the grid structure, wherein the third dielectric layer resides directly on a top surface and side surfaces of the grid. However, Lim (figs. 5-6) teaches a second oxide layer ([0024], [0049], 30, 41) on a second side of the substrate ([0019], top of 10) and on a second end of the DTI structure ([0022], top of 13), wherein the second end of the DTI structure (top of 13) is opposite from the first end of the DTI structure (bottom of 13); a grid structure ([0039], 41, 42) on the second oxide layer (30, 41) and aligned (see fig. 6) with the DTI structure (top of 13); and a third dielectric layer ([0019], 50) on the second oxide layer (30, 41) and around the grid structure (41, 42), wherein the third dielectric layer (50) resides directly on a top surface (50 resides directly on the top surface of 42, see fig. 6) and side surfaces (50 resides directly on the side surfaces of 41 and 42, see fig. 6) of the grid structure (41, 42). Lim also teaches that the grid structure helps reflect incident light obliquely on the substrate, thereby causing more incident light to reach the photodiode and reducing or preventing crosstalk ([0029]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the pixel sensor of Sze to include the grid pattern of Lim to help reduce or prevent crosstalk. Regarding Claim 15, Sze (see fig. 16) teaches the pixel array of claim 14, wherein the plurality of absorption layers (124) are configured to absorb an infrared light component of the incident light ([0038], [0017], 124 may be tantalum nitride). Regarding Claim 16, Sze (see fig. 16) teaches the pixel array of claim 14, wherein each of the plurality of absorption layers (124) comprises at least one of silicon oxide, tantalum, or tantalum nitride (0038], [0017], 124 may be tantalum nitride). Regarding Claim 18, Sze (see fig. 16) teaches the pixel array of claim 14, wherein the plurality of conductive structures comprise a layer (126) including at least one of aluminum, copper ([0071]), silver, or gold. Regarding Claim 30, Sze (fig. 16) teaches the pixel sensor of claim 1, further comprising: a transfer gate ([0028], 147) residing directly on the first dielectric layer (134), wherein the first oxide layer (132) surrounds a top (fig. 16 is rotated by 180 degrees when compared to the claimed invention, so the bottom of 147 can be interpreted to be the top) and sides of the transfer gate (147), and wherein the plurality of absorption layers (124) includes a first absorption region (124 connected to 147, labeled first absorption region, see annotated fig. 16) connected to the transfer gate (147). PNG media_image1.png 742 1068 media_image1.png Greyscale Annotated Figure 16 Regarding Claim 31, Sze (fig. 16) teaches the pixel sensor of claim 30, wherein the plurality of absorption layers (124) includes a second absorption region (124 connected to 110, labeled second absorption region, see annotated fig. 16) connected to the photodiode (110) and a third absorption region (124 connected to 140, labeled third absorption region, see annotated fig. 16) connected to the drain region (140). Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Sze, Lee, and Lim, as applied to Claim 1, and further in view of Venezia et al. (U.S. 2009/0200625 A1; hereinafter Venezia). Regarding Claim 2, Sze doesn’t explicitly teach the pixel sensor of claim 1, wherein a height of the DTI structure is in a range of approximately 1 micron to approximately 9 microns. However, Venezia (see fig. 3) teaches that a height of the DTI structure ([0034], 310) is in a range of approximately 1 micron to approximately 9 microns ([0034], 1 to 3 microns). One of ordinary skill in the art would have found it obvious to try forming a DTI a structure with the suggested height and yielded the predictable results of electrically isolating adjacent image sensors. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to use the suggested DTI structure height of Venezia since this limitation is one of a finite number of identified, predictable potential solutions. This is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). Regarding Claim 3, Sze doesn’t teach the pixel sensor of claim 1, wherein a width of the DTI structure changes from the first side of the substrate to the second side of the substrate. However, Venezia (see fig. 2) teaches that a width of the DTI structure ([0028], 208) changes from the first side of the substrate ([0027], top of 202) to the second side of the substrate (bottom of 202) while still maintaining the function of a DTI structure. One of ordinary skill in the art could have substituted the DTI structure of Venezia for the DTI structure of Sze and yielded the predictable results of electrically isolating adjacent image sensors. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the DTI structure of Venezia for the DTI structure of Sze, since simple substitution of DTI structures for another is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). Claims 17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Sze, Lee, and Lim as applied to Claim 14 above, and further in view of Kato (U.S. 2014/0145287 A1; hereinafter Kato). Regarding Claim 17, Sze does not explicitly teach the pixel array of claim 14, wherein a ratio between an area of the plurality of conductive structures, and an area of the dielectric layer, is in a range of approximately 0.3 to approximately 1.5. It is recognized that the applicant states that a ratio between an area of the plurality of conductive structures, and an area of the dielectric layer is chosen to provide sufficient light reflection performance and that it is chosen to increase or decrease the light reflection performance of the conductive structures ([0058]). Kato (see, e.g., fig. 1) similarly teaches that the areas of the conductive structures ([0020], 110, 111, 112) are manipulated in order to improve device sensitivity and reduce a mixture of colors ([0025]). As evidenced by the figure (fig. 1) the area of the conductive structures (110, 111, 112) is less than the area of the dielectric layer ([0020], 105). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to consider a ratio between an area of the plurality of conductive structures, and an area of the dielectric layer would be a condition to optimize and control through routine experimentation as long as it satisfies the condition that the conductive structures reflect a desired portion of incident light. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) Regarding Claim 19, Sze teaches the pixel array of claim 14, wherein (as discussed in the rejection of Claim 14, one skilled in the art would find it obvious that 602 may comprise the same materials as disclosed for 122 and 126) the plurality of conductive structures comprise: a second layer (602), on the first layer (126), including at least one of aluminum, copper ([0071]), silver, or gold. However, Sze does not explicitly teach that the plurality of conductive structures comprise: a first layer including tungsten. Kato (see fig. 1), in a similar image sensor, teaches that the plurality of conductive structures ([0020], 110, 111, 112) comprise: a first layer including tungsten ([0021]). Kato also teaches that tungsten, aluminum, and copper are equivalently used for conductive structures ([0021]). One of ordinary skill in the art would have found it obvious to try and use tungsten as a material for a conductive structure and yielded the predictable results of being electrically conductive and reflective. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to use tungsten in the first layer since this limitation is one of a finite number of identified, predictable potential solutions. This is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). Regarding Claim 20, Sze teaches the pixel array of claim 19, wherein (as discussed in the rejection of Claim 14, one skilled in the art would find it obvious that 602 may comprise the same materials as disclosed for 122 and 126) a third layer (604), on the second layer (602), including at least one of aluminum, copper ([0071]), silver, or gold. Claims 21, 25-26, and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Sze in view of Lim. Regarding Claim 21, Sze (see fig. 16) teaches: A pixel sensor ([0073], 1600), comprising: a substrate ([0022], 103); a photodiode ([0031], 110) in the substrate (103); a drain region ([0028], 140) in the substrate (103); a deep trench isolation (DTI) structure ([0027], 156, 158) that extends through the substrate (103) on a first side of the substrate (top of 103, see fig. 16) and on a second side of the substrate (bottom of 103, see fig. 16); a first single oxide layer ([0058], 119 is in an oxide-to-oxide bond) over (fig. 16 is rotated by 180 degrees when compared to the claimed invention, so 119 can be interpreted to be over 103 and 156, 158) the first side of the substrate (bottom of 103) and over a first end of the DTI structure (bottom of 156, 158); a plurality of conductive structures ([0029], 126, [0058], 602, 604), over (fig. 16 is rotated by 180 degrees when compared to the claimed invention, so 602 and 604 can be interpreted to be over 119) the first single oxide layer (119) and spaced apart from each other, comprising: a first conductive structure (126, 602, 604 that are connected to 110, labeled first conductive structure, see additional annotated fig. 16) connected to the photodiode (110) and a second conductive structure (126, 602, 604 that are connected to 140, labeled second conductive structure, see additional annotated fig. 16) connected to the drain region (140); a plurality of absorption layers ([0038], 124 may be tantalum nitride, tantalum nitride absorbs light in a first wavelength range), over (fig. 16 is rotated by 180 degrees when compared to the claimed invention, so 124 can be interpreted to be over 119) the first single oxide layer (119) and spaced from each other (spaced apart in the vertical direction, see fig. 16), corresponding to the plurality of conductive structures (126, 602, 604), wherein each of the plurality of absorption layers (124) comprises dielectric materials ([0071], may be tantalum nitride, stated to be a dielectric in [0062] of applicant’s filed specification); a second single oxide layer on the second side of the substrate and on a second end of the DTI structure, wherein the second end of the DTI structure is opposite from the first end of the DTI structure; a grid structure extending directly from the second single oxide layer and aligned with the DTI structure, wherein the grid structure comprises a first portion of the second single oxide layer, wherein the first portion of the second single oxide layer extends laterally from a second portion of the second single oxide layer; and a third dielectric layer on the second single oxide layer and around the grid structure. Sze doesn’t teach a second single oxide layer on the second side of the substrate and on a second end of the DTI structure, wherein the second end of the DTI structure is opposite from the first end of the DTI structure; a grid structure extending directly from the second single oxide layer and aligned with the DTI structure, wherein the grid structure comprises a first portion of the second single oxide layer, wherein the first portion of the second single oxide layer extends laterally from a second portion of the second single oxide layer; and a third dielectric layer on the second single oxide layer and around the grid structure. However, Lim (figs. 5-6) teaches a second single oxide layer ([0024], [0039], 30, 41) on a second side of the substrate ([0019], top of 10) and on a second end of the DTI structure ([0022], top of 13), wherein the second end of the DTI structure (top of 13) is opposite from the first end of the DTI structure (bottom of 13); a grid structure ([0039], 41, 42, see fig. 6) extending directly from the second single oxide layer (41 extends directly from 30, see fig. 6) and aligned (see fig. 6) with the DTI structure (top of 13), wherein the grid structure (41, 42) comprises a first portion (41) of the second single oxide layer (30, 41), wherein the first portion (41) of the second single oxide layer (30, 41) extends laterally (41 extends outward from 30, see fig. 6) from a second portion (30) of the second single oxide layer (30, 41); and a third dielectric layer ([0019], 50) on the second single oxide layer (30, 41) and around the grid structure (41, 42). Lim also teaches that the grid structure helps reflect incident light obliquely on the substrate, thereby causing more incident light to reach the photodiode and reducing or preventing crosstalk ([0029]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the pixel sensor of Sze to include the grid pattern of Lim to help reduce or prevent crosstalk. PNG media_image2.png 742 1068 media_image2.png Greyscale Additional Annotated Figure 16 Regarding Claim 25, Sze doesn’t teach the pixel sensor of claim 21, further comprising: a transfer gate over the substrate, wherein the plurality of conductive structures includes a third conductive structure connected to the transfer gate. However, another embodiment of Sze (fig. 4) teaches a transfer gate ([0049], 402) over (see fig. 4) the substrate (103), wherein the plurality of conductive structures includes a third conductive structure (126 and upper 124 that are connected to 402) connected to the transfer gate (402). Sze also teaches that the addition of a transfer gate allows or prevents the flow of carriers ([0049]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the pixel sensor of Sze to include the transfer gate of another embodiment of Sze to allow or prevent carrier flow. Regarding Claim 26, Sze (see fig. 4) teaches the pixel sensor of claim 25, wherein the transfer gate (402) is entirely within the first single oxide layer (119). Regarding Claim 29, Lim (figs. 5-6) teaches the pixel sensor of claim 21, wherein the grid structure (41, 42) further comprises a portion of a metal layer (42) over the first portion (41) of the second single oxide layer (30, 41). Claims 27-28 are rejected under 35 U.S.C. 103 as being unpatentable over Sze and Lim as applied to Claim 21 above, and further in view of Kobayashi (2012/0199883 A1; hereinafter Kobayashi). Regarding Claim 27, Sze doesn’t teach the pixel sensor of claim 21, wherein the photodiode comprises a p-type region and a plurality of n-type region. Kobayashi (fig. 5A) teaches that the photodiode ([0029], photoelectric conversion unit) comprises a p-type region ([0050], 107) and a plurality of n-type regions ([0084], 101, 501). Kobayashi also teaches that by having different N-type regions at different depths can increase sensitivity ([0088]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Sze to include the photodiode of Kobayashi to increase sensitivity. Regarding Claim 28, Kobayashi (fig. 5A) teaches the pixel sensor of claim 27, wherein the p-type region (107) resides over each of the plurality of n-type regions (101, 501). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADIN HRNJIC whose telephone number is (571)270-1794. The examiner can normally be reached Monday-Friday 8:00 AM - 4:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /A.H./Examiner, Art Unit 2817 /Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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Prosecution Timeline

Show 28 earlier events
May 16, 2025
Interview Requested
Jun 30, 2025
Response Filed
Nov 06, 2025
Final Rejection mailed — §103
Nov 24, 2025
Interview Requested
Jan 06, 2026
Response after Non-Final Action
Feb 06, 2026
Request for Continued Examination
Feb 16, 2026
Response after Non-Final Action
Jun 23, 2026
Non-Final Rejection mailed — §103 (current)

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Patent 12514095
DISPLAY SUBSTRATES AND MANUFACTURING METHODS THEREOF, AND DISPLAY DEVICES
4y 2m to grant Granted Dec 30, 2025
Patent 12514029
PART INCLUDING SILICON CARBIDE LAYER AND MANUFACTURING METHOD THEREOF
3y 5m to grant Granted Dec 30, 2025
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

7-8
Expected OA Rounds
66%
Grant Probability
73%
With Interview (+7.8%)
3y 4m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 58 resolved cases by this examiner. Grant probability derived from career allowance rate.

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