DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Claim rejections under 35 U.S.C. § 103
Applicant states that Jung et al. (US 2018/0300434) is not prior art under 35 U.S.C. § 102(a)(1) nor 35 U.S.C. § 102(a)(2). The Examiner apologizes for the inconvenience. A new reference is hereby introduced to replace Jung et al. The grounds of rejection is largely the same as it was with Jung et.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
trained machine learning model (assuming the trained machine learning model is performing the claimed act/function in claims 1-2, 5-16, 19-20, and 22-28);
hardware computer system in claims 1-2, 5-16, 19-20, and 22-28;
computer program product in claims 15-16, 19-20, and 25-28.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 5-16, 19-20, and 22-28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hu et al. (US 2018/0300434) in view of Lin et al. (US 2021/0389677).
Hu shows:
1. A method comprising:
converting one or more patterning process images comprising image patterns (see para. [0115], Fig. 2) into feature vectors (see paras. [0113]-[0115]; para. [0116]: For example, for the set of good patterns, certain geometric properties of the reference patterns are extracted or otherwise determined. The set of these geometric properties for each pattern is herein referred to as a “feature vector”)) (para. [0116]:”The intended patterns that are classified as good and the intended patterns that are classified as bad are separated. In some embodiments, feature extraction is performed on each of the good and bad groupings of reference patterns;” The predicted image of a pattern is taken to be equivalent to “intended patterns”); and
grouping, by a hardware computer system (see Fig. 1B; para. [0018]) and using the trained machine learning model, feature vectors with features indicative of image patterns that cause matching wafer behavior in a patterning process (see paras. [0026],[0054],[0117]-[0120]: “good or bad” and “ranking” is taken to be equivalent to the claimed “grouping”), see also [0202]-[0205]), and
using the grouped feature vectors to facilitate detection of potential patterning defects on a wafer (see paras. [0124]-[0128]).
Hu shows that process images are converted to feature vectors but not how it is converted, and in particular not that this conversion is done by a trained machine learning model into which the one or more process images are inputted.
Lin shows the determination of a root cause affecting yield in a process for manufacturing devices on a substrate, e.g. wafers (para. [0123]) where semantic feature vectors are extracted by a pre-trained machine learning model. The machine learning model is able to classify and detect fingerprints (distribution patterns). See para. [0062].
Before the effective filing date of the claimed invention, it would have been obvious to use a trained machine learning model in order to convert the process images into feature vectors and further because a trained machine learning model will operate with higher accuracy.
2. The method of claim 1, wherein the method is for grouping image patterns to identify potential wafer defects in the patterning process, and the grouping comprises grouping, based on the trained machine learning model, feature vectors with features indicative of image patterns that cause matching wafer defect behavior in the patterning process (see para. [0128]).
5. The method of claim 1, wherein the trained machine learning model comprises a first trained machine learning model (the trained machine learning model of Lin as discussed for claim 1) and a second trained machine learning model (Lin, para. "A machine learning model is built or obtained which is able to classify and detect fingerprints (distribution patterns). This model is then trained using training data comprising a labeled dataset of wafer sort maps, where the labels can be provided by human engineer annotation (e.g., supervised learning); see para. [0062]), wherein converting the one or more patterning process images comprising the image patterns into feature vectors is based on the first trained machine learning model, and wherein grouping feature vectors with features indicative of image patterns that cause matching wafer behavior is based on the second trained machine learning model.
6. The method of claim 5, wherein the first machine learning model is an image encoder (Lin: "based on informative semantic feature vectors (e.g., encodings)." para. [0062]) trained to:
extract features from images (images are from above the wafer) indicative of:
image pattern configurations of a first range (Lin, "Once the similarity scores have been computed, the system will be able to identify each of the scanner metrology wafer maps which resembles (e.g., has a high similarity based on a similarity threshold to) the final wafer sort map.” of para. [0063]; “range” is not limiting because the range is not defined and any value defines a range, limitations of the range are not imported from the specification); and
pattern structures that influence the wafer behavior (Hu; Lin's "a root cause affecting yield"), of a second range different than the first range (); and
encode the extracted features into the feature vectors (see discussion for claim 1 above).
7. The method of claim 6, wherein grouping the feature vectors with features indicative of image patterns that cause matching wafer behavior based on the second machine learning model comprises:
grouping the feature vectors into first groups based on the features indicative of the image pattern configurations of the first range (see Hu, paras. [0117]-[0120]: “good”; see also discussion of “range” for claim 6), and
grouping the feature vectors into second groups based on the first groups and the pattern structures of the second range (see Hu, paras. [0117]-[0120]: “bad”),
such that the second groups comprise the groups of feature vectors with the features indicative of image patterns that cause the matching wafer behavior in the patterning process.
8. The method of claim 5, further comprising training the first machine learning model with simulated images (Lin, para. "This model is then trained using training data comprising a labeled dataset of wafer sort maps, where the labels can be provided by human engineer annotation (e.g., supervised learning); see para. [0062])).
9. The method of claim 8, wherein the first machine learning model comprises a loss function, and further comprising iteratively re-training the first machine learning model based on the output from the first machine learning model and the additional simulated images including comprises adjusting the loss function (Official notice that retraining of neural networks was well known. Before the effective filing date of the claimed invention, it would have been obvious re-train or further train the machine learning model in order to improve the accuracy of the conversion) .
10. The method of claim 5, further comprising training the second machine learning model with labeled wafer defects from a wafer verification process (see Hu para. [0081]; Lin, para. "This model is then trained using training data comprising a labeled dataset of wafer sort maps, where the labels can be provided by human engineer annotation (e.g., supervised learning); see para. [0062]).
11. The method of claim 10, wherein a given labeled wafer defect includes information related to: (i) image pattern configurations of a first range associated with the given labeled wafer defect, or (ii) pattern structures of a second range different than the first range associated with the given labeled wafer defect, or (iii) both (i) and (ii), and wherein (iv) the information related to the image pattern configurations of the first range associated with the given labeled wafer defect, or (v) the information related to pattern structures of the second range associated with the given labeled wafer defect, or (vi) both (iv) and (v),are related to a probability of whether the given labeled wafer defect is real or not (The claim does not limit how the information is “related to”. The information of Hu is “related” to images and to a probability).
12. The method of claim 1, wherein the feature vectors describe the image patterns and include features related to optical proximity verification model terms and/or imaging conditions for the one or more patterning process images (the claim does not specify how the elements are “related to” each other and thus a non-specified relationship is inherent).
13. The method of claim 12, comprising grouping of the feature vectors into groups based on the features indicative of image pattern configurations of a certain range, and wherein the features indicative of the image pattern configurations of the certain range include the features related to optical proximity verification model terms and/or imaging conditions for the one or more patterning process images (see para. Hu [0081]; also see discussion of “related to” above).
14. The method of claim 1, further comprising training the machine learning model configured to predict wafer behavior by grouping feature vectors with features indicative of image patterns that cause matching wafer behavior in the patterning process (see Hu para. [0135]).
15. A computer program product (see para. Hu [0018]) comprising a non-transitory computer readable medium having instructions therein, the instructions, when executed by a computer system, configured to cause the computer system to at least:
execute a trained machine learning model into which one or more patterning process images inputted to convert the one or more patterning process images comprising image patterns into feature vectors, the feature vectors corresponding to the image patterns and the image patterns comprising an actual or simulated image (all images are actual or simulated i.e., artificial) of a pattern as formed on a mast, an actual or simulated aerial image of a mask pattern and/or an actual or simulated image of a mask pattern as exposed or etched on a substrate; and
execute the trained machine learning model, to group feature vectors with features indicative of image patterns that cause matching wafer behavior in a patterning process; and
use the grouped feature vectors to facilitate detection of potential patterning defects on a wafer (see citations given for claim 1; In addition, the program covered by claim 15 is not found to be different whether the images are actual or simulated because no algorithm has been found that differentiates an image is a simulated or actual image pattern from other pattern images. Furthermore, the claimed program product is not found to comprise the trained machine learning model. That is, the broadest reasonable interpretation of claim 15 is a program that is configured to simply instruct a separate computer having a trained machine learning model to start operating the trained learning model).
16. The computer program product of claim 15, configured group image patterns to identify potential wafer defects in the patterning process, and the instructions configured to cause the computer system to group the feature vectors are configured to group, based on the trained machine learning model, feature vectors with features indicative of image patterns that cause matching wafer defect behavior in the patterning process (see citations given for claim 2).
19. The computer program product of claim 15, wherein the trained machine learning model comprises a first trained machine learning model and a second trained machine learning model, wherein the instructions configured to cause the computer system to convert the one or more patterning process images are configured to do so based on the first trained machine learning model, and wherein the instructions configured to cause the computer system to group the feature vectors are configured to do so based on the second trained machine learning model (see citations given for claim 5).
20. The computer program product of claim 15, wherein the feature vectors describe the image patterns and include features related to model terms and/or imaging conditions for the one or more patterning process images (see citations given for claim 5).
22. The method of claim 10, further comprising iteratively re-training the second machine learning model based on output from the second machine learning model, the given labeled wafer defect, and additional labeled wafer defects from the wafer verification process (see citations given for claim 9).
23. The method of claim 5, wherein the first range is shorter than the second range (see discussion for claim 6).
24. The method of claim 1, further comprising performing optical proximity correction based on the grouped feature vectors (para. [0039]: “At 102, Optical Proximity Correction (OPC) verification and contour simulation of decomposed patterns is performed.”).
25. The computer program product of claim 15, wherein the instructions are further configured performance of optical proximity correction based on the grouped feature vectors (para. [0039]: “At 102, Optical Proximity Correction (OPC) verification and contour simulation of decomposed patterns is performed.”).
26. The computer program product of claim 19, wherein the first machine learning model is an image encoder trained to:
extract features from images indicative of:
image pattern configurations of a first range; and
pattern structures, that influence the wafer behavior, of a second range different than the first range; and
encode the extracted features into the feature vectors (see discussion of claim 6).
27. The computer program product of claim 19, wherein the instructions configured to cause the computer system to group the feature vectors with features indicative of image patterns that cause matching wafer behavior based on the second machine learning model are further configured to cause the computer system to:
group the feature vectors into first groups based on the features indicative of the image pattern configurations of the first range, and
group the feature vectors into second groups based on the first groups and the pattern structures of the second range,
such that the second groups comprise the groups of feature vectors with the features indicative of image patterns that cause the matching wafer behavior in the patterning process (see discussion of claim 7 above).
28. The computer program product of claim 15, wherein the instructions are further configured to cause the computer system to train the machine learning model by grouping feature vectors with features indicative of image patterns that cause matching wafer behavior in the patterning process (see discussion of claim 5 above) .
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Hwa Andrew S Lee whose telephone number is (571)272-2419. The examiner can normally be reached Mon-Fri 9am-5:30pm.
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/Hwa Andrew Lee/ Primary Examiner, Art Unit 2877
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