Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Request for Continued Examination
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/20/2025 has been entered.
DETAILED ACTION
Status of the Claims
Applicant’s arguments/remarks of claims 1-8 and 10-21 in the reply filed on October 20th, 2025 are acknowledged. Claims 1, 3, 11-12 and 17 have been amended. Claim 9 has been cancelled. Claims 1-8 and 10-21 are pending.
Action on merits of claims 1-8 and 10-21 as follows.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1-4, 7-8, 10 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Mitsuiki (US 2016/0056233, hereinafter as Mitsu ‘233) in view of You (US 2016/0218180, hereinafter as You ‘180) and further in view of Chou (US 2015/0194506, hereinafter as Chou ‘506).
Regarding Claim 1, Mitsu ‘233 teaches a device comprising:
a semiconductor substrate (Fig. 27, (SUB); [0101];
an isolation region (DF; [0050]) extending into the semiconductor substrate, wherein the isolation region comprises: a first bottom portion having a first top surface (see Fig. 27; annotated “A”), with some portions of the first sidewall portions being lower than a top surface of the semiconductor substrate (see Fig. 27); first sidewall portions higher than the top surface (Fig. 27; annotated “A”) of the first bottom portion, wherein the first sidewall portions are connected to opposing ends of the first bottom portion (Fig. 27; annotated “A”);
a gate dielectric (GI1; [0048]) comprising: a second bottom portion over and contacting the top surface of the first bottom portion (Fig. 27; annotated “A”); and second sidewall portions over and connecting to opposing ends of the second bottom portion;
a first well region (WL1); and
a second well region (WL2), wherein the first well region and the second well region extend to opposite sides of the isolation region (DF), and wherein both of the first well region and the second well region contact the first bottom portion and the first sidewall portions of the isolation region.
Thus, Mitsu ‘233 is shown to teach all the features of the claim with the exception of explicitly the limitations: “a gate dielectric having a U-shape in a cross-sectional view of the device; the second bottom portion forms a distinguishable interface with the first top surface of the first bottom portion of the isolation region; a gate spacer contacting the gate dielectric”.
You ‘180 teaches a gate dielectric (Fig. 14C, (215); [0144]) having a U-shape in a cross-sectional view of the device; the second bottom portion (Fig. 14C, (215); [0144]) forms a distinguishable interface with the first top surface of the first bottom portion of the isolation region (135; [0142]); a gate spacer (210; [0114]) contacting the gate dielectric (215).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Mitsu ‘233 by having a gate dielectric having a U-shape in a cross-sectional view of the device; the second bottom portion forms a distinguishable interface with the first top surface of the first bottom portion of the isolation region and a gate spacer contacting the gate dielectric in order to improve performance by enhancing a width effect through adjustment of a channel shape of a fin-shaped field effect transistor (FINFET) (see para. [0006] as suggested by You ‘180.
Thus, Mitsu ‘233 and You ‘180 are shown to teach all the features of the claim with the exception of explicitly the limitations: “an interface between the gate spacer and the isolation region is lower than the top surface of the semiconductor substrate”.
Chou ‘506 teaches an interface between the gate spacer (Fig. 1, (135a); [0017]) and the isolation region (122; [0010]) is lower than the top surface of the semiconductor substrate (110; [0010]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Mitsu ‘233 and You ‘180 by having an interface between the gate spacer and the isolation region is lower than the top surface of the semiconductor substrate in order to provide a process margin for preventing a short circuit between a conductive line and a gate electrode, which are directly above the isolation structure, is improved (see para. [0008]) as suggested by Chou ‘506.
Further, it has been held to be within the general skill of a worker in the art to select a U shape for a gate dielectric on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.).
PNG
media_image1.png
18
19
media_image1.png
Greyscale
[AltContent: connector][AltContent: textbox (A)][AltContent: arrow][AltContent: connector]
PNG
media_image2.png
432
659
media_image2.png
Greyscale
Fig. 27 (Mitsu ‘233_Annotated)
Regarding Claim 2, You ‘180 teaches the second bottom portion (215) is substantially planar (see Fig. 2).
Regarding Claim 3, Chou ‘506 teaches the gate spacer (135a) extends lower than a top surface of one of the first sidewall portions (122).
Regarding Claim 4, Chou ‘506 teaches the gate spacer (135a) is between, and is spaced apart from, the first sidewall portions of the isolation region (122).
Regarding Claim 7, Mitsu ‘233 teaches a first High Voltage Well (HVW) region of a first conductivity type, wherein the first HVW region comprises a portion directly underlying the gate dielectric (WL1); and a second HVW region and a third HVW region on opposing sides of, and joining to, the first HVW region, wherein the second HVW region and a third HVW region contact sidewalls of the first sidewall portions of the isolation region (DF) (see Fig. 27).
Regarding Claim 8, Mitsu ‘233 teaches first HVW region (WL1) extends laterally beyond, and is wider than, the gate dielectric (GI1).
Regarding Claim 10, Mitsu ‘233 teaches an additional gate dielectric (GI2) and top edges of the first sidewall portions of the isolation region (40).
Thus, Mitsu ‘233, You ‘180 and Chou ‘506 are shown to teach all the features of the claim with the exception of explicitly the limitations: “an additional gate dielectric higher than top edges of the first sidewall portions of the isolation region”.
However, it has been held to be within the general skill of a worker in the art to select an additional gate dielectric higher than top edges of the first sidewall portions of the isolation region on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
PNG
media_image1.png
18
19
media_image1.png
Greyscale
Regarding Claim 21, You ‘180 teaches the isolation region (135; [0141]) comprises silicon oxide, and the gate dielectric (215; [0145]) comprises a high-k dielectric material.
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Mitsu ‘233, You ‘180 and Chou ‘506 as applied to claim 1 above, and further in view of Tien (US 2007/0085145, hereinafter as Tien ‘145).
Regarding Claim 5, Mitsu ‘233, You ‘180 and Chou ‘506 are shown to teach all the features of the claim with the exception of explicitly the limitations: “a contact etch stop layer (CESL), wherein the CESL extends into a space between the gate dielectric and one of the first sidewall portions, and extends lower than a top surface of the one of the first sidewall portions”.
Tien ‘145 teaches a contact etch stop layer (CESL) (Fig. 9, (56); [0024]), wherein the CESL extends into a space between the gate dielectric (49; [0020]) and one of the first sidewall portions (32; [0017]), and extends lower than a top surface of the one of the first sidewall portions (see Fig. 9).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Mitsu ‘233, You ‘180 and Chou ‘506 by having a contact etch stop layer (CESL), wherein the CESL extends into a space between the gate dielectric and one of the first sidewall portions, and extends lower than a top surface of the one of the first sidewall portions in order to prevent the surface damage within the sour/drain regions causes Idsat to drop of the HVMOS transistor device (see para. [0024]) as suggested by Chu ‘687.
Regarding Claim 6, Tien ‘145 teaches an inter-layer dielectric (210; [0030]) over the CESL (56), wherein the inter-layer dielectric extends into the space, and extends lower than the top surface of the one of the first sidewall portions (32).
Claims 11-14 and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Mitsu ‘233 in view of Kao (US 2011/0084332, hereinafter as Kao ‘332) and further in view of Chou ‘506.
Regarding Claim 11, Mitsu ‘233 teaches a device comprising:
a semiconductor substrate (Fig. 27, (SUB); [0101];
an isolation region (DF; [0050]) comprising edge portions and a middle portion between the edge portions, wherein the middle portion is recessed lower than the edge portions of the isolation region and a top surface of the semiconductor substrate to form a recess;
a gate stack (GE1; [0048]) extending into the recess;
a gate spacer (SW1; [0048]) on a sidewall of the gate stack; and
a first source/drain region (SR1/DR1; [0048]) and a second source/drain region (SR1/DR1; [0101]) extending into the semiconductor substrate, wherein the first source/drain region and the second source/drain region are on opposite sides of the isolation region.
Thus, Mitsu ‘233 is shown to teach all the features of the claim with the exception of explicitly the limitations: “the gate spacer extends into the recess; the gate spacer physically contacts a top surface of the middle portion of the isolation region that is directly under the recess; and wherein the gate spacer comprises a bottom surface lower than the top surface of the semiconductor substrate”.
Kao ‘332 teaches the gate spacer (Fig. 2, (22); [0014]) extends into the recess; the gate spacer ((22); [0014]) physically contacts a top surface of the middle portion of the isolation region (20; [0013]) that is directly under the recess (see Fig. 2).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Mitsu ‘233 by having the gate spacer extends into the recess; the gate spacer physically contacts a top surface of the middle portion of the isolation region that is directly under the recess in order to reduce charge coupling and electromagnetic field crowding and significantly reduce the resulting reverse-biased leakage current (see para. [0012] as suggested by Kao ‘332.
Thus, Mitsu ‘233 and Kao ‘332 are shown to teach all the features of the claim with the exception of explicitly the limitations: “the gate spacer comprises a bottom surface lower than the top surface of the semiconductor substrate”.
Chou ‘506 teaches the gate spacer (Fig. 1, (135a); [0017]) comprises a bottom surface lower than the top surface of the semiconductor substrate (110; [0010]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Mitsu ‘233 and Kao ‘332 by having the gate spacer comprises a bottom surface lower than the top surface of the semiconductor substrate in order to provide a process margin for preventing a short circuit between a conductive line and a gate electrode, which are directly above the isolation structure, is improved (see para. [0008]) as suggested by Chou ‘506.
Regarding Claim 17, Mitsu ‘233 teaches a device comprising:
a semiconductor substrate (Fig. 27, (SUB); [0101];
a first well region (LS1) of a first conductivity type in the semiconductor substrate;
a second well region (W1) and a third well region (W2) on opposing sides of the first well region and in the semiconductor substrate, wherein the second well region is of a second conductivity type opposite to the first conductivity type (see para. [0054]);
an isolation region extending into the first well region, the second well region, and the third well region; and
a transistor comprising: a gate stack (GE1);
gate spacers (SW1) on opposing sides of the gate stack (GE1), wherein the gate stack extends into the isolation region;
a first source/drain region in the second well region (W1); and
a second source/drain region in the third well region (W2), wherein the first source/drain region and the second source/drain region are on opposite sides of, and are spaced apart from, the isolation region (see Fig. 27).
Thus, Mitsu ‘233 is shown to teach all the features of the claim with the exception of explicitly the limitations: “the gate spacers extend into the recess; the gate spacer extends into the isolation region to physically contact a top surface of a recessed portion of the isolation region, and wherein the isolation region further comprises un-recessed portions that are higher than the top surface of the recessed portion of the isolation region”.
Kao ‘332 teaches the gate spacers (Fig. 2, (22); [0014]) extend into the recess; the gate spacer (Fig. 2, (22); [0014]) extends into the isolation region to physically contacts a top surface of a recessed portion of the isolation region (20; [0013]) and wherein the isolation region (20) further comprises un-recessed portions that are higher than the top surface of the recessed portion of the isolation region (see Fig. 2).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Mitsu ‘233 by having the gate spacers extend into the recess; the gate spacer extends into the isolation region to physically contact a top surface of a recessed portion of the isolation region, and wherein the isolation region further comprises un-recessed portions that are higher than the top surface of the recessed portion of the isolation region in order to reduce charge coupling and electromagnetic field crowding and significantly reduce the resulting reverse-biased leakage current (see para. [0012] as suggested by Kao ‘332.
Thus, Mitsu ‘233 and Kao ‘332 are shown to teach all the features of the claim with the exception of explicitly the limitations: “some portions of the gate spacers are lower than the top surface of the semiconductor substrate”.
Chou ‘506 teaches some portions of the gate spacers (Fig. 1, (135a); [0017]) are lower than the top surface of the semiconductor substrate (110; [0010]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Mitsu ‘233 and Kao ‘332 by having some portions of the gate spacers are lower than the top surface of the semiconductor substrate in order to provide a process margin for preventing a short circuit between a conductive line and a gate electrode, which are directly above the isolation structure, is improved (see para. [0008]) as suggested by Chou ‘506.
Regarding Claim 12, Mitsu ‘233 teaches a top surface of the middle portion of the isolation region (40) is lower than a top surface of the semiconductor substrate (see Fig. 27).
Regarding Claim 13, Kao ‘332 teaches a gate dielectric (32; [0013]) having a U- shape in a cross-sectional view of the device, wherein the U-shape comprises a bottom part, and two sidewall parts connecting to opposite ends of the bottom part, and wherein an entirety of the bottom part is in the recess (see Fig. 2).
Regarding Claim 14, Kao ‘332 teaches the gate spacer (22) is between, and is laterally spaced apart from both of, the edges portions of the isolation region (20; [0013]) (see Fig. 2).
Regarding Claim 18, Kao ‘332 teaches the isolation region (20) comprises: a bottom part; and a first sidewall part and a second sidewall part over and connected to the bottom part, wherein the gate spacers (22) are between, and are separated from, the first sidewall part and the second sidewall part (see Fig. 2)
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Mitsu ‘233, Kao ‘332 and Chou ‘506 as applied to claim 17 above, and further in view of Chu (US 2010/0140687, hereinafter as Chu ‘687).
Regarding Claim 19, Mitsu ‘233, Kao ‘332 and Chou ‘506 are shown to teach all the features of the claim with the exception of explicitly the limitations: “an additional isolation region in the semiconductor substrate, wherein the additional isolation region has a substantially planar top surface, and a sidewall of the additional isolation region contacts the first source/drain region”.
Chu ‘687 teaches an additional isolation region (40) in the semiconductor substrate, wherein the additional isolation region has a substantially planar top surface, and a sidewall of the additional isolation region (40) contacts the first source/drain region (62; [0031]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Mitsu ‘233, Kao ‘332 and Chou ‘506 by an additional isolation region in the semiconductor substrate, wherein the additional isolation region has a substantially planar top surface, and a sidewall of the additional isolation region contacts the first source/drain region in order to improve the performance of the HVMOS device (e.g increase the breakdown voltage) (see para. [0029]) as suggested by Chu ‘687.
Claims 15-16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Mitsu ‘233, Kao ‘332 and Chou ‘506 as applied to claim 11 above, and further in view of Hsu (US 2010/0171171, hereinafter as Hsu ‘171).
Regarding Claim 15, Mitsu ‘233, Kao ‘332 and Chou ‘506 are shown to teach all the features of the claim with the exception of explicitly the limitations: “the contact etch stop layer comprises a portion inside the recess”.
Hsu ‘171 teaches a contact etch stop layer (108; [0024]), wherein the contact etch stop layer comprises a portion inside the recess (see Fig. 1I).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Mitsu ‘233, Kao ‘332 and Chou ‘506 by having the contact etch stop layer comprises a portion inside the recess in order to reduce switching loss of the trench MOSFET device (see para. [0030]) as suggested by Hsu ‘171.
Regarding Claim 16, Hsu ‘171 teaches an inter-layer dielectric (110; [0022]) over the contact etch stop layer (108), wherein the inter-layer dielectric further extends into the recess (see Fig. 1E).
Regarding Claim 20, Tien ‘145 teaches a dielectric layer (210; [0030]) extending into the isolation region (32), wherein the dielectric layer contacts the gate spacers (60; [0023]).
Response to Arguments
Applicant’s arguments with respect to claims 1-8 and 10-21, filed on October 20th, 2025, have been considered but are moot in view of the new ground of rejection.
Interviews After Final
Applicants note that an interview after a final rejection is permitted in order to place the application in condition for allowance or to resolve issues prior to appeal. However, prior to the interview, the intended purpose and content of the interview should be presented briefly, preferably in writing. Upon review of the agenda, the Examiner may grant the interview if the examiner is convinced that disposal or clarification for appeal may be accomplished with only nominal further consideration. Interviews merely to restate arguments of record or to discuss new limitations will be denied. See MPEP § 714.13
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Examiner Dzung Tran whose telephone number is (571) 270-3911. The examiner can normally be reached on M-F 8 AM-5PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Supervisor Sue Purvis can be reached on 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DZUNG TRAN/
Primary Examiner, Art Unit 2893
Prosecution Insights