Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 7 and 18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/29/2025 has been considered by the examiner and made of record in the application file.
Claim Objections
Claim 13 is objected to because of the following informalities where proposed corrections are bolded and underlined: “third metal oxide layer of the metal oxide channel” to match the “a metal oxide channel” of claim 10 which claim 13 depends on. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 4-5, 9, 21-23 and 25 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by US 2017/0186843 A1, Hosaka et al.; 06/2017; (“843”).
Regarding Claim 1. 843 discloses A device (Figure 40A), comprising:
a substrate (#102, Figure 40A, substrate);
a thin film transistor (TFT) (#100F, Figure 40A, oxide semiconductor thin film transistor) disposed over the substrate (Figure 40A, the transistor is over #102), the TFT being a single top gate TFT (Figure 40A, the transistor comprises only one top gate #112, which functions as a gate according to [0467]) comprising:
a metal oxide channel (#108, Figure 40A, oxide semiconductor film which includes a channel functionality according to [0572]) having a first metal oxide layer (#108_3, Figure 40A, oxide semiconductor film), a second metal oxide layer (#108_2, Figure 40A, oxide semiconductor film), and a third metal oxide layer (#108_1, Figure 40A, oxide semiconductor film), the third layer metal oxide disposed closer to the substrate than the first metal oxide layer and the second metal oxide layer (Figure 40A, #108_1 is closer to #102 than #108_2 and #108_3), the second metal oxide layer disposed on the third metal oxide layer (Figure 40A, #108_2 is disposed on #108_1), the first metal oxide layer disposed on the second metal oxide layer (Figure 40A, #108_3 is disposed on #108_2), the second metal oxide layer separating the first metal oxide layer from the third metal oxide layer (Figure 40A, #108_2 is separating #108_3 from #108_1), the second metal oxide layer ([0580], “an oxide semiconductor film formed using a metal oxide target whose atomic ratio of In to Ga and Zn is 4:2:4.1 is used as the oxide semiconductor film 108_2”) having a greater electron mobility than the first metal oxide layer and the third metal oxide layer ([0580], “an oxide semiconductor film formed using a metal oxide target whose atomic ratio of In to Ga and Zn is 1:3:2 is used as the oxide semiconductor film 108_1/3”) ([0587]-[0589], #108_2 provides the greatest mobility as the primary path through which electrons travel), the electron mobility of the second metal oxide layer being greater than or equal to 30 cm2/V·s ([0393], H1 is an example of a film utilizing In : Ga : Zn in a 4:2:4.1 ratio and [0398]-[0402], H1 is shown in Figure 30A and “the field-effect mobility of 30 cm2/V·s or higher which is shown in FIG. 30A”);
a gate insulator layer (#110, Figure 40A, gate insulating film according to [0468]) disposed contacting a top surface of the first metal oxide layer of the metal oxide channel (Figure 40A, #110 is disposed contacting a top surface of #108_3);
a gate electrode (#112, Figure 40A, conductive film functioning as a gate electrode according to [0467]) disposed on the gate insulator layer (Figure 40A, #112 is disposed on #110);
a buffer layer (#104, Figure 40A, insulating film that improves the interface with the oxide semiconductor film, according to [0484], as a buffer layer) disposed on and in contact with the substrate (Figure 40A, #104 is disposed on and in contact with #102), the buffer layer disposed below the metal oxide channel and in direct contact with the third metal oxide layer (Figure 40A, #104 is disposed below #108 and is in direct contact with #108_1);
an inter-layer dielectric (ILD) layer (#116 and #118, Figure 40A, insulating films) disposed over and in contact with the gate insulator layer, the gate electrode, and the first metal oxide layer (Figure 40A, combination of #116/#118 is disposed over and in contact with #110, #112, and #108_3);
a source electrode (#120a, Figure 40A, conductive film functioning as a source electrode according to [0467]) disposed on and in contact with the ILD layer (Figure 40A, #120a is in contact with and disposed on the combination of #116/#118), the source electrode contacting the top surface of the first metal oxide layer of the metal oxide channel by a first via through the ILD layer (Figure 40A, #120a contacts a top surface of #108_3 by a first via through #116), the ILD layer extending from the top surface of the first metal oxide layer along the first via to a bottom surface of the source electrode (Figure 40A, the combination of #116/#118 extends from the top surface of the metal oxide channel along the first via to the bottom surface of #120a); and
a drain electrode (#120b, Figure 40A, conductive film functioning as a drain electrode according to [0467]) disposed on and in contact with the ILD layer (Figure 40A, #120b is in contact with and disposed on the combination of #116/#118), the drain electrode contacting the top surface of the first metal oxide layer of the metal oxide channel by a second via through the ILD layer (Figure 40A, #120b contacts a top surface of #108_3 by a second via through #116), the ILD layer extending from the top surface of the first metal oxide layer along the second via to a bottom surface of the drain electrode (Figure 40A, the combination of #116/#118 extends from the top surface of the metal oxide channel along the first via to the bottom surface of #120b),
the ILD layer disposed between the metal oxide channel and the source electrode (Figure 40A, #116 is at least partially disposed between #108 and the top portion of #120a on the left side of the first via through #116).
Regarding Claim 4. 843 discloses The device of claim 1, wherein each layer of the metal oxide channel is selected from the group consisting of In-Sn-O, In-Ga-O, In-Zn-O, In-Zn-Sn-O, In-Ga-Zn-O, In-Ga-Sn-O, In-Ga-Zn-Sn-O, and combinations thereof ([0580], “an oxide semiconductor film formed using a . . . atomic ratio of In to Ga and Zn is used as . . .108_1, an oxide semiconductor film formed using a . . . atomic ratio of In to Ga and Zn is used as . . . 108_2, and an oxide semiconductor film formed using a . . . atomic ratio of In to Ga and Zn is 1:3:2 is used as . . . 108_3”, i.e. all three layers of #108 are formed from In-Ga-Zn-O).
Regarding Claim 5. 843 discloses The device of claim 1, wherein each layer of the metal oxide channel has a thickness from about 0.5 nm to about 50 nm ([0393], Sample H1 described above as functioning as the second metal oxide layer has a thickness of approximately 40 nm, and according to [0458], the overall thickness of the entire film (comprising all three layers) is 3nm to 60 nm such that the first and third layers made of the same material as described above are necessarily around 10 nm thick).
Regarding Claim 9. 843 discloses The device of claim 1, wherein the TFT has a threshold voltage of about -0.5 V to about 2.5 V (Figure 30A, [0400]-[0402], sample H1, which functions as the channel of the transistor as #108_2 as described above (see [0585]), is observed to have a threshold voltage of approximately 0 V).
Regarding Claim 21. 843 discloses The device of claim 1, wherein the first metal oxide layer and the third metal oxide layer include Ga ([0580], “an oxide semiconductor film formed using a . . . atomic ratio of In to Ga and Zn is used as . . .108_1, . . . an oxide semiconductor film formed using a . . . atomic ratio of In to Ga and Zn is 1:3:2 is used as . . . 108_3”, i.e. #108_1 and #108_3 include Ga).
Regarding Claim 22. 843 discloses The device of claim 1, wherein the first metal oxide layer includes In, Ga, and Zn ([0580], “an oxide semiconductor film formed using a . . . atomic ratio of In to Ga and Zn is 1:3:2 is used as . . . 108_3”, i.e. #108_3 includes In, Ga, and Zn).
Regarding Claim 23. 843 discloses The device of claim 1, wherein the second metal oxide layer includes In, Zn, and O ([0580], “an oxide semiconductor film formed using a . . . atomic ratio of In to Ga and Zn is used as . . . 108_2, i.e. #108_2 includes In, Zn, and O (oxide)).
Regarding Claim 25. 843 discloses The device of claim 1, wherein the third metal oxide layer has a larger concentration of Ga than the second metal oxide layer ([0580], “an oxide semiconductor film formed using a metal oxide target whose atomic ratio of In to Ga and Zn is 1:3:2 is used as the oxide semiconductor film 108_1, an oxide semiconductor film formed using a metal oxide target whose atomic ratio of In to Ga and Zn is 4:2:4.1 is used as the oxide semiconductor film 108_2”, i.e. #108_1 has a greater Ga concentration (50% by the ratio above) then #108_2, (around 20% by the ratio above)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6, 10-14, and 24 is/are rejected under 35 U.S.C. 103 as being obvious in view of US 2017/0186843 A1, Hosaka et al.; 06/2017; (“843”) as applied to claim(s) 1 above, and further in view of US 2016/0071983 A1; Yamazaki, Shunpei et al.; 09/2014; (“983”).
Regarding Claim 6. 843 discloses The device of claim 1.
843 does not appear to disclose that the TFT has an electron mobility of about 35 cm2/V·s to about 70 cm2/V·s.
However, 983 discloses a similar TFT (Figure 4A) wherein the channel comprises a plurality of layers (#101, #102, and #103) composed of oxide semiconductor materials ([0092]) wherein the middle oxide semiconductor layer has a greater electron mobility than the upper and lower oxide semiconductor layers ([0131], the energy gap of #102 is smaller than #101 and #103, such that the mobility of #102 is greater than #101 and #103 based on [0020]) wherein the TFT has an electron mobility of about 35 cm2/V·s to about 70 cm2/V·s (Figures 24 and 26 show example transistors of the given structure wherein one of the oxide layers in each graph has a bulk mobility of 35 cm2/V·s such that the transistor as a whole may have a mobility within the required range).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to provide a TFT with an electron mobility in the range of 35 cm2/V·s to about 70 cm2/V·s, as was done in 983, for the device of 843 since it is clear that through modifying the materials and their ratios of the corresponding oxide semiconductor layers that the bulk mobility may be changed (see [0138]-[0143] of 843 and [0490]-[0492], “the difference in the field-effect mobility shown in FIGS. 24 and 26 became remarkable depending on the oxide semiconductor materials and the stack order of layers of the oxide semiconductor stacked layer . . . electrical characteristics (the field-effect mobility and the off-state current in this example) of a transistor can be changed variously by a stacked layer of oxide semiconductor layers whose band gaps are different from each other without changing the structure of the transistor. . . electrical characteristics of a transistor can be adjusted with high accuracy, providing the transistor with appropriate electrical characteristics”) to meet the requirements of the user and achieve higher field effect mobility transistors such that this limitation is considered both routine optimization and overlapping ranges; see MPEP 2144.05.II and MPEP 2144.05.I).
Regarding Claim 10. 843 discloses A device (Figure 40A), comprising:
a substrate (#102, Figure 40A, substrate);
a thin film transistor (TFT) (#100F, Figure 40A, oxide semiconductor thin film transistor) disposed over the substrate (Figure 40A, the transistor is over #102), the TFT comprising:
a metal oxide channel (#108, Figure 40A, oxide semiconductor film which includes a channel functionality according to [0572]) having a first metal oxide layer (#108_3, Figure 40A, oxide semiconductor film), a second metal oxide layer (#108_2, Figure 40A, oxide semiconductor film), and a third metal oxide layer (#108_1, Figure 40A, oxide semiconductor film), the third layer metal oxide disposed closer to the substrate than the first metal oxide layer and the second metal oxide layer (Figure 40A, #108_1 is closer to #102 than #108_2 and #108_3), the second metal oxide layer disposed on the third metal oxide layer (Figure 40A, #108_2 is disposed on #108_1), the first metal oxide layer disposed on the second metal oxide layer (Figure 40A, #108_3 is disposed on #108_2), the second metal oxide layer separating the first metal oxide layer from the third metal oxide layer (Figure 40A, #108_2 is separating #108_3 from #108_1), the second metal oxide layer ([0580], “an oxide semiconductor film formed using a metal oxide target whose atomic ratio of In to Ga and Zn is 4:2:4.1 is used as the oxide semiconductor film 108_2”) having a greater electron mobility than the first metal oxide layer and the third metal oxide layer ([0580], “an oxide semiconductor film formed using a metal oxide target whose atomic ratio of In to Ga and Zn is 1:3:2 is used as the oxide semiconductor film 108_1/3”) ([0587]-[0589], #108_2 provides the greatest mobility as the primary path through which electrons travel), and the electron mobility of the first metal oxide layer and the third metal oxide layer being less than or equal to 30 cm2/V·s ([0393], H1 is an example of a film utilizing In : Ga : Zn in a 4:2:4.1 ratio and [0398]-[0402], H1 is shown in Figure 30A and “the field-effect mobility of 30 cm2/V·s or higher which is shown in FIG. 30A”, i.e. #108_1 and #108_3 necessarily have mobilities lower than 30 cm2/V·s since they have mobilities lower than #108_2 which may have a mobility of 30 cm2/V·s);
a gate insulator layer (#110, Figure 40A, gate insulating film according to [0468]) disposed contacting a top surface of the first metal oxide layer of the metal oxide channel (Figure 40A, #110 is disposed contacting a top surface of #108_3);
a gate electrode (#112, Figure 40A, conductive film functioning as a gate electrode according to [0467]) disposed on the gate insulator layer (Figure 40A, #112 is disposed on #110);
an inter-layer dielectric (ILD) layer (#116, Figure 40A, insulating film) disposed over and in contact with the gate insulator layer, the gate electrode, and the first metal oxide layer adjacent to the gate insulator layer and the gate electrode (Figure 40A, #116 is disposed over and in contact with #110, #112, and #108_3 adjacent to #110 and #112);
a bottom gate electrode (#106, Figure 40A, conductive film which functions as a bottom gate electrode according to [0524]) disposed below the metal oxide channel (Figure 40A, #106 is disposed below #108) and comprising a bottom gate width equal to or less than a width of the channel (Figure 40A, #106 is observed to have a width less than the width of the channel which is interpreted to be the width of #108 which extends between #120a and #120b);
a source electrode (#120a, Figure 40A, conductive film functioning as a source electrode according to [0467]) disposed in the ILD layer and contacting the top surface of the first metal oxide layer of the metal oxide channel through a first via in the ILD layer (Figure 40A, #120a extends within #116 and contacts a top surface of #108_3 by a first via through #116); and
a drain electrode (#120b, Figure 40A, conductive film functioning as a drain electrode according to [0467]) disposed in the ILD layer and contacting the top surface of the first metal oxide layer of the metal oxide channel through a second via in the ILD layer (Figure 40A, #120b extends within #116 and contacts a top surface of #108_3 by a second via through #116).
843 does not appear to disclose that the TFT has an electron mobility of about 35 cm2/V·s to about 70 cm2/V·s.
However, 983 discloses a similar TFT (Figure 4A) wherein the channel comprises a plurality of layers (#101, #102, and #103) composed of oxide semiconductor materials ([0092]) wherein the middle oxide semiconductor layer has a greater electron mobility than the upper and lower oxide semiconductor layers ([0131], the energy gap of #102 is smaller than #101 and #103, such that the mobility of #102 is greater than #101 and #103 based on [0020]) wherein the TFT has an electron mobility of about 35 cm2/V·s to about 70 cm2/V·s (Figures 24 and 26 show example transistors of the given structure wherein one of the oxide layers in each graph has a bulk mobility of 35 cm2/V·s such that the transistor as a whole may have a mobility within the required range).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to provide a TFT with an electron mobility in the range of 35 cm2/V·s to about 70 cm2/V·s, as was done in 983, for the device of 843 since it is clear that through modifying the materials and their ratios of the corresponding oxide semiconductor layers that the bulk mobility may be changed (see [0138]-[0143] of 843 and [0490]-[0492] of 983, “the difference in the field-effect mobility shown in FIGS. 24 and 26 became remarkable depending on the oxide semiconductor materials and the stack order of layers of the oxide semiconductor stacked layer . . . electrical characteristics (the field-effect mobility and the off-state current in this example) of a transistor can be changed variously by a stacked layer of oxide semiconductor layers whose band gaps are different from each other without changing the structure of the transistor. . . electrical characteristics of a transistor can be adjusted with high accuracy, providing the transistor with appropriate electrical characteristics”) to meet the requirements of the user and achieve higher field effect mobility transistors such that this limitation is considered both routine optimization and overlapping ranges; see MPEP 2144.05.II and MPEP 2144.05.I).
Regarding Claim 11. 843 in view of 983 discloses The device of claim 10, wherein the gate electrode comprises a gate width less than or equal to the bottom gate width (843, Figure 40A, #112 is observed to have a width less than the width of #106).
Regarding Claim 12. 843 in view of 983 discloses The device of claim 10, wherein each layer of the channel is selected from the group consisting of In-Sn-O, In-Ga-O, In-Zn-O, In-Zn-Sn-O, In-Ga-Zn-O, In-Ga- Sn-O, In-Ga-Zn-Sn-O, and combinations thereof (843, [0580], “an oxide semiconductor film formed using a . . . atomic ratio of In to Ga and Zn is used as . . .108_1, an oxide semiconductor film formed using a . . . atomic ratio of In to Ga and Zn is used as . . . 108_2, and an oxide semiconductor film formed using a . . . atomic ratio of In to Ga and Zn is 1:3:2 is used as . . . 108_3”, i.e. all three layers of #108 are formed from In-Ga-Zn-O).
Regarding Claim 13. 843 in view of 983 discloses The device of claim 10, wherein at least one of the first metal oxide layer and the third metal oxide layer of the metal oxide channel has an electron mobility lower than 20 cm2/V·s (843, [0589], “the oxide semiconductor films 108_1 and 108_3 serve as oxide insulating films”, i.e. #108_1 and #108_3 effectively serve as oxide insulting films such that they necessarily have an electron mobility lower than 20 cm2/V·s).
Regarding Claim 14. 843 in view of 983 discloses The device of claim 10, wherein the TFT has a threshold voltage of about -0.5 V to about 2.5 V (843, Figure 30A, [0400]-[0402], sample H1, which functions as the channel of the transistor as #108_2 as described above (see [0585]), is observed to have a threshold voltage of approximately 0 V).
Regarding Claim 24. 843 discloses The device of claim 1.
843 does not appear to disclose that the second metal oxide layer does not include Ga.
However, 983 discloses a similar TFT (Figure 4A) wherein the channel comprises a plurality of layers (#101, #102, and #103) composed of oxide semiconductor materials ([0092]) wherein the middle oxide semiconductor layer has a greater electron mobility than the upper and lower oxide semiconductor layers ([0131], the energy gap of #102 is smaller than #101 and #103, such that the mobility of #102 is greater than #101 and #103 based on [0020]) wherein the second metal oxide semiconductor layer does not include Ga ([0133], “an In—Sn—Zn-based oxide film (with an energy gap of 2.8 eV) . . . are used as . . . the second oxide semiconductor layer 102”).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider utilizing a Ga-free oxide semiconductor layer, such as In-Sn-Zn-O, as the second oxide semiconductor layer of 843, as was done in 983. Motivation includes that Sn is preferably used to stabilize oxide semiconductor layers (see [0105] of 983) and “high mobility can be obtained relatively easily with an In—Sn—Zn-based oxide” (see [0112] of 983).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being obvious in view of US 2017/0186843 A1, Hosaka et al.; 06/2017; (“843”) in view of US 2016/0071983 A1; Yamazaki, Shunpei et al.; 09/2014; (“983”) as applied to claim 10 above, and further in view of US 2017/0263782 A1; Yamazaki, Shunpei; 09/2014; (“782”).
Regarding Claim 16. 843 in view of 983 discloses The device of claim 10.
843 in view of 983 do not explicitly disclose that at least one layer of the channel is free of Zn.
However, 782 teaches structures of oxide semiconductor thin film transistors ([0005]-[0009]) and further describes in [0200] a reduction in the zinc content to zero, in oxide semiconductor films, such that the fraction of the metal content increases, in an oxide semiconductor layer, and the result is a reduced carrier mobility and better insulation performance. Furthermore, 843 teaches in [0589] that “the oxide semiconductor films 108_1 and 108_3 serve as oxide insulating films”.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider making the first and third oxide semiconductor layers of 843 as Zn-free layers since doing so improves the insulation performance of the layers and reduces their mobility, as taught by 782 in [0200], below their value with Zinc such that they would still have a mobility less than 30 cm2/V·s as required by claim 10.
Claim(s) 17 and 19-20 is/are rejected under 35 U.S.C. 103 as being obvious in view of US 2017/0186843 A1, Hosaka et al.; 06/2017; (“843”).
Regarding Claim 17. 843 discloses A device, comprising:
a substrate (#102, Figure 40A, substrate);
a thin film transistor (TFT) (#100F, Figure 40A, oxide semiconductor thin film transistor) disposed over the substrate (Figure 40A, the transistor is over #102), the TFT comprising:
a first metal oxide layer (#108_3, Figure 40A, oxide semiconductor film) having a first electron mobility (a metal oxide layer necessarily has a mobility);
a second metal oxide layer (#108_2, Figure 40A, oxide semiconductor film) contacting the first metal oxide layer (Figure 40A, #108_2 is contacting #108_3);
a third metal oxide layer (#108_1, Figure 40A, oxide semiconductor film) separated from the first metal oxide layer by the second metal oxide layer (Figure 40A, #108_2 is separating #108_3 from #108_1), the second metal oxide layer disposed on the third metal oxide layer (Figure 40A, #108_2 is disposed on #108_1), the first metal oxide layer disposed on the second metal oxide layer (Figure 40A, #108_3 is disposed on #108_2), an electron mobility of the second metal oxide layer ([0580], “an oxide semiconductor film formed using a metal oxide target whose atomic ratio of In to Ga and Zn is 4:2:4.1 is used as the oxide semiconductor film 108_2”) being greater than an electron mobility of the first metal oxide layer and the third metal oxide layer ([0580], “an oxide semiconductor film formed using a metal oxide target whose atomic ratio of In to Ga and Zn is 1:3:2 is used as the oxide semiconductor film 108_1/3”) ([0587]-[0589], #108_2 provides the greatest mobility as the primary path through which electrons travel), the electron mobility of the second metal oxide layer being greater than or equal to 30 cm2/V·s ([0393], H1 is an example of a film utilizing In : Ga : Zn in a 4:2:4.1 ratio and [0398]-[0402], H1 is shown in Figure 30A and “the field-effect mobility of 30 cm2/V·s or higher which is shown in FIG. 30A”),
wherein the second metal oxide layer is free of Sn ([0580], “an oxide semiconductor film formed using a metal oxide target whose atomic ratio of In to Ga and Zn is 4:2:4.1 is used as the oxide semiconductor film 108_2”, i.e. #108_2 does not include Sn),
wherein the first, second, and third metal oxide layers together form a channel (#108, Figure 40A, oxide semiconductor film which includes a channel functionality according to [0572]);
a gate insulator layer (#110, Figure 40A, gate insulating film according to [0468]) disposed on and in contact a top surface of the first metal oxide layer (Figure 40A, #110 is disposed on and contacting a top surface of #108_3);
a gate electrode (#112, Figure 40A, conductive film functioning as a gate electrode according to [0467]) disposed on the gate insulator layer (Figure 40A, #112 is disposed on #110);
an inter-layer dielectric (ILD) layer (#116 and #118, Figure 40A, insulating films) disposed over and in contact with the gate insulator layer, the gate electrode, and the first metal oxide layer (Figure 40A, combination of #116/#118 is disposed over and in contact with #110, #112, and #108_3);
a source electrode (#120a, Figure 40A, conductive film functioning as a source electrode according to [0467]) disposed over the ILD layer and the gate electrode (in the instant application, the source electrode (#112) is not observed to overlap with the top gate electrode (#108) in any of the elected figures (Figures 1A and 1C elected on 09/20/2023) and there is no support for the overlap of the source and gate electrodes, therefore, “over” is interpreted under BRI to mean extending to a greater vertical height; 843 Figure 40A, #120a is over #116/#118 and #112), the source electrode contacting the top surface of the first metal oxide layer by a first via through the ILD layer (Figure 40A, #120a contacts a top surface of #108_3 by a first via through #116/#118), the ILD layer extending from the top surface of the first metal oxide layer along the first via to a bottom surface of the source electrode (Figure 40A, the combination of #116/#118 extends from the top surface of the metal oxide channel along the first via to the bottom surface of #120a); and
a drain electrode (#120b, Figure 40A, conductive film functioning as a drain electrode according to [0467]) disposed over the ILD layer and the gate electrode (in the instant application, the drain electrode (#114) is not observed to overlap with the top gate electrode (#108) in any of the elected figures (Figures 1A and 1C elected on 09/20/2023) and there is no support for the overlap of the drain and gate electrodes, therefore, “over” is interpreted under BRI to mean extending to a greater vertical height; 843 Figure 40A, #120b is over #116/#118 and #112), the drain electrode contacting the top surface of the first metal oxide layer by a second via through the ILD layer (Figure 40A, #120b contacts a top surface of #108_3 by a second via through #116/#118) the ILD layer extending from the top surface of the first metal oxide layer along the second via to a bottom surface of the drain electrode (Figure 40A, the combination of #116/#118 extends from the top surface of the metal oxide channel along the second via to the bottom surface of #120b),
the ILD layer disposed between the metal oxide channel and the source electrode (Figure 40A, #116/#118 is at least partially disposed between #108 and the top portion of #120a on the left side of the first via through #116/#118).
843 does not explicitly disclose that the ILD layer is a single layer.
However, [0500] of 843 teaches that “the insulating film 116, for example, a nitride insulating film can be used. The nitride insulating film can be formed using . . . silicon nitride oxide, silicon oxynitride . . . or the like” and [0501] of 843 teaches that “The insulating film 118 can be formed using, for example . . . silicon oxynitride, silicon nitride oxide . . .” such that both layers may be composed of silicon oxynitride or silicon nitride oxide such that they may be a single layer of the same material.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider providing both insulating layers (#116/#118) of the same material (silicon oxide nitride or silicon oxynitride) as considered by 843 in order to reduce processing requirements by limiting the number of required materials utilized in the manufacturing process and forming the layers as a single layer structure to make them integral as an obvious engineering choice (see MPEP 2144.04.V.B).
Regarding Claim 19. 843 discloses The device of claim 17, wherein the first metal oxide layer of the channel is selected from the group consisting of In-Sn-O, In-Ga-O, In-Zn-O, In-Zn-Sn-O, In-Ga-Zn-O, In-Ga-Sn-O, In-Ga-Zn-Sn-O, and combinations thereof ([0580], “an oxide semiconductor film formed using a . . . atomic ratio of In to Ga and Zn is 1:3:2 is used as . . . 108_3”, i.e. #108_3 is formed from In-Ga-Zn-O).
Regarding Claim 20. 843 discloses The device of claim 17, wherein the second metal oxide layer is selected from the group consisting of In-Ga-O, In-Zn-O, In-Ga-Zn-O, and combinations thereof ([0580], “an oxide semiconductor film formed using a . . . atomic ratio of In to Ga and Zn is used as . . . 108_2, i.e. #108_2 is formed from In-Ga-Zn-O).
Response to Arguments/Amendments
Applicant’s arguments for the rejoinder of claims 7 and 18 for being dependent on suggested allowable claims 1 and 17, see page 9 of the remarks, filed 06/12/2024, have been fully considered but are not persuasive. Claims 7 and 18 stand withdrawn as claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by US 2017/0186843 A1, Hosaka et al.; 06/2017; (“843”) and claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2017/0186843 A1, Hosaka et al.; 06/2017; (“843”).
Applicant’s amendments to claim 1 and corresponding arguments, see pages 9-10 of the remarks, filed 06/09/2025, with respect to the 35 U.S.C. 102 rejection of claim 1 as being anticipated by US 2017/0186843 A1, Hosaka et al.; 06/2017; (“843”), along with its dependent claims, have been fully considered but are not found persuasive.
Applicant argues that 843 does not teach “the ILD layer extending from the top surface of the first metal oxide layer along the first via to a bottom surface of the source electrode” and “the ILD layer extending from the top surface of the first metal oxide layer along the first via to a bottom surface of the drain electrode” based on Applicant’s interpretation of the insulating layer (#116, 843) not extending in such a manner in Figure 40A as cited in the previous rejection. While the examiner agrees with applicant’s interpretation based on the previous rejection’s mapping of #116 in 843 to the ILD layer, in view of the amendments a new interpretation is made upon further consideration of the applied reference. Examiner respectfully disagrees that 843 does not disclose all the limitations of amended claims 1. Specifically, the ILD layer of the claim is now mapped to the combination of #116 and #118 in 843 as these are both insulating layers, which together meet the required limitations in the amended claim. In figure 40A, the combination of #116/#118 extends from the top surface of the metal oxide channel along the first/second vias to the bottom surfaces of the source/drain electrodes (#120a/#120b). Under this broader interpretation, 843 does appear to teach “the ILD layer extending from the top surface of the first metal oxide layer along the first via to a bottom surface of the source electrode” and “the ILD layer extending from the top surface of the first metal oxide layer along the first via to a bottom surface of the drain electrode”. Claim(s) 1 stands rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by US 2017/0186843 A1, Hosaka et al.; 06/2017; (“843”). Claims which depend on claim 1 stand rejected as described above.
Applicant’s amendments to claim 10 and corresponding arguments, see page 10 of the remarks, filed 06/09/2025, with respect to the 35 U.S.C. 102 rejection of claim 10 as being anticipated by US 2017/0186843 A1, Hosaka et al.; 06/2017; (“843”), along with its dependent claims, have been fully considered and are found persuasive. 843 does not disclose all of the limitations of amended claim 10. The 35 U.S.C. 102 rejection of claim 10 has been withdrawn.
Applicant’s amendments to claim 17 and corresponding arguments, see page 10 of the remarks, filed 06/09/2025, with respect to the 35 U.S.C. 102 rejection of claim 17 as being anticipated by US 2017/0186843 A1, Hosaka et al.; 06/2017; (“843”), along with its dependent claims, have been fully considered and are found persuasive. 843 does not explicitly disclose all of the limitations of amended claim 17. The 35 U.S.C. 102 rejection of claim 10 has been withdrawn. However, upon further consideration, it is the examiner’s interpretation that when considered as a whole, the teachings of 843 render claim 17 obvious. As described above, 843 teaches that both insulating layers (#116/#118) may be composed of silicon oxynitride or silicon nitride oxide such that they may be a single layer of the same material. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider providing both insulating layers (#116/#118) of the same material to make them integral as an obvious engineering choice (see MPEP 2144.04.V.B) and reduce processing steps. Claim(s) 17 stand rejected under 35 U.S.C. 103 as being obvious in view of US 2017/0186843 A1, Hosaka et al.; 06/2017; (“843”). Claims which depend on claim 17 stand rejected as described above.
Applicant’s arguments regarding claims 6 and 24, see page 11 of the remarks, filed 06/09/2025, with respect to the 35 U.S.C. 103 rejections of claims 6 and 24 in view of the believed allowability of claim 1 on which they depend have been fully considered but are not found persuasive. As described above, claim 1 stands rejected under 35 U.S.C. 102 such that claims 6 and 24 are not interpreted to be allowable for their dependencies.
Applicant’s amendments to claim 10 and corresponding arguments, see pages 11-12 of the remarks, filed 06/09/2025, with respect to the 35 U.S.C. 103 rejection of claim 10 as being obvious in view of US 2017/0186843 A1, Hosaka et al.; 06/2017; (“843”) and further in view of US 2016/0071983 A1; Yamazaki, Shunpei et al.; 09/2014; (“983”), have been fully considered but are not found persuasive.
Applicant argues that 843 in view of 983 does not teach “the TFT has an electron mobility of about 35 cm2/V·s to about 70 cm2/V·s” based on Figures 24 and 26 of 983 referring to the mobilities of two oxide semiconductor layer TFTs instead of the three oxide semiconductor layer TFT claimed by the applicant. While the examiner agrees with applicant’s interpretation of Figures 24 and 26, Examiner respectfully disagrees that 843 in view of 983 does not render obvious all the limitations of amended claim 10. Specifically, 983 does disclose a TFT in Figures 24 and 26 which show example transistors of the given structure wherein one of the TFTs in each graph has a bulk mobility of 35 cm2/V·s such that the transistor as a whole may have a mobility within the required range. Furthermore, [0138]-[0143] of 843 and [0490]-[0492] of 983 teaches that “the difference in the field-effect mobility shown in FIGS. 24 and 26 became remarkable depending on the oxide semiconductor materials and the stack order of layers of the oxide semiconductor stacked layer . . . electrical characteristics (the field-effect mobility and the off-state current in this example) of a transistor can be changed variously by a stacked layer of oxide semiconductor layers whose band gaps are different from each other without changing the structure of the transistor. . . electrical characteristics of a transistor can be adjusted with high accuracy, providing the transistor with appropriate electrical characteristics”. It is this combination of teachings that lead to the examiner’s position that the claim is rendered obvious. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to provide a TFT with an electron mobility in the range of 35 cm2/V·s to about 70 cm2/V·s, as was done in 983, for the device of 843 since it is clear that through modifying the materials and their ratios of the corresponding oxide semiconductor layers that the bulk mobility may be changed to meet the requirements of the user and achieve higher field effect mobility transistors such that this limitation is considered at least routine optimization (see MPEP 2144.05.II). Claim(s) 10 stand(s) rejected under 35 U.S.C. 103 as being obvious in view of US 2017/0186843 A1, Hosaka et al.; 06/2017; (“843”) and further in view of US 2016/0071983 A1; Yamazaki, Shunpei et al.; 09/2014; (“983”). Claims which depend on claim 10 stand rejected as described above.
Applicant’s arguments regarding claim 16, see page 12 of the remarks, filed 06/09/2025, with respect to the 35 U.S.C. 103 rejections of claim 16 in view of the believed allowability of claim 10 on which it depends have been fully considered but are not found persuasive. As described above, claim 10 stands rejected under 35 U.S.C. 103 such that claim 10 is not interpreted to be allowable for its dependency.
Conclusion
Applicant's amendment necessitated the modified ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/TYLER J WIEGAND/Examiner, Art Unit 2812
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812