DETAILED ACTION
This action is responsive to the amendment to the claims received on 04/15/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claim(s) 7 and 26-36 is/are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim.
Newly submitted claim(s) 38-41 is/are directed to an invention that is independent or distinct from the invention originally claimed for the following reasons: All of the originally filed claims on 05/12/2021, and other current non-withdrawn claims 1, 4-6, 9, 21-22, 25, and 37, is/are interpreted as requiring, or at least allowing for, the inclusion of a bottom gate in the TFT structure. See for example originally filed (05/12/2021) claims 7, 10-11, and 18 all of which specifically recite the inclusion of a bottom gate electrode. In contrast, new claim 38 (and new claims 39-41), specifically recites “the TFT being a single top gate TFT” which is interpreted by the examiner to exclude any bottom gate structures.
There is a serious search and/or examination burden for the patentably distinct species as set forth above because at least the following reason(s) apply: the species or groupings of patentably indistinct species require a different field of search (e.g., searching different classes/subclasses or electronic resources, or employing different search strategies or search queries). For example, the examiner would have to restrict perform additional new search queries to particularly TFTs which do not include a bottom gate structure in combination with all of the other required limitations of the new claims.
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claim(s) 38-41 is/are withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/15/2026 has been considered by the examiner and made of record in the application file.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 4-5, 9, 21-22, 25, and 37 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2017/0186843 A1, Hosaka et al.; 06/2017; (“Hosaka”).
Regarding Claim 1. Hosaka discloses A device (Figure 40A), comprising:
a substrate (#102, Figure 40A, substrate);
a thin film transistor (TFT) (#100F, Figure 40A, oxide semiconductor thin film transistor) disposed over the substrate (Figure 40A, the transistor is over #102), the TFT being a single top gate TFT (Figure 40A, the transistor comprises only one top gate #112, which functions as a gate according to [0467]) comprising:
a metal oxide channel (#108, Figure 40A, oxide semiconductor film which includes a channel functionality according to [0572]) having a first metal oxide layer (#108_3, Figure 40A, oxide semiconductor film), a second metal oxide layer (#108_2, Figure 40A, oxide semiconductor film), and a third metal oxide layer (#108_1, Figure 40A, oxide semiconductor film), the third layer metal oxide disposed closer to the substrate than the first metal oxide layer and the second metal oxide layer (Figure 40A, #108_1 is closer to #102 than #108_2 and #108_3), the second metal oxide layer disposed on the third metal oxide layer (Figure 40A, #108_2 is disposed on #108_1), the first metal oxide layer disposed on the second metal oxide layer (Figure 40A, #108_3 is disposed on #108_2), the second metal oxide layer separating the first metal oxide layer from the third metal oxide layer (Figure 40A, #108_2 is separating #108_3 from #108_1), the second metal oxide layer ([0580], “an oxide semiconductor film formed using a metal oxide target whose atomic ratio of In to Ga and Zn is 4:2:4.1 is used as the oxide semiconductor film 108_2”) having a greater electron mobility than the first metal oxide layer and the third metal oxide layer ([0580], “an oxide semiconductor film formed using a metal oxide target whose atomic ratio of In to Ga and Zn is 1:3:2 is used as the oxide semiconductor film 108_1/3”) ([0587]-[0589], #108_2 provides the greatest mobility as the primary path through which electrons travel), the electron mobility of the second metal oxide layer being greater than or equal to 30 cm2/V·s ([0393], H1 is an example of a film utilizing In : Ga : Zn in a 4:2:4.1 ratio and [0398]-[0402], H1 is shown in Figure 30A and “the field-effect mobility of 30 cm2/V·s or higher which is shown in FIG. 30A”), wherein the second metal oxide layer comprises indium (In), zinc (Zn), and oxygen (O) ([0580], “an oxide semiconductor film formed using a metal oxide target whose atomic ratio of In to Ga and Zn is 4:2:4.1 is used as the oxide semiconductor film 108_2”, i.e. #108_2 comprises indium, zinc, and oxygen as it is an oxide semiconductor film);
a gate insulator layer (#110, Figure 40A, gate insulating film according to [0468]) disposed contacting a top surface of the first metal oxide layer of the metal oxide channel (Figure 40A, #110 is disposed contacting a top surface of #108_3);
a gate electrode (#112, Figure 40A, conductive film functioning as a gate electrode according to [0467]) disposed on the gate insulator layer (Figure 40A, #112 is disposed on #110);
a buffer layer (#104, Figure 40A, insulating film that improves the interface with the oxide semiconductor film, according to [0484], as a buffer layer) disposed on and in contact with the substrate (Figure 40A, #104 is disposed on and in contact with #102), the buffer layer disposed below the metal oxide channel and in direct contact with the third metal oxide layer (Figure 40A, #104 is disposed below #108 and is in direct contact with #108_1);
a single inter-layer dielectric (ILD) layer (#116, Figure 40A, insulating film) disposed over and in contact with the gate insulator layer, the gate electrode, sidewalls of the metal oxide channel and a top surface of the first metal oxide layer (Figure 40A, #116 is disposed over and in contact with #110, #112, sidewalls of #108_1-#108_3, and a top surface of #108_3);
a source electrode (#120a, Figure 40A, conductive film functioning as a source electrode according to [0467]) disposed on and in contact with the single ILD layer (Figure 40A, #120a is in contact with and disposed on #116), the source electrode contacting the top surface of the first metal oxide layer of the metal oxide channel by a first via through the single ILD layer (Figure 40A, #120a contacts a top surface of #108_3 by a first via through #116), the single ILD layer extending from the top surface of the first metal oxide layer along the first via to a bottom surface of the source electrode (Figure 40A, #120a is observed to have narrowing tapered sidewalls, which may be interpreted as part of the bottom surface of #120a, as it traverses through the via such that #116 extends from the top surface of the metal oxide channel along the first via to the bottom surface of #120a); and
a drain electrode (#120b, Figure 40A, conductive film functioning as a drain electrode according to [0467]) disposed on and in contact with the single ILD layer (Figure 40A, #120b is in contact with and disposed on #116), the drain electrode contacting the top surface of the first metal oxide layer of the metal oxide channel by a second via through the single ILD layer (Figure 40A, #120b contacts a top surface of #108_3 by a first via through #116), the single ILD layer extending from the top surface of the first metal oxide layer along the second via to a bottom surface of the drain electrode (Figure 40A, #120b is observed to have narrowing tapered sidewalls, which may be interpreted as part of the bottom surface of #120b, as it traverses through the via such that #116 extends from the top surface of the metal oxide channel along the first via to the bottom surface of #120b),
the single ILD layer disposed between the metal oxide channel and the source electrode (Figure 40A, #116 is at least partially disposed between #108 and the top portion of #120a on the left side of the first via through #116).
Regarding Claim 4. Hosaka discloses The device of claim 1, wherein the first metal oxide layer and the third metal oxide layer are selected from the group consisting of In-Sn-O, In-Ga-O, In-Zn-O, In-Zn-Sn-O, In-Ga-Zn-O, In-Ga-Sn-O, In-Ga-Zn-Sn-O, and combinations thereof ([0580], “an oxide semiconductor film formed using a . . . atomic ratio of In to Ga and Zn is used as . . .108_1 . . . and an oxide semiconductor film formed using a . . . atomic ratio of In to Ga and Zn is 1:3:2 is used as . . . 108_3”, i.e. all three layers of #108 are formed from In-Ga-Zn-O).
Regarding Claim 5. Hosaka discloses The device of claim 1, wherein each layer of the metal oxide channel has a thickness from about 0.5 nm to about 50 nm ([0393], Sample H1 described above as functioning as the second metal oxide layer has a thickness of approximately 40 nm, and according to [0458], the overall thickness of the entire film (comprising all three layers) is 3nm to 60 nm such that the first and third layers made of the same material as described above are necessarily around 10 nm thick).
Regarding Claim 9. Hosaka discloses The device of claim 1, wherein the TFT has a threshold voltage of about -0.5 V to about 2.5 V (Figure 30A, [0400]-[0402], sample H1, which functions as the channel of the transistor as #108_2 as described above (see [0585]), is observed to have a threshold voltage of approximately 0 V).
Regarding Claim 21. Hosaka discloses The device of claim 1, wherein the first metal oxide layer and the third metal oxide layer include Ga ([0580], “an oxide semiconductor film formed using a . . . atomic ratio of In to Ga and Zn is used as . . .108_1, . . . an oxide semiconductor film formed using a . . . atomic ratio of In to Ga and Zn is 1:3:2 is used as . . . 108_3”, i.e. #108_1 and #108_3 include Ga).
Regarding Claim 22. Hosaka discloses The device of claim 1, wherein the first metal oxide layer includes In, Ga, and Zn ([0580], “an oxide semiconductor film formed using a . . . atomic ratio of In to Ga and Zn is 1:3:2 is used as . . . 108_3”, i.e. #108_3 includes In, Ga, and Zn).
Regarding Claim 25. Hosaka discloses The device of claim 1, wherein the third metal oxide layer has a larger concentration of Ga than the second metal oxide layer ([0580], “an oxide semiconductor film formed using a metal oxide target whose atomic ratio of In to Ga and Zn is 1:3:2 is used as the oxide semiconductor film 108_1, an oxide semiconductor film formed using a metal oxide target whose atomic ratio of In to Ga and Zn is 4:2:4.1 is used as the oxide semiconductor film 108_2”, i.e. #108_1 has a greater Ga concentration (50% by the ratio above) then #108_2, (around 20% by the ratio above)).
Regarding Claim 37. Hosaka discloses The device of claim 1, wherein the single ILD layer comprises silicon oxide or silicon nitride ([0500], “the insulating film 116, for example, a nitride insulating film can be used. The nitride insulating film can be formed using silicon nitride”, i.e. #116 may comprise silicon nitride).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being obvious in view of US 2017/0186843 A1, Hosaka et al.; 06/2017; (“Hosaka”) as applied to claim(s) 1 above, and further in view of US 2016/0071983 A1; Yamazaki, Shunpei et al.; 09/2014; (“Yamazaki”).
Regarding Claim 6. Hosaka discloses The device of claim 1.
Hosaka does not appear to disclose that the TFT has an electron mobility of about 35 cm2/V·s to about 70 cm2/V·s.
However, Yamazaki discloses a similar TFT (Figure 4A) wherein the channel comprises a plurality of layers (#101, #102, and #103) composed of oxide semiconductor materials ([0092]) wherein the middle oxide semiconductor layer has a greater electron mobility than the upper and lower oxide semiconductor layers ([0131], the energy gap of #102 is smaller than #101 and #103, such that the mobility of #102 is greater than #101 and #103 based on [0020]) wherein the TFT has an electron mobility of about 35 cm2/V·s to about 70 cm2/V·s (Figures 24 and 26 show example transistors of the given structure wherein one of the oxide layers in each graph has a bulk mobility of 35 cm2/V·s such that the transistor as a whole may have a mobility within the required range).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to provide a TFT with an electron mobility in the range of 35 cm2/V·s to about 70 cm2/V·s, as was done in Yamazaki, for the device of Hosaka since it is clear that through modifying the materials and their ratios of the corresponding oxide semiconductor layers that the bulk mobility may be changed (see [0138]-[0143] of Hosaka and [0490]-[0492], “the difference in the field-effect mobility shown in FIGS. 24 and 26 became remarkable depending on the oxide semiconductor materials and the stack order of layers of the oxide semiconductor stacked layer . . . electrical characteristics (the field-effect mobility and the off-state current in this example) of a transistor can be changed variously by a stacked layer of oxide semiconductor layers whose band gaps are different from each other without changing the structure of the transistor. . . electrical characteristics of a transistor can be adjusted with high accuracy, providing the transistor with appropriate electrical characteristics”) to meet the requirements of the user and achieve higher field effect mobility transistors such that this limitation is considered both routine optimization and overlapping ranges; see MPEP 2144.05.II and MPEP 2144.05.I).
Response to Arguments/Amendments
Applicant’s amendments to claim 1 and corresponding arguments, see pages 10-11 of the remarks, filed 04/15/2026, with respect to the 35 U.S.C. 102 rejection of claim 1 as being anticipated by US 2017/0186843 A1, Hosaka et al.; 06/2017; (“Hosaka”), along with its dependent claims, have been fully considered but are not found persuasive.
Applicant’s position is that Hosaka does not disclose a single inter-layer dielectric (ILD) layer disposed over and in contact with the gate insulator layer, the gate electrode, sidewalls of the metal oxide channel and a top surface of the first metal oxide layer as recited in claim 1. During the interview on 03/19/2026, the examiner indicated that depending on how the amendments were written in relation to the single ILD layer structure, they may overcome the cited prior art. Regrettably, the current amendments do not appear to overcome the prior art. In particular, Hosaka discloses a single inter-layer dielectric (ILD) layer (#116, Figure 40A, insulating film) disposed over and in contact with the gate insulator layer, the gate electrode, sidewalls of the metal oxide channel and a top surface of the first metal oxide layer (Figure 40A, #116 is disposed over and in contact with #110, #112, sidewalls of #108_1-#108_3, and a top surface of #108_3).
Claim(s) 1, 4-5, 9, 21-22, 25, and 37 stand(s) rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2017/0186843 A1, Hosaka et al.; 06/2017; (“Hosaka”).
Claim(s) 6 stand(s) rejected under 35 U.S.C. 103 as being obvious in view of US 2017/0186843 A1, Hosaka et al.; 06/2017; (“Hosaka”) as applied to claim(s) 1 above, and further in view of US 2016/0071983 A1; Yamazaki, Shunpei et al.; 09/2014; (“Yamazaki”).
Applicant’s introduction of new claims 38-41 and corresponding arguments, see page 11 of the remarks, filed 04/15/2026, with respect to the allowability of the new claims for their similar subject matter to claim 1 have been fully considered. However, as described above, claim(s) 38-41 is/are withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/TYLER J WIEGAND/Examiner, Art Unit 2812
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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