DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on June 28, 2023 has been entered.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters “430” and “460” have both been used to designate “redistribution layer”; reference characters “410” and “422” have both been used to designate “molding compound”; reference characters “508” and “558” have both been used to designate “wiring layer”; reference characters “410” and “422” have both been used to designate “molding compound”; reference characters “526a”, “526b”, “526c”, “542”, “532a” and “532b” have been used to designate “insulating layer”; . Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings (Figs. 4A-4I) are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: “410”” ([0028]). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “450” has been used to designate “semiconductor die”, “packaged semiconductor die”, “packaged die” and “die”; reference character “120” has been used to designate both “interposer” and “semiconductor interposer”. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities: “bumps and wires” should read “bumps with wires” ([0039], lines 3, 6 and 8); “7A-10D” should read “7A-7C, 8, 9A, 9B, 10A-10D ([0045], line 1); and one of “415”” should read “415^” ([0045], line 3).
Appropriate correction is required.
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-15 and 21, 22 and 25-27 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. There is no support in the original specification (in the prior-filed application #13/475,674, filed on May 18, 2012) for the claim limitations of “a substrate; a plurality of metal pillars on a top surface of the substrate; a semiconductor component on the substrate, wherein the semiconductor comprises one or more dies; a mold compound laterally surrounding the semiconductor component, wherein the mold compound has a top surface above the top surface of the semiconductor component, and the mold compound is separated from the top surface of the semiconductor component; an interposer laterally adjacent to each of the plurality of metal pillars”, as recited in claim 1; “each of the plurality of metal pillars includes a solder cap”, as recited in claims 2 and 11; “an interconnect over the semiconductor component and the substrate”, as recited in claims 5 and 12; “the mold compound directly contacts the semiconductor component”, as recited in claims 7 and 15; “the interposer directly contacts each of the plurality of metal pillars”, as recited in claim 8; “a substrate; a plurality of metal pillars on a top surface of the substrate; a semiconductor component on the substrate, wherein the semiconductor comprises one or more dies; a mold compound laterally surrounding the semiconductor component; an interposer laterally adjacent to each of the plurality of metal pillars; a first plurality of solder balls on a bottom surface of the substrate; an insulating layer directly contacting a top surface of the semiconductor component”, as recited in claim 9; “a substrate; a plurality of metal pillars on a top surface of the substrate; a semiconductor component on the substrate, wherein the semiconductor comprises one or more dies; a second molding compound laterally encapsulating the semiconductor component, wherein the second molding compound has a top surface above the top surface of the semiconductor component; the second molding compound is between the first molding compound and the semiconductor component, and an interface exists between the first molding compound and the second molding compound; wherein the top surface of the second molding compound is coplanar with a top surface of the insulating layer; an insulating layer over the semiconductor component, wherein the top surface of the second molding compound is coplanar with a top surface of the insulating layer”, as recited in claim 21; “a top surface of the insulating layer is coplanar with a top surface of the mold compound”, as recited in claim 27; “a redistribution layer (RDL) over the semiconductor component, wherein a top-most surface of the RDL is co-planar with a top-most surface of the mold compound”, as recited in claim 28; “the mold compound directly contacts … the semiconductor component”, as recited in claim 29; “the bottommost surface of the mold compound is co-planar with a bottommost surface of the semiconductor component”, as recited in claim 30.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-15 and 25-30 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claimed limitation of "a mold compound laterally surrounding the semiconductor component", as recited in claims 1 and 9, is unclear as to which mold compound is being referred to in the claim since the specification discloses multiple mold compounds.
The claimed limitation of "an interposer laterally adjacent to each of the plurality of metal pillars", as recited in claims 1 and 9, which indefinite and renders the claim uncertain because said limitation is inconsistent with the (specification) disclosure: i.e. paragraph [0028], lines 6-8 and Fig. 4A disclose that "the interposer (frame) includes through-molding vias (TMVs) 415". See MPEP §2173.03.
The claimed limitation of "a second plurality of solder balls on an opposite side of the interposer from the plurality of metal pillars", as recited in claim 14, is unclear as to whether said limitation is on one-to-one, one-to-multiple or multiple-to-one relationship between the “solder ball” and the “metal pillar” applicant refers.
Claim 25 renders indefinite as being depend on the cancelled claim 23.
The claimed limitation of "a top surface of the mold compound", as recited in claim 27, is unclear as to whether said limitation is the same as or different from "a top surface", as recited in claim 1, line 7.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-3, 5-15, 21, 22, 25-28, 29 and 30, as best understood, is/are rejected under pre-AIA 35 U.S.C. 102(b) as being anticipated by Chow et al. (2010/0144101).
As for claims 1 and 9, Chow et al. show in Fig. 3f and related text a semiconductor package 100 comprising:
a substrate 128/132/126/134/130;
a plurality of metal pillars 104 on a top surface of the substrate;
a semiconductor component 110/112 on the substrate, wherein the semiconductor component comprises one or more dies 110, and the semiconductor component has a top surface (a first height);
a mold compound (vertical portion of) 114 surrounding the semiconductor component, wherein the mold compound has a top surface (a second height greater than the first height) above the top surface of the semiconductor component, and the mold compound is separated from the top surface of the semiconductor component;
an interposer 106 laterally adjacent to each of the plurality of metal pillars;
(a first plurality of solder balls on a bottom surface of the substrate 136; and
an insulating layer (horizontal portion of) 114 directly contacting a top surface of the semiconductor component).
As for claims 2 and 11, Chow et al. show each of the plurality of metal pillars includes a solder cap (top end portion of) 104 (Fig. 3f).
As for claim 3, Chow et al. show a top surface of the solder cap is co-planar with the top surface of the mold compound (Fig. 3f).
As for claims 5 and 12, Chow et al. show an interconnect (not shown) over the semiconductor component and the substrate ([0038], lines 22-24).
As for claim 6, Chow et al. show the mold compound directly contacts the interposer (Fig. 3f).
As for claims 7 and 15, Chow et al. show the mold compound directly contacts the semiconductor component (Fig. 4g).
As for claim 8, Chow et al. show the interposer directly contacts each of the plurality of metal pillars (Fig. 3f).
As for claim 10, Chow et al. show each of the plurality of metal pillars as the second height (Fig. 3f).
As for claim 13, Chow et al. show each of the plurality of metal pillars has a variable width ([0039], lines 9-12).
As for claim 14, Chow et al. show a second plurality of solder balls 236 on an opposite side of the interposer from the plurality of metal pillars (Fig. 3f).
As for claim 21, Chow et al. show in Fig. 3f and related text a semiconductor package 100 comprising:
a substrate 128/132/126/134/130;
a plurality of metal pillars 104 on a top surface of the substrate;
a semiconductor component 110/112 on the substrate, wherein the semiconductor component comprises one or more dies 110, and the semiconductor component has a top surface;
a first molding compound 106 encapsulating the plurality of metal pillars;
a second molding compound (vertical portion of) 114 laterally encapsulating the semiconductor component, wherein the second molding compound has a top surface above the top surface of the semiconductor component; the second molding compound is between the first molding compound and the semiconductor component, and an interface exists between the first molding compound and the second molding compound; and
an insulating layer (horizontal portion of) 114 over the semiconductor component, wherein the top surface of the second molding compound is coplanar with a top surface of the insulating layer.
As for claim 22, Chow et al. show a width of each of the plurality of metal pillars is non-uniform ([0039], line 9-12).
As for claim 25, Chow et al. show the first molding compound comprises an electrically isolating material ([0039], lines 14-15).
As for claim 26, Chow et al. show an insulating layer (horizontal portion of) 114 directly contacting a top surface of the one or more dies (Fig. 3f).
As for claim 27, Chow et al. show a top surface of the insulating layer is coplanar with a top surface of the mold compound (Fig. 3f).
As for claim 29, Chow et al. show the mold compound directly contacts the interposer and directly contacts the semiconductor component (Fig. 3f).
As for claim 30, Chow et al. show a bottommost surface of the mold compound is co-planar with a bottommost surface of the semiconductor component (Fig. 3f).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim 4, as best understood, is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Chow et al. (2010/0144101).
Chow et al. disclosed substantially the entire claimed invention, as applied to claim 1 above, except a height of each of the plurality of metal pillars ranges from 10 microns (µm) to 600 µm.
It would have been obvious to one having ordinary skill in the art at the time of the invention was made to include a height of each of the plurality of metal pillars ranging from 10 microns (µm) to 600 µm, in order to optimize the performance of the device. Furthermore, it has been held that where then general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Furthermore, it has been held in that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990). Note that the law is replete with cases in which when the mere difference between the claimed invention and the prior art is some dimensional limitation or other variable within the claims, patentability cannot be found. The instant disclosure does not set forth evidence ascribing unexpected results due to the claimed dimensions. See Gardner v. TEC Systems, Inc., 725 F.2d 1338 (Fed. Cir. 1984), which held that the dimensional limitations failed to point out a feature which performed and operated any differently from the prior art.
Response to Arguments
Applicant's arguments filed December 16, 2022 have been fully considered but they are not persuasive.
Applicant argues that “with respect to claim 1, a non-limiting example of the recited claim language is depicted in Figure 5, which includes element 542 as a substrate; element 450 as a semiconductor component; element 422 as a mold compound; and element 410 as an interposer”.
The examiner respectfully disagrees because elements 542, 450, 410 are disclosed as “an insulating layer”, “a semiconductor die” and “a molding compound”, respectively. Therefore, the claim lacks written description support under 35 U.S.C. §112(a).
Applicant argues that “with respect to "an interconnect," Applicants respectfully note that element 508, a wiring layer is a non-limiting example of an interconnect. The Office asserted that "interconnect" is broader than an RDL or a pillar bump. (Office Action at page 5). However, the rejection is a written description rejection, not an enablement rejection. To the extent that the Office attempts to assert an enablement rejection, the Office failed to provide any analysis of the Wands factors, as required by MPEP 2164.
The examiner respectively disagrees because the examiner never rejected the term “interconnect” under the enablement rejection.
Applicant argues that “with respect to the interposer directly contacting the metal pillars; Figure 5 clearly includes a non-limiting example of an interposer frame 410 directly contacting a metal pillar 415”.
The examiner respectfully disagrees because 410 is disclosed as “a molding compound” not “an interposer frame”. Therefore, the claim lacks written description support under 35 U.S.C. §112(a).
Applicant argues that “with respect to the mold compound having a top surface above a top surface of the semiconductor component, Figure 5 provides a non-limiting example of the recited claim language, including element 526a as a non-limiting example of an insulating layer”.
The examiner respectfully disagrees because 526a is part of 450 (semiconductor die); and 536a is formed below a lower surface of 524 (substrate). Therefore, the claim lacks written description support under 35 U.S.C. §112(a).
Applicant argues that Chow fails to explicitly or inherently disclose each and every element recited in claims 1, 9 and 21 because 1) "claim 1 recites "the mold compound has a top surface above the top surface of the semiconductor component", 2) "claim 9 recites "a mold compound surrounding the semiconductor component, wherein the mold compound has a second height greater than the first height ... an insulating layer directly contacting a top surface of the semiconductor component" and 3) "claim 21 recites "an insulating layer over the semiconductor component, wherein the top surface of the second molding compound is coplanar with a top surface of the insulating layer."; however, "figure 4g of Chow clearly indicates that element 214 has a top surface coplanar with a top surface of element 210".
The examiner used the embodiment of Fig. 3f for the rejection. However, the applicant's argument is referred to a different embodiment of Fig. 4g.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MEIYA LI whose telephone number is (571)270-1572. The examiner can normally be reached Monday-Friday 7AM-3PM.
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/MEIYA LI/Primary Examiner, Art Unit 2811