DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 2/3/2026 have been fully considered but they are not persuasive.
Applicant argues on page 7 of the remarks with respect to the newly added limitations of claim 1 (and similarly in claim 11 and 20), Applicant contends that Tanaka fails to teach the extended portions which extends in the second direction to be directly underneath a plurality of gate structures.
As can be seen below in the annotated fig. 2 of Tanaka, the extended portions are shown as meeting the newly added claim limitations.
The rejection is being maintained and has been updated to include the newly amended portions.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 9 and 17 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The specification as filed fails to provide support for the claimed limitation of “the wavy conductive lines are provided below the plurality of gate structures” as recited at lines 1-2 of claim 9 and lines 2-3 of claim 17. The figures show plurality of gate structures 18 directly on the substrate and isolation structures 14b in fig. 1B. This would not allow the possibility of the wavy metal lines 22 to be provided below gate structures 18.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 9 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 recites the limitation of “the wavy conductive lines are provided below the plurality of gate structures and above a gate structure” as recited at lines 1-2. It is unclear how an element can be both below and above another element.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-8, 10-12, 14-16, 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over fig. 2, 4d, 5d of Tanaka et al. (JPH0621401; hereinafter “Tanaka”; see attached English translation for paragraph numbers cited below) in view of fig. 6 of Tanaka.
Re claim 1: Tanaka teaches (e.g. figs. 2, 4d, 5d and labeled fig. 2 below) a structure comprising: a source line (source diffusion 14 serves as a common source diffusion layer; e.g. paragraph 4) extending in a first direction (vertical direction of fig. 4; hereinafter “1D”); a plurality of gate structure (plural floating gates 21, wordlines 13, and dielectric layers 24, 25, 26 ; e.g. paragraphs 5, 25, 27; hereinafter “GS”) on opposing sides (11 are on opposite sides of common source diffusion layer 14) of the source line (14) and each of which are extending in the first direction (13 extends in the vertical direction of fig. 2; hereinafter “1D”); isolation structures (staggered pattern of isolation insulating regions 11; e.g. paragraph 25) extending in a second direction (11 extends in the horizontal direction of fig. 4; hereinafter “2D”) perpendicular to the first direction (1D), the isolation structures (11) being in a staggered offset pattern (staggered pattern of isolation insulating regions 11; e.g. paragraph 25; hereinafter “SOP”) on the opposing sides of the source line (14) such that the isolation structures (11) on a first side (11 of the left side of 14; hereinafter “11F”) of the source line (14) are laterally offset from the isolation structures (11) on a second side (11 of the left side of 14; hereinafter “11S”) of the source line (14), the isolation structures (11) on a same side of the source line (14) being adjacent to a semiconductor substrate (23), and the staggered offset pattern (SOP) avoiding breakdown of the source line (14) between the isolation structures (11); and wavy conductive lines (bit lines 18 which are wavy as shown in fig. 2; e.g. paragraph 24) substantially aligned along the second direction (2D) and extending between and along a longitudinal side of the isolation structures (11) on the first side (11F) of the source line (14) and the isolation structures (11) on the second side (11S) of the source line (14), wherein the source line (14) comprises extended portions (portions labeled “EP”) which extend in the second direction (2D) to be directly underneath the plurality of gate structures (GS).
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Tanaka’s fig. 2 may be considered as being silent as to explicitly teaching the wavy conductive lines overlapping multiple corners on a same side of each of the isolation structures on the opposing sides of the source line.
Tanaka’s fig. 6 teaches the wavy conductive lines (18) overlapping multiple corners (fig. 6 shows corners of 11 on opposing sides of 14 is overlapped by 18) on a same side of each of the isolation structures (11) on the opposing sides of the source line (14).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the express illustration of the conductive lines 18 and how it behaves on corners of the isolation structures as shown in fig. 6 into the structure of embodiment of fig. 2 in order to have the predictable result of using a wavy conductive lines that is known to effectively operate and shows the wavy conductive lines beyond what is illustrated in fig. 2.
Re claim 2: Tanaka teaches the structure of claim 1, wherein the gate structure (GS) comprises a floating gate structure (floating gate 21; e.g. paragraph 5).
Re claim 3: Tanaka teaches the structure of claim 1, wherein the isolation structures (11) comprise shallow trench isolation structures (11 extends into the substrate 23 in a shallow manner) within semiconductor material (23).
Re claim 4: Tanaka teaches the structure of claim 3, wherein the source line (14) comprises the semiconductor material (23).
Re claim 5: Tanaka teaches the structure of claim 1, wherein the source line (14) comprises bulk semiconductor material (23).
Re claim 6 Tanaka teaches the structure of claim 1, wherein the source line (14) comprises semiconductor (23) on insulator (11) material.
Re claim 7: Tanaka teaches the structure of claim 1, wherein the isolation structures (11) and the source line (14) are planar (each of 11 and 14 have planar portions).
Re claim 8: Tanaka teaches the structure of claim 1, wherein the isolation structures (11) on the first side (11F) are laterally shifted along the first direction (1D) of the source line (14) from the isolation structures (11) on the second side (11S) by up to 1/2 pitch (the shift is half the pitch of each 11).
Re claim 10: Tanaka teaches, as best understood, the structure of claim 1, wherein the wavy conductive lines (in view of fig. 2 and 6, 18) comprise curved sections which overlap the multiple corners (fig. 6 shows corners on the same side of each isolation structure 11 is overlapped by 18) on the same side of each of the isolation structures (11) on the opposing sides of the source line (14).
Re claim 11: Tanaka teaches (e.g. figs. 2, 4d, 5d and labeled fig. 2 above) a structure comprising: a source line (source diffusion 14 serves as a common source diffusion layer; e.g. paragraph 4) comprising semiconductor material (bulk semiconductor substrate 23) extending in a first direction (vertical direction of fig. 4; hereinafter “1D”); a floating gate structure (floating gate 21; e.g. paragraph 5) on at least a first side (right side of 14; hereinafter “1S”) of the source line (14); a first set of shallow trench isolation structures (isolation insulating regions 11 to the right of 14; e.g. paragraph 25; hereinafter “11F”) within the semiconductor material (23) and which extend in a second direction (11 extends in the horizontal direction of fig. 4; hereinafter “2D”) and perpendicular to the first direction (1D) of the source line (14) on the first side (1S) of the source line (14); a second set (isolation insulating regions 11 to the left of 14; e.g. paragraph 25; hereinafter “11S”) of shallow trench isolation structures (11) within the semiconductor material (23) and which extend in the second direction (2D) from and perpendicular to a second, opposing side (left side of 14; hereinafter “2S”) of the source line (14), the second set of shallow trench isolation structures (11S) being in a staggered offset pattern (staggered pattern of isolation insulating regions 11; e.g. paragraph 25; hereinafter “SOP”) from the first set of shallow trench isolation structures (11F) along the first direction (1D) of the source line (14), and the staggered offset pattern (SOP) avoiding breakdown of the source line (14) between the first and second set of shallow trench isolation structures (11F, 11S); and wavy conductive lines (bit lines 18 which are wavy as shown in fig. 2; e.g. paragraph 24) substantially aligned along the second direction (2D) and extending between and along a longitudinal side of the first set of shallow trench isolation structures (11F) and the second set of shallow trench isolation structures (11S), wherein the source line (14) comprises extended portions (portions labeled “EP”) which extend in the second direction (2D) to be directly underneath the plurality of gate structures (GS).
Tanaka’s fig. 2 may be considered as being silent as to explicitly teaching the wavy conductive lines overlapping multiple corners on a same side of the first set of isolation structures on the opposing sides of the source line and multiple corners of the second set of isolation structures on the opposing sides of the source line.
Tanaka’s fig. 6 teaches the wavy conductive lines (18) overlapping multiple corners (fig. 6 shows corners of 11F on opposing sides of 14 is overlapped by 18) on a same side of the first set of isolation structures (11F) on the opposing sides of the source line (14) and multiple corners (fig. 6 shows corners of 11S on opposing sides of 14 is overlapped by 18) of the second set of isolation structures (11S) on the opposing sides of the source line (14)
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the express illustration of the conductive lines 18 and how it behaves on corners of the isolation structures as shown in fig. 6 into the structure of embodiment of fig. 2 in order to have the predictable result of using a wavy conductive lines that is known to effectively operate and shows the wavy conductive lines beyond what is illustrated in fig. 2.
Re claim 12: Tanaka teaches the structure of claim 11, wherein the floating gate structure (21) comprises polysilicon material (polycrystalline Si; e.g. paragraph 6).
Re claim 14: Tanaka teaches the structure of claim 11, wherein the semiconductor material (23) comprises bulk semiconductor material.
Re claim 15: Tanaka teaches the structure of claim 11, wherein the semiconductor material (23) comprises semiconductor (silicon material of substrate; e.g. paragraph 25) on insulator (11) material.
Re claim 16: Tanaka teaches the structure of claim 11, wherein the first set of shallow trench isolation structures (11F) are laterally shifted along the first direction (1D) of the source line (14) from the second set of shallow trench isolation structures (11S) by up to 1/2 pitch (the shift is half the pitch of each 11).
Re claim 18: Tanaka teaches the structure of claim 17, wherein the wavy conductive lines (18) are provided above (bit line 18 are shown above floating gate 21 a can be seen in fig. 5d) the floating gate structure (21).
Re claim 19: Tanaka teaches, as best understood, the structure of claim 11, wherein the wavy conductive lines (in view of fig. 2 and 6, 18) comprise curved sections which overlap the multiple corners (fig. 6 shows corners on the same side of each isolation structure 11 is overlapped by 18) on the same side of the first set of shallow trench isolation structures (11F) on the first side of the source line (14) and which also overlap the multiple corners of the second set of shallow trench isolation structures (11S) on the opposing side of the source line (14).
Re claim 20: Tanaka teaches (e.g. figs. 2, 4d, 5d and labeled fig. 2 above) a method comprising: forming a source line (source diffusion 14 serves as a common source diffusion layer; e.g. paragraph 4) extending in a first direction (vertical direction of fig. 4; hereinafter “1D”); forming a plurality of gate structure (floating gate 21, wordline 13, and dielectric layers 24, 25, 26 ; e.g. paragraphs 5, 25, 27; hereinafter “GS”) on opposing sides of the source line (14) and each of which are extending in the first direction (vertical direction of fig. 4; hereinafter “1D”); forming isolation structures (staggered pattern of isolation insulating regions 11; e.g. paragraph 25) extending in a second direction (11 extends in the horizontal direction of fig. 4; hereinafter “2D”) perpendicular to the first direction (1D), the isolation structures (11) being in a staggered offset pattern (staggered pattern of isolation insulating regions 11; e.g. paragraph 25; hereinafter “SOP”) on the opposing sides of the source line (14) such that the isolation structures (11) on a first side (11 of the left side of 14; hereinafter “11F”) of the source line (14) are laterally offset from the isolation structures (11) on a second side (11 of the left side of 14; hereinafter “11S”) of the source line (14), the isolation structures (11) on a same side of the source line (14) being adjacent to a semiconductor substrate (23), and the staggered offset pattern (SOP) avoiding breakdown of the source line (14) between the isolation structures (11); and forming wavy conductive lines (bit lines 18 which are wavy as shown in fig. 2; e.g. paragraph 24) substantially aligned along the second direction (2D) and extending between and along a longitudinal side of the isolation structures (11) on the first side (11F) of the source line (14) and the isolation structures (11) on the second side (11S) of the source line (14), wherein the source line (14) comprises extended portions (portions labeled “EP”) which extend in the second direction (2D) to be directly underneath the plurality of gate structures (GS).
Tanaka’s fig. 2 may be considered as being silent as to explicitly teaching the wavy conductive lines overlapping multiple corners on a same side of each of the isolation structures on the opposing sides of the source line.
Tanaka’s fig. 6 teaches the wavy conductive lines (18) overlapping multiple corners (fig. 6 shows corners of 11 on opposing sides of 14 is overlapped by 18) on a same side of each of the isolation structures (11) on the opposing sides of the source line (14).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the express illustration of the conductive lines 18 and how it behaves on corners of the isolation structures as shown in fig. 6 into the structure of embodiment of fig. 2 in order to have the predictable result of using a wavy conductive lines that is known to effectively operate and shows the wavy conductive lines beyond what is illustrated in fig. 2.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka as applied to claim 11 above, and further in view of Hu et al. (US 5,511,020; hereinafter “Hu”).
Re claim 13: Tanaka teaches substantially the entire structure as recited in claim 11 except explicitly teaching wherein the floating gate structure comprises workfunction metal.
Hu teaches the floating gate structure (floating gate 207; e.g. column 4, line 32) comprises workfunction metal (platinum or polysilicon; e.g. column 4, line 34).
It would have been obvious to one of ordinary skill in the art, absent unexpected results, at the time of effective filing to use the workfunction metal layer instead of polysilicon for the floating gate as taught by Hu in the device of Tanaka in order to have the predictable result of using a metal material which has higher conductivity, allowing for easier programming of the memory cell.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JESSE Y MIYOSHI whose telephone number is (571)270-1629. The examiner can normally be reached M-F, 8:30AM-5:00PM.
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/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898
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