DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/06/2026 has been entered.
Response to Amendment
Claim 5 has been cancelled; Claims 1, 12 and 19 have been amended; claim 21 has been newly added; and claims 1-4, and 6-21 are currently pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, and 6-18 are rejected under 35 U.S.C. 103 as being unpatentable over Mailho et al. (USPN 6031211, hereinafter “Mailho”) in view of Komatsu (WO 2010110169 A1, hereinafter “Komatsu”), Shimizu (US 2007/0224839 A1, hereinafter “Shimizu”),
Moslehi et al. (USPN 6705394 B1, hereinafter “Moslehi”), and Andrew (USPN
6,922,603 B1, hereinafter "Andrew").
In regards to claim 1, Mailho discloses (See, for example, Figs. 1-4) an apparatus for controlling wafer uniformity, comprising:
a plurality of temperature control elements , wherein each of the temperature control elements corresponds to a different portion of a wafer respectively such that the temperature control elements correspond to different portions of the wafer (“…independently controlled heating zones within …induction coils along with a feedback control system to heat and cool a semiconductor wafer at a substantially uniform rate and to maintain the wafer at a substantially constant and uniform temperature.”, see, for example, Col. 2 line 66 thru col. 3 line 4),
at least one of the temperature control elements is configured to adjust, based on an instruction from a processor, temperature of at least one portion of the wafer for controlling temperature uniformity of the wafer ( “In FIG. 4, each of temperature sensors 28 is connected to an input terminal of control circuit 30 to provide information indicative of the temperature of associated portion of susceptor 14 and chamber top 12, which is then used by control circuit 30 to determine temperature fluctuations across susceptor 14 and chamber top 12. Control circuit 30 then adjusts control signals CSP.sub.n and CS.sub.1 -CS.sub.6 accordingly to provide a uniform heating and cooling rate and to maintain a precise and uniform temperature across susceptor 14 and chamber top 12. Each sensor 28 has an associated independent control loop to compensate for temperature variations. Each independent control loop adjusts for temperature variations within its associated zone, independent of measurements from the other zones.”., See, for example, Col. 7 lines 44-57); and
a sensing element (28) configured to detect temperature of the corresponding portion of the wafer (See, for example, Col. 7 lines 30-43).
Mailho is silent about the temperature of the at least one portion is adjusted in response to a temperature map of the wafer, wherein the temperature map is determined based on a plurality of plasma processing conditions, wherein the plurality of plasm processing conditions is determined by a multiple-parameter optimization process.
Komatsu while disclosing a plasma process teaches (See, for example, Figs. 1, 3) the temperature of the at least one portion is adjusted in response to a temperature map of the wafer, wherein the temperature map is determined based on a plurality of plasma processing conditions, wherein the plurality of plasm processing conditions is determined by a multiple-parameter optimization process (The resistance heater group 88 is connected to a power supply line L (L1 to L6). The power supply line L is drawn out of the processing vessel 32 through the cylindrical support column 64. Each power supply line L is connected to a heater control unit 92 having a heater power supply and a computer, and controls the temperature of the wafer W by controlling the power supplied to the resistance heater group 88. In order to control the temperature, a thermocouple (not shown) is provided …
In the illustrated example, it is divided into two concentric (annular) zones, a circular inner peripheral zone 94 at the center of the mounting table main body 62 and a ring-shaped outer peripheral zone 96 surrounding the inner peripheral zone 94. In the illustrated example, since the outer peripheral zone 96 is located on the outermost periphery, it becomes the outermost peripheral zone.
…
while the plasma processing such as the film forming process is performed on the wafer W, the heater control unit 92 transfers the resistance heating heaters 98 and 100 in the zones 94 and 96 to each other by feedback control. Individually controlled power is supplied. …. Electric power is supplied to the resistance heater 98 in the inner peripheral zone 94 through the feed lines L5 and L6 by feedback control, and the temperature control of the inner peripheral zone 94 is performed as a whole.
On the other hand, the outermost peripheral resistance heater 100 which is a resistance heater in the outermost peripheral zone (outer peripheral zone) 96 is divided into four heater sections 100A to 100D in the circumferential direction, and the four outermost peripheral power supply lines L1 to By individually changing the electrical state (potential etc.) of L4, the power supply mode to the heater sections 100A to 100D can be changed.
…
For example, in the case where the temperature of the wafer peripheral portion corresponding to the location where the gate valve 44 and the observation window 47 facing the gate valve 44 are provided on the side wall of the processing vessel 32 tends to decrease. When the heater sections corresponding to the window 47 are, for example, the heater sections 100A and 100C, respectively, the power input to these heater sections 100A and 100C is made larger than the power input to the other heater sections 100B and 100D. For example, the temperature compensation is performed for the portion where the temperature tends to decrease by increasing the time during which the current flows in the pattern as shown in the aspect 3. See, for example, pages 4, 7, and 9)
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Mailho by Komatsu because this would help individually control the electrical states of the outer peripheral feed lines by heater control unit such that temperature distribution at the periphery of the semiconductor wafer is simply controlled.
Mailho as modified above is silent about that a plurality of temperature control elements are arranged in multiple rows and multiple columns within a wafer chuck.
Shimizu while disclosing a heat-treating apparatus teaches (See, for example, Fig. 2) a plurality of temperature control elements (32) are arranged in multiple rows and multiple columns within a wafer chuck (28).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Mailho by Shimizu because this would allow the temperature to be rapidly raised or lowered without being influenced by the type of surface material of the substrate while maintaining an in-surface uniformity of temperature, and would help the substrate to be heated with a high efficiency.
Mailho is silent about that each of the temperature control elements is configured to individually control temperature of a corresponding portion of the wafer, and each temperature control element comprises:
a heating element configured to increase temperature of a corresponding portion of the wafer;
an active cooling element configured to decrease temperature of the corresponding portion of the wafer, the active cooling element distinct from and structurally different from the heating element.
Moslehi while disclosing rapid thermal cycling of substrates teaches (See, for example, Fig. 3) each of the temperature control elements is configured to individually control temperature of a corresponding portion of the wafer (See, for example, Col. 6 lines 18-33), and each temperature control element comprises:
a heating element (106, 108/110) configured to increase temperature of a corresponding portion of the wafer (102);
an active cooling element (112, 114/116) configured to decrease temperature of the corresponding portion of the wafer (102), the active cooling element (112, 114/116) distinct from and structurally different from the heating element (106, 108/110).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Mailho by Moslehi because having the heater block and the cooler block divided into different zones would help better control radial temperature gradient of the substrate.
Mailho as modified above further fails to explicitly teach a processor to determine a critical dimension (CD) map of a wafer having an average thickness after a plasma-enhanced etching process or a plasma-enhanced polishing process, wherein the CD map includes different portions of the wafer and respective different deviations from the average thickness for the different portions, respectively.
Andrew teaches a critical dimension (CD) map of a wafer having an average thickness after a plasma-enhanced etching or polishing process
teaching measuring a quantity, e.g., thickness, at multiple locations on a top surface of a wafer after process operations including etching and polishing (see also col. 1, lines 25–55),
disclosing that semiconductor wafers undergo numerous processes including etching and polishing, and the wafer is examined to confirm the previous process was completed with an acceptable level of nonuniformities, wherein the CD map includes different portions of the wafer and respective different deviations from the average thickness for the different portions, respectively (See, Col. 2 lines 22-65),
teaching measuring a thickness at each one of the multiple locations on the wafer, converting the measured thickness at each location to a corresponding mass density value, determining an average mass density value for the wafer, and determining a standard deviation i.e., respective deviations from the average for the wafer, teaching that the 3-sigma uniformity metric quantifies a standard deviation of measurements, such as the deviations in thickness of the wafer detected by an array of measurement points across the wafer, e.g., using a 49-point array wherein each point represents approximately 1/49th of the area of the wafer i.e., different portions of the wafer, and each point has a respective measured deviation from the average thickness, describing various nonuniformity patterns across the wafer surface including center-fast, edge-fast, and asymmetric patterns corresponding to different portions exhibiting different deviations) (See also Col. 4, lines 13–32, and Col. 5, lines 1–40)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the process chamber of Mailho as modified by Komatsu and Moselehi to further include a critical dimension (CD) map of the wafer having an average thickness after a plasma-enhanced etching or polishing process, the CD map including different portions of the wafer and respective different deviations from the average thickness for the different portions because such a modification would predictably improve the process control capability of the chamber of Mailho as modified by enabling spatially-resolved feedback for compensating thickness non-uniformities introduced by etching or polishing processes, thereby improving device yield.
In regards to claim 12, Mailho discloses (See, for example, Figs. 1-4) a wafer process chamber comprising:
a support (14) configured to support a wafer (16) when the wafer (16) is placed on the support (14) and processed;
a plurality of temperature control elements coupled to the support,
wherein each of the temperature control elements corresponds to a different portion of the wafer respectively such that the temperature control elements correspond to different portions of the wafer (“…independently controlled heating zones within …induction coils along with a feedback control system to heat and cool a semiconductor wafer at a substantially uniform rate and to maintain the wafer at a substantially constant and uniform temperature.”, see, for example, Col. 2 line 66 thru col. 3 line 4),
at least one of the temperature control elements is configured to adjust, based on an instruction from a processor, temperature of at least one portion of the wafer for controlling temperature uniformity of the wafer ( “In FIG. 4, each of temperature sensors 28 is connected to an input terminal of control circuit 30 to provide information indicative of the temperature of associated portion of susceptor 14 and chamber top 12, which is then used by control circuit 30 to determine temperature fluctuations across susceptor 14 and chamber top 12. Control circuit 30 then adjusts control signals CSP.sub.n and CS.sub.1 -CS.sub.6 accordingly to provide a uniform heating and cooling rate and to maintain a precise and uniform temperature across susceptor 14 and chamber top 12. Each sensor 28 has an associated independent control loop to compensate for temperature variations. Each independent control loop adjusts for temperature variations within its associated zone, independent of measurements from the other zones.”., See, for example, Col. 7 lines 44-57); and a sensing element (28) configured to detect temperature of the corresponding portion of the wafer (See, for example, Col. 7 lines 30-43).
Mailho is silent about the temperature of the at least one portion is adjusted in response to a temperature map of the wafer, wherein the temperature map is determined based on a plurality of plasma processing conditions, wherein the plurality of plasm processing conditions is determined by a multiple-parameter optimization process.
Komatsu while disclosing a plasma process teaches (See, for example, Figs. 1, 3) the temperature of the at least one portion is adjusted in response to a temperature map of the wafer, wherein the temperature map is determined based on a plurality of plasma processing conditions, wherein the plurality of plasm processing conditions is determined by a multiple-parameter optimization process (The resistance heater group 88 is connected to a power supply line L (L1 to L6). The power supply line L is drawn out of the processing vessel 32 through the cylindrical support column 64. Each power supply line L is connected to a heater control unit 92 having a heater power supply and a computer, and controls the temperature of the wafer W by controlling the power supplied to the resistance heater group 88. In order to control the temperature, a thermocouple (not shown) is provided …
In the illustrated example, it is divided into two concentric (annular) zones, a circular inner peripheral zone 94 at the center of the mounting table main body 62 and a ring-shaped outer peripheral zone 96 surrounding the inner peripheral zone 94. In the illustrated example, since the outer peripheral zone 96 is located on the outermost periphery, it becomes the outermost peripheral zone.
…
while the plasma processing such as the film forming process is performed on the wafer W, the heater control unit 92 transfers the resistance heating heaters 98 and 100 in the zones 94 and 96 to each other by feedback control. Individually controlled power is supplied. …. Electric power is supplied to the resistance heater 98 in the inner peripheral zone 94 through the feed lines L5 and L6 by feedback control, and the temperature control of the inner peripheral zone 94 is performed as a whole.
On the other hand, the outermost peripheral resistance heater 100 which is a resistance heater in the outermost peripheral zone (outer peripheral zone) 96 is divided into four heater sections 100A to 100D in the circumferential direction, and the four outermost peripheral power supply lines L1 to By individually changing the electrical state (potential etc.) of L4, the power supply mode to the heater sections 100A to 100D can be changed.
…
For example, in the case where the temperature of the wafer peripheral portion corresponding to the location where the gate valve 44 and the observation window 47 facing the gate valve 44 are provided on the side wall of the processing vessel 32 tends to decrease. When the heater sections corresponding to the window 47 are, for example, the heater sections 100A and 100C, respectively, the power input to these heater sections 100A and 100C is made larger than the power input to the other heater sections 100B and 100D. For example, the temperature compensation is performed for the portion where the temperature tends to decrease by increasing the time during which the current flows in the pattern as shown in the aspect 3. See, for example, pages 4, 7, and 9)
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Mailho by Komatsu because this would help individually control the electrical states of the outer peripheral feed lines by heater control unit such that temperature distribution at the periphery of the semiconductor wafer is simply controlled.
Mailho as modified above is silent about that at least one of the different portions has a shape different from an annulus.
Shimizu teaches (See, for example, Fig. 2) at least one of the different portions has a shape different from an annulus.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Mailho by Shimizu because this would allow the temperature to be rapidly raised or lowered without being influenced by the type of surface material of the substrate while maintaining an in-surface uniformity of temperature, and would help the substrate to be heated with a high efficiency.
Mailho is silent about that each of temperature control element comprises:
a heating element configured to increase temperature of a corresponding portion of the wafer;
an active cooling element configured to decrease temperature of the corresponding portion of the wafer, the active cooling element distinct from and structurally different from the heating element.
Moslehi while disclosing rapid thermal cycling of substrates teaches (See, for example, Fig. 3) that each of temperature control element comprises:
a heating element (106, 108/110) configured to increase temperature of a corresponding portion of the wafer (102);
an active cooling element (112, 114/116) configured to decrease temperature of the corresponding portion of the wafer (102), the active cooling element (112, 114/116) distinct from and structurally different from the heating element (106, 108/110).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Mailho by Moslehi because having the heater block and the cooler block divided into different zones would help better control radial temperature gradient of the substrate.
Mailho as modified above further fails to explicitly teach a processor to determine a critical dimension (CD) map of a wafer having an average thickness after a plasma-enhanced etching process or a plasma-enhanced polishing process, wherein the CD map includes different portions of the wafer and respective different deviations from the average thickness for the different portions, respectively.
Andrew teaches a critical dimension (CD) map of a wafer having an average thickness after a plasma-enhanced etching or polishing process
teaching measuring a quantity, e.g., thickness, at multiple locations on a top surface of a wafer after process operations including etching and polishing (see also col. 1, lines 25–55),
disclosing that semiconductor wafers undergo numerous processes including etching and polishing, and the wafer is examined to confirm the previous process was completed with an acceptable level of nonuniformities, wherein the CD map includes different portions of the wafer and respective different deviations from the average thickness for the different portions, respectively (See, Col. 2 lines 22-65),
teaching measuring a thickness at each one of the multiple locations on the wafer, converting the measured thickness at each location to a corresponding mass density value, determining an average mass density value for the wafer, and determining a standard deviation i.e., respective deviations from the average for the wafer, teaching that the 3-sigma uniformity metric quantifies a standard deviation of measurements, such as the deviations in thickness of the wafer detected by an array of measurement points across the wafer, e.g., using a 49-point array wherein each point represents approximately 1/49th of the area of the wafer i.e., different portions of the wafer, and each point has a respective measured deviation from the average thickness, describing various nonuniformity patterns across the wafer surface including center-fast, edge-fast, and asymmetric patterns corresponding to different portions exhibiting different deviations) (See also Col. 4, lines 13–32, and Col. 5, lines 1–40)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the process chamber of Mailho as modified by Komatsu and Moselehi to further include a critical dimension (CD) map of the wafer having an average thickness after a plasma-enhanced etching or polishing process, the CD map including different portions of the wafer and respective different deviations from the average thickness for the different portions because such a modification would predictably improve the process control capability of the chamber of Mailho as modified by enabling spatially-resolved feedback for compensating thickness non-uniformities introduced by etching or polishing processes, thereby improving device yield.
In regards to claims 2, 4, 13 and 15, Mailho discloses all limitations of claim 1 except that the different portions corresponding to the temperature control elements have a same size; and
at least one of the different portions corresponding to the temperature control elements has a shape different from an annulus.
Notwithstanding, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these relative dimensions because applicant has not disclosed that the relative dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another relative dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
As for the shapes for the temperature control elements, it has been held that a configuration of the claimed temperature control elements was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed temperature control elements was significant. See, In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966)
In regards to claims 3 and 14, Mailho discloses (See, for example, Fig. 2A) wherein the different portions corresponding to the temperature control elements are evenly distributed on the wafer.
In regards to claims 6, 7., and 16, Mailho discloses all limitations of claim 1 except that the design of the temperature control elements based on the CD map of the wafer; the temperature of the at least one portion is adjusted to minimize a non-uniformity in the CD map of the wafer; and wherein the non-uniformity in the CD map is minimized by minimizing at least a chemical reaction rate variation among the different portions of the wafer,
However, it is the general concept of Mailho’s invention to have a uniform temperature on all different zones of the wafer and maintaining the temperature uniformly during heating and cooling with increased accuracy and precision (the at least one portion of the wafer is determined based on a critical dimension (CD) map of the wafer …having uniform processing temperatures on all zones of the wafer and maintaining it during the duration of the processing time would help achieve the desired CD requirement(s) as reaction rates (deposition rates) directly depends on it). Furthermore, Mailho describes controlling each zones independently and, both deviations of the wafer temperature from the processing temperature and temperature gradients across the surface of the wafer may be quickly corrected (See, for example, Abstract), wherein the CD map represents CD performance of the wafer in at least one of the following plasma enhanced processes: etching, deposition, and polishing (See, for example, Col. 1 lines 5-10).
In regards to claim 8, Mailho discloses (See, for example, Figs. 1-4) wherein a group of temperature control elements, among the plurality of temperature control elements, corresponds to a group of portions of the wafer and is configured to adjust temperature of the group of portions together for controlling temperature uniformity of the wafer ( “In FIG. 4, each of temperature sensors 28 is connected to an input terminal of control circuit 30 to provide information indicative of the temperature of associated portion of susceptor 14 and chamber top 12, which is then used by control circuit 30 to determine temperature fluctuations across susceptor 14 and chamber top 12. Control circuit 30 then adjusts control signals CSP.sub.n and CS.sub.1 -CS.sub.6 accordingly to provide a uniform heating and cooling rate and to maintain a precise and uniform temperature across susceptor 14 and chamber top 12. Each sensor 28 has an associated independent control loop to compensate for temperature variations. Each independent control loop adjusts for temperature variations within its associated zone, independent of measurements from the other zones.”., See, for example, Col. 7 lines 44-57).
In regards to claims 9 and 17, Mailho discloses (See, for example, Figs. 1-4) a platform holding the plurality of temperature control elements (See, for example, temperature control elements 18 in Fig. 1), wherein the platform is above the wafer (16) during the temperature uniformity control.
In regards to claims 10 and 18, Mailho discloses (See, for example, figs. 1-4) further comprising a platform holding the plurality of temperature control elements (See, for example, temperature control elements 20 in Fig. 1), wherein the platform is under the wafer during the temperature uniformity control.
In regards to claim 11, Mailho discloses (See, for example, Figs. 1-4) the heating elements fo reach of the temperature control elements is an electromagnetic coil comprises: a heating element (“…induction coils…to heat … a semiconductor wafer…”, See, for example, Col. 2 line 66 thru Col. 3 line 4).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Mailho in view of Komatsu, Shimizu, Moslehi, and Andrew as applied to claim 12 above, and further in view of Atlas (US 2014/0131005 A1, hereinafter “Atlas”).
In regards to claim 21, Mailho as modified above teaches all limitations of claim 12 but the heating elements and active cooling elements are arranged according to a first set of parallel lines and a second set of parallel lines that traverse the first set of parallel lines when viewed from a top view of the wafer, such that the plurality heating elements and active cooling elements, respectively, are located at respective intersections of the first set of parallel lines and the second set of parallel lines.
Atlas while disclosing a temperature control system teaches (See, for example, annotated Fig. 3 included below) the heating elements and active cooling elements are arranged according to a first set of parallel lines and a second set of parallel lines that traverse the first set of parallel lines when viewed from a top view of the wafer, such that the plurality heating elements and active cooling elements, respectively, are located at respective intersections of the first set of parallel lines and the second set of parallel lines (the specific heating and active cooling elements are the same elements—they are p-type and n-type semiconductor elements 109. The are for selectively providing heating or cooling to the target. Therefore, these structures are arranged in a vertical (…V1, V2…) and horizontal (…H1, H2…) and at the intersection of these lines there are these specific heating and active cooling elements).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to further modify Mailho by Atlas because the thermoelectric elements capable of both heating and cooling provide precise and rapid fine temperature control of the wafer surface.
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Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Mailho in view of Komatsu, Moslehi, and Andrew.
In regards to claim 19, Mailho discloses (See, for example, Figs. 1-4) a method for controlling wafer uniformity, comprising:
corresponding a plurality of heating elements and active cooling elements to a different portion of a wafer respectively (“…independently controlled heating zones within …induction coils along with a feedback control system to heat and cool a semiconductor wafer at a substantially uniform rate and to maintain the wafer at a substantially constant and uniform temperature.”, see, for example, Col. 2 line 66 thru col. 3 line 4),
wherein each of the heating elements is an electromagnetic coil (“…induction coils…to heat … a semiconductor wafer…”, See, for example, Col. 2 line 66 thru Col. 3 line 4); and
configuring each of the heating elements and active cooling elements to individually control temperature of a corresponding portion of the wafer (“…induction coils…to heat and cool a semiconductor wafer…”, See, for example, Col. 2 line 66 thru Col. 3 line 4);
detecting temperature of each portion of the wafer (“Each sensor 28 measures the temperature between a section of coil 18 or 20 associated with a particular zone, so that six sensors 28 are needed for temperature measurements of the three zones of chamber top 12 and the three zones of susceptor 14.”, See, for example, Col. 7 lines 36-40) ;
determining, based on the detecting, at least one portion of the wafer for temperature uniformity control of the wafer (“…each of temperature sensors 28 is connected to an input terminal of control circuit 30 to provide information indicative of the temperature of associated portion of susceptor 14 and chamber top 12, which is then used by control circuit 30 to determine temperature fluctuations across susceptor 14 and chamber top 12.”, see, for example, Col. 7 lines 44-51);
selecting at least one heating element or active cooling element, among the plurality of heating elements and active cooling elements, corresponding to the at least one portion; and adjusting temperature of the at least one portion for controlling temperature uniformity of the wafer ( “…Control circuit 30 then adjusts control signals CSP.sub.n and CS.sub.1 -CS.sub.6 accordingly to provide a uniform heating and cooling rate and to maintain a precise and uniform temperature across susceptor 14 and chamber top 12. Each sensor 28 has an associated independent control loop to compensate for temperature variations. Each independent control loop adjusts for temperature variations within its associated zone, independent of measurements from the other zones.”, See, for example, Col. 7 line 49 thru Col. 8 line 29).
Mailho is silent about the temperature of the at least one portion is adjusted in response to a temperature map of the wafer, wherein the temperature map is determined based on a plurality of plasma processing conditions, wherein the plurality of plasm processing conditions is determined by a multiple-parameter optimization process.
Komatsu while disclosing a plasma process teaches (See, for example, Figs. 1, 3) the temperature of the at least one portion is adjusted in response to a temperature map of the wafer, wherein the temperature map is determined based on a plurality of plasma processing conditions, wherein the plurality of plasm processing conditions is determined by a multiple-parameter optimization process (The resistance heater group 88 is connected to a power supply line L (L1 to L6). The power supply line L is drawn out of the processing vessel 32 through the cylindrical support column 64. Each power supply line L is connected to a heater control unit 92 having a heater power supply and a computer, and controls the temperature of the wafer W by controlling the power supplied to the resistance heater group 88. In order to control the temperature, a thermocouple (not shown) is provided …
In the illustrated example, it is divided into two concentric (annular) zones, a circular inner peripheral zone 94 at the center of the mounting table main body 62 and a ring-shaped outer peripheral zone 96 surrounding the inner peripheral zone 94. In the illustrated example, since the outer peripheral zone 96 is located on the outermost periphery, it becomes the outermost peripheral zone.
…
while the plasma processing such as the film forming process is performed on the wafer W, the heater control unit 92 transfers the resistance heating heaters 98 and 100 in the zones 94 and 96 to each other by feedback control. Individually controlled power is supplied. …. Electric power is supplied to the resistance heater 98 in the inner peripheral zone 94 through the feed lines L5 and L6 by feedback control, and the temperature control of the inner peripheral zone 94 is performed as a whole.
On the other hand, the outermost peripheral resistance heater 100 which is a resistance heater in the outermost peripheral zone (outer peripheral zone) 96 is divided into four heater sections 100A to 100D in the circumferential direction, and the four outermost peripheral power supply lines L1 to By individually changing the electrical state (potential etc.) of L4, the power supply mode to the heater sections 100A to 100D can be changed.
…
For example, in the case where the temperature of the wafer peripheral portion corresponding to the location where the gate valve 44 and the observation window 47 facing the gate valve 44 are provided on the side wall of the processing vessel 32 tends to decrease. When the heater sections corresponding to the window 47 are, for example, the heater sections 100A and 100C, respectively, the power input to these heater sections 100A and 100C is made larger than the power input to the other heater sections 100B and 100D. For example, the temperature compensation is performed for the portion where the temperature tends to decrease by increasing the time during which the current flows in the pattern as shown in the aspect 3. See, for example, pages 4, 7, and 9)
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Mailho by Komatsu because this would help individually control the electrical states of the outer peripheral feed lines by heater control unit such that temperature distribution at the periphery of the semiconductor wafer is simply controlled.
Mailho fails to explicitly teach that each of the active cooling elements is a liquid-based, gaseous based, or cryogenic cooling element; and
the heating elements and the active cooling elements are arranged according to a first set of parallel lines and a second set of parallel lines that traverse the first set of parallel lines when viewed from a top view of the wafer, such that the plurality of heating elements and active cooling elements, respectively, are located at a respective intersection of the first set of parallel lines and the second set of parallel lines.
Moslehi discloses (See, for example, Fig. 3) each of the active cooling elements is a liquid-based, gaseous based, or cryogenic cooling element (See, for example, Col. 2 lines 47-60); and
the heating elements (106, 108/110) and the active cooling elements (112, 114/116) are arranged according to a first set of parallel lines and a second set of parallel lines that traverse the first set of parallel lines when viewed from a top view of the wafer (102), such that the plurality of heating elements (106, 108/110) and active cooling elements (112, 114/116), respectively, are located at a respective intersection of the first set of parallel lines and the second set of parallel lines.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Mailho by Moslehi because having the heater block and the cooler block divided into different zones would help better control radial temperature gradient of the substrate.
Mailho as modified above further fails to explicitly teach determining a critical dimension (CD) map for a wafer having an average thickness after a plasma-enhanced etching process or a plasma-enhanced polishing process, wherein the CD map specifies different portions of the wafer and respective different deviations from the average thickness for the different portions, respectively.
Andrew teaches a critical dimension (CD) map of a wafer having an average thickness after a plasma-enhanced etching or polishing process
teaching measuring a quantity, e.g., thickness, at multiple locations on a top surface of a wafer after process operations including etching and polishing (see also col. 1, lines 25–55),
disclosing that semiconductor wafers undergo numerous processes including etching and polishing, and the wafer is examined to confirm the previous process was completed with an acceptable level of nonuniformities, wherein the CD map includes different portions of the wafer and respective different deviations from the average thickness for the different portions, respectively (See, Col. 2 lines 22-65),
teaching measuring a thickness at each one of the multiple locations on the wafer, converting the measured thickness at each location to a corresponding mass density value, determining an average mass density value for the wafer, and determining a standard deviation i.e., respective deviations from the average for the wafer, teaching that the 3-sigma uniformity metric quantifies a standard deviation of measurements, such as the deviations in thickness of the wafer detected by an array of measurement points across the wafer, e.g., using a 49-point array wherein each point represents approximately 1/49th of the area of the wafer i.e., different portions of the wafer, and each point has a respective measured deviation from the average thickness, describing various nonuniformity patterns across the wafer surface including center-fast, edge-fast, and asymmetric patterns corresponding to different portions exhibiting different deviations) (See also Col. 4, lines 13–32, and Col. 5, lines 1–40)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the process chamber of Mailho as modified by Komatsu and Moselehi to further include a critical dimension (CD) map of the wafer having an average thickness after a plasma-enhanced etching or polishing process, the CD map including different portions of the wafer and respective different deviations from the average thickness for the different portions because such a modification would predictably improve the process control capability of the chamber of Mailho as modified by enabling spatially-resolved feedback for compensating thickness non-uniformities introduced by etching or polishing processes, thereby improving device yield.
In regards to claim 20, Mailho discloses adjusting temperature of the at least one portion comprises at least one of the following during a CVD process of the wafer: increasing the temperature of the at least one portion; decreasing the temperature of the at least one portion; or detecting the temperature of the at least one portion (See, for example, Col. 7 line 31 thru Col. 8 line 64).
However, Mailho fails to explicitly teach that the process is plasma enhanced process.
However, it is readily known in the manufacturing of semiconductor devices to employ plasma enhanced process because this would help produce better conformity.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to employ plasma enhanced process over the CVD because this would help produce better conformity.
Response to Arguments
Applicant’s arguments with respect to claims 1, 12 and 19 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERMIAS T WOLDEGEORGIS whose telephone number is (571)270-5350. The examiner can normally be reached on Monday-Friday 8 am - 5 pm E.S.T..
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/ERMIAS T WOLDEGEORGIS/Primary Examiner, Art Unit 2893