DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/22/2025 has been entered.
Drawings
In view of Applicant’s amendments, the prior drawing objection is partially withdrawn, but claimed features remain that are not shown in the drawings.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “conductive vias are in physical contact with the exposed top surfaces of the exposed top surfaces of the topmost metal features and exposed sidewalls of the topmost seed layers of the first conductive structure” as found in claim 1 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
(Re Claim 1) “the exposed top surfaces of the topmost metal features and the exposed sidewalls of the topmost seed layers of the first conductive structure” lack antecedent basis.
Claims 2-8 inherit this rejection for lack of antecedence.
(Re Claim 2) The number of first metal features and second polymer layers is unclear. Claim 2 introduces “a first metal feature” and then recites “the first glass carrier is in direct contact with a first metal feature underlying the first metal feature”. Similarly, claim 2 describes a first metal feature “embedded in the second polymer layer”, but then recites “a second portion connected with the first portion and embedded in a second polymer layer”.
Additionally, it is unclear how the first metal feature or the second polymer layer can underly themselves. Claim 2 recites “embedded in a second polymer layer underlying the second polymer layer…direct contact with a first metal feature underlying the first metal feature…is entirely embedded in the second polymer layer underlying the second polymer layer”. This arrangement is neither shown nor described in the specification and drawings.
During examination, reference to a “second polymer layer” was understood to mean only the one second polymer layer introduced in claim 1, and that limitations requiring features to underly themselves are interpreted as requiring only that the features exist.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-3, and 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over Sawadaishi (US 2021/0118698), Palanduz (US 2006/0043567), Takahashi et al. (US 2015/0313020), Nakagawa et al. (US 20070194412), Morganelli (US 2015/0072478), Ludden et al. (US 5,637,925), Jang et al. (US 2008/0284041), Wu et al. (US 2016/0056087), and Inagaki et al. (US 2016/0064318), all of record, and Hirose et al. (US 2001/0042637) and Tsunetomo et al. (US 2017/0229318), both newly cited.
(Re Claim 1) Sawadaishi teaches a method of forming a semiconductor structure, comprising:
providing a first glass carrier, wherein the first glass carrier has a first side and a second side opposite to the first side (A first glass carrier 10 is provided with a first side 10a and a second side 10b opposite to the first side; Fig. 2(a), para. [0059]-[0060]);
forming a first conductive structure on the first side of the first glass carrier (First conductive structure 14 is formed on the first side 10a of the first glass carrier 10; Fig. 2(c), para. [0055]),
wherein the first conductive structure comprises first metal features (First conductive structure comprises first metal features; Fig. 2(b), para. [0053]) electrically connected to each other and embedded in first polymer layers (First metal via is formed, electrically connected to each other, and embedded in first polymer layers 12, 13; Fig. 2(c), para. [0055]);
bonding a second glass carrier to the first conductive structure (Second glass carrier 30 is bonded to the first conductive structure 14; Fig. 2(d), para. [0057]);
after bonding the second glass carrier to the first conductive structure, performing a patterning process (¶61) to the second side of the first glass carrier to directly form through holes from the second side of the first glass carrier (40; Fig. 2(f)) and penetrating the first glass carrier (Fig. 2(f), ¶61);
forming a copper seed layer in direct contact with the second side of the first glass carrier and covering sidewalls and bottoms of the through holes (the copper seed layer is formed on the second surface, and conformal deposition of the seed layer results in covering the sidewalls and bottom of the through holes; Fig. 2(g), ¶65);
forming a conductive layer in the through holes and on the copper seed layer (¶65);
forming conductive vias in the through holes penetrating through the first glass carrier, wherein each conductive via, the copper seed layer surrounds a sidewall and a bottom of the conductive layer, and top and bottom surfaces of each conductive via are flushed with the first and second sides of the first glass carrier (Conductive vias are formed within through holes 40, penetrating the first glass carrier 10; each conductive via comprises a conductive pattern and a copper seed layer surrounding a sidewall and a bottom of the conductive pattern, and top and bottom surfaces of each conductive via are flushed with the first and second sides of the first glass carrier 10; Fig. 2(g), para. [0065]); and
forming a second conductive structure on the second side of the first glass carrier, the second conductive structure electrically connected to the conductive vias (Second conductive structure 15 is formed on the second side 10b of the first glass carrier 10 opposite to the first side 10a, and the second conductive structure 15 is electrically connected to the conductive vias; Fig. 2(g), para. [0066]).
Sawadaishi does not explicitly teach a method wherein for the first conductive structure a coefficient of thermal expansion (CTE) of a first polymer layer facing away from the first glass carrier is higher than a coefficient of thermal expansion (CTE) of a first polymer layer facing the first glass carrier;
removing portions of the copper seed layer and the conductive layer outside of the through holes to form conductive vias in the through holes penetrating through the first glass carrier, wherein the conductive vias are in physical contact with the exposed top surfaces of the topmost metal features and the exposed sidewalls of the topmost seed layers of the first conductive structure; and
forming a second conductive structure on the second side of the first glass carrier, wherein the second conductive structure comprises second metal features electrically connected to each other and embedded in second polymer layers, and a coefficient of thermal expansion (CTE) of a second polymer layer facing away from the first glass carrier is higher than a coefficient of thermal expansion (CTE) of a second polymer layer facing the first glass carrier.
Takahashi teaches forming through holes (145; Fig. 8, ¶78) penetrating through a first glass carrier (110; Fig. 8, ¶78) with a first conductive structure (125; Fig. 8, ¶82) formed on a first side (top; Fig. 8) of the first glass carrier by a laser drilling process (¶77).
A PHOSITA would find it obvious to use a laser drilling process to form the through holes 40 of Sawadaishi, as taught by Takahashi, instead of the chemical etch (Sawadaishi: Fig. 2(f), ¶61) to form through holes with higher density, as laser drilling allows one to form through holes with a closer pitch (Ludden: Col. 5 Ln. 38-46) as compared to chemical etching, allowing for denser patterning. Furthermore, maintaining the original, greater thickness reduces the influence of vibration and flexure on the first glass carrier during processing steps (Takahashi: ¶8).
Wu teaches forming a first (104; Fig. 1) and second (102; Fig. 1, ¶14) conductive structure respectively on a first (bottom) and second (top) side of a first carrier, each conductive structure respectively comprises first and second metal features (112; Fig. 1) electrically connected to each other and embedded in a first and second polymer layer (dielectric layers formed from e.g., polyimide; ¶14).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form each metal feature of the first and second conductive structure according to Wu, as electroplating (e.g., Nakagawa: ¶95) using seed layers is a simple, inexpensive process capable of meeting performance requirements including low temperature operation, high deposition rates, and good step coverage.
Inagaki teaches conductive structures (55F and 55S; Fig. 9) using multiple polymer layers each (Fig. 9).
A PHOSITA would understand that forming multiple polymer layers having metal features is a repeatable processs (Wu: ¶14) that allows for the device interconnects to be fanned out according to design constraints. See also Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004).
Palanduz teaches forming layers of an interposer such that the CTE of each material used to form each respective layer increases the further each respective layer is from one side (Interposer 10 with layers 12, 14, and 16; Fig. 1, ¶22).
Nakagawa teaches adding filler to a polymer layer to reduce the CTE (¶¶70-71).
Morganelli teaches an amount of polymer filler material mixed into a polymer layer, so as to lower the CTE of the layer overall, can be as low as 0 wt %, i.e., filler-free (¶21).
A person having ordinary skill in the art before the effective filing date of the claimed invention would know to add filler as taught by Nakagawa to the first and second polymer layers such that the layers are formed with increasing CTE, as the fill amount may be a range (Morganelli: ¶21), to form the first and second polymer layers of Sawadaishi, in order to reduce stress within the semiconductor structure of Sawadaishi (Palanduz: ¶22), resulting in a CTE of a first polymer layer facing away from the first glass carrier 10 of Sawadaishi being higher than a CTE of a first polymer layer facing the first glass carrier 10, and likewise for a second polymer layer facing away from the first glass carrier 10 and a second polymer layer facing the first glass carrier 10.
Jang teaches forming a through hole (150; Fig. 7) further extending into a first conductive structure (115+120+127; Fig. 7). Jang also teaches that an alternative to forming the through hole such that it makes contact but does not penetrate through metal feature 120, is to form the through hole 150 such that a portion of the metal feature is penetrated (¶35).
Takahashi teaches that the depth of the laser drilling can be controlled by determining a relationship between the irradiation time and the processing depth (¶84), and that the laser can be used to such that it does not pass through the topmost metal feature 120 (Fig. 8, ¶85).
As the irradiation time is a result-effective variable of processing depth, and therefore how far the through holes extend into the first conductive structure, a PHOSITA would find it obvious to form the through holes extending into the first conductive structure, such that the through holes expose top surfaces of topmost metal features and sidewalls of topmost seed layers of the first conductive structure, as this is a result of irradiating for a time that is long enough to ablate a topmost seed layer (Wu: ¶14) but short enough not to pass completely through (Jang: ¶35). As the topmost metal feature is conductive (Wu: ¶14), this allows for an electrical connection to be formed. The claimed surface and sidewall exposure would have been obvious to optimize and ascertainable through routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). See also Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004).
As the conductive vias are formed conformally (Sawadaishi: ¶65) to the through holes, and the through holes expose the top (from the orientation where the top is the bottom of Fig. 2(g)) surfaces of the topmost metal features and the exposed sidewalls of the topmost seed layers (due to the through holes formed through the seed layers) of the first conductive structure, the conductive vias are formed in physical contact with the exposed top surfaces of the topmost metal features and the exposed sidewalls of the topmost seed layers of the first conductive structure.
Modified Sawadaishi has yet to be shown to teach the method comprising removing portions of the copper seed layer and the conductive layer outside of the through holes to form the conductive vias in the through holes.
Hirose teaches that plating using a seed layer (22+52; Fig. 4(M)-4(P)) may be part of a a plating operation that etches through a conductive layer (56; Fig. 4(M)-4(P)) and the seed layer using a mask formed on top of the plated stack after plating. Alternatively, the mask may be formed before plating the conductive layer (Fig. 5(M)’-5(P)’, ¶¶324-329).
Tsunetomo teaches that plating using a seed layer (12; Fig. 5(a)) may be part of a plating operation that etches through a conductive layer (part of material that forms 30 that is outside of a through hole 11; Fig. 5(b) and then 5(e)) and the seed layer using a photolithography process (¶163). Alternatively, portions of the conductive layer and the seed layer that are outside of the through hole may be removed through a backside grinding step (¶162) to form conductive vias (30; Fig. 5(d)), followed by subsequent formation of metal features (40a; Fig. 5(d), ¶162).
A PHOSITA would find it obvious to utilize the removal technique of Hirose where a mask is applied after plating using the seed layer (Hirose: Fig. 4(M)-4(P)) to remove the conductive layer and the seed layer on the second side of the first glass carrier, for forming the conductive vias of modified Sawadaishi, as removal of the conductive layer and the seed layer after plating is an art recognized alternative to forming a mask before plating using the seed layer in order to control where material in a plating operation is ultimately retained (Hirose: ¶¶324-329; Sawadaishi: “Next, the dry film resist no longer needed is dissolved away to form a through electrode. Then, the seed layer no longer needed is removed, and the surface is coated with an outer layer protective film such as an insulating resin or a solder resist layer. If any external connection terminal is required, an opening may be formed.”; Fig. 2(g), ¶65). See In re Fout, 675 F.2d 297, 213 USPQ 532 (CCPA 1982).
Furthermore, a PHOSITA would find it obvious to utilize the plating operation of Tsunetomo, where a grinding operation is performed to remove the parts of a seed layer and a conductive layer outside of a through hole to form conductive vias (Tsunetomo: Fig. 5(c)), with a subsequent formation of metal features (Tsunetomo: Fig. 5(d)), as this is an art recognized alternative method to control where plated material is retained in a plating operation (Tsunetomo: Fig. 5(c) and 5(e), ¶¶161-163). See In re Fout, 675 F.2d 297, 213 USPQ 532 (CCPA 1982).
This results in modified Sawadaishi teaching removing portions of the copper seed layer (Sawadaishi: Fig. 2(d), ¶65) and the conductive layer (Fig. 2(d), the conductive material plated in the through holes; ¶65) outside of the through holes (in the manner taught by Tsunetomo’s Fig. 5(a-d)) to form conductive vias in the through holes penetrating through the first glass carrier (Sawadaishi: conductive vias are formed within through holes 40, penetrating the first glass carrier 10; ¶65).
(Re Claim 2) Modified Sawadaishi teaches the method of claim 1, wherein a first metal feature (the element 112 from Wu contacting the conductive via of modified Sawadaishi; Wu: Fig. 1) facing away from the first glass carrier has a first portion (top portion) embedded in the second polymer layer (from Wu and Inagaki, the second polymer layer of e.g., polyimide closest to the conductive vias of modified Sawadaishi; Wu: ¶14) facing away from the first glass carrier and a second portion (bottom portion) connected with the first portion and embedded in a second polymer layer underlying the second polymer layer facing away from the first glass carrier (Wu: Fig. 1), the first metal feature facing away from the first glass carrier is in direct contact with a first metal feature underlying the first metal feature facing away from the first glass carrier (Wu: Fig. 1), and the first metal feature underlying the first metal feature facing away from the first glass carrier is entirely embedded in the second polymer layer underlying the second polymer layer facing away from the first glass carrier (Wu: Fig. 1).
(Re Claim 3) Modified Sawadaishi teaches the method of claim 1, further comprising removing the second glass carrier from the first conductive structure (Removal of the second glass carrier 30 from the first conductive structure 14; Fig. 2(h), para. [0068]).
(Re Claim 5) Modified Sawadaishi teaches the method of claim 1, wherein forming the first conductive structure comprises:
forming a first copper seed material layer on the first side of the first glass carrier (Wu: ¶14);
forming a first metal line by using the first copper seed line as a seed (First metal line is formed by using the first copper seed layer as a seed; Fig. 2(b), para. [0053]; Wu: ¶14);
forming a first metal via by using the first metal line as a seed (First metal via is formed by using the first metal line as a seed; Fig. 2(c), para. [0055]).
(Re Claim 6) Modified Sawadaishi teaches the method of claim 1, but does not explicitly teach the method wherein the forming the second conductive structure comprises: forming second lines completely covering the through vias, respectively.
Wu teaches forming second vias (the thicker portions of 112; Fig. 1) and second lines (the thinner portions of 112; Fig. 1), wherein the second lines are formed completely covering through vias (120; Fig. 1).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to from the second lines of modified Sawadaishi such that they completely cover the through vias (Sawadaishi: Fig. 2(g), ¶65), as a consequence of forming individual electrical connections to each through via, as taught by Wu, using electroplating. See Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004).
(Re Claim 7) Modified Sawadaishi teaches the method of claim 1, wherein in the first conductive structure, a first polymer layer facing away from the first glass carrier is formed softer than a first polymer layer facing the first glass carrier (to achieve a smaller CTE value, more fill that is harder than the polymer material is added to the first polymer layer facing the first glass carrier, than the first polymer layer facing away from the first glass carrier; Nakagawa: ¶¶70-71; Palanduz: ¶22).
However, modified Sawadaishi does not explicitly teach the method wherein the outermost polymer layer is a filler-free polymer layer.
Morganelli teaches an amount of polymer filler material mixed into a polymer layer, so as to lower the CTE of the layer overall, can be as low as 0 wt %, i.e., filler-free (¶21).
Following from the discussion of the CTE gradient of claim 1 around Palanduz and Nakagawa, a PHOSITA would find it obvious to use a filler-free polymer layer for the outmost polymer layer, as a filler-free polymer layer will be formed softer than any same polymer layer filled with glass (glass filler being taught by Palanduz ¶59 and Morganelli ¶21), at some percentage, while having a higher CTE value, and so modified Sawadaishi teaches claim 7.
(Re Claim 8) Modified Sawadaishi teaches the method of claim 1, wherein the second conductive structure comprises second metal features electrically connected to each other and embedded in second polymer layers (Wu: ¶14), and a second polymer layer facing away from the first glass carrier is formed softer than a second polymer layer facing the first glass carrier (to achieve a smaller CTE value, more fill that is harder than the polymer material is added to the second polymer layer facing the first glass carrier, than the second polymer layer facing away from the first glass carrier; Nakagawa: ¶¶70-71; Palanduz: ¶22).
Liou et al. teaches dielectric layering in an ILD structure, where each layer is a different hardness, according to the interconnect pitch size in each layer, with larger pitch sizes corresponding with a softer layer, as larger pitch size interconnects require less support (The hardness of the second dielectric 118 may be smaller than the hardness of the first dielectric 110; Fig. 2F, [0027], [0030]).
Additionally, Liou et al. states that the dielectric may be an organic polymer ([0025]).
A person having ordinary skill in the art before the effective filing date of the claimed invention would recognize the deposition of a softer polymer layer facing away from the first glass carrier, when compared to the hardness of a polymer layer facing the glass carrier, as applicable to the dielectric layers of the instant invention, and then do so because stacking polymer layers of varying hardness in inverse proportion to interconnect pitch size allow for said interconnects to be mechanically supported by softer dielectrics, which have lower k-values, resulting in lower RC delay, and higher breakdown resistance.
Therefore, a person having ordinary skill in the art before the effective filing date of the claimed invention would deposit a softer polymer layer facing away from the first glass carrier of Sawadaishi, when compared to the hardness of a polymer layer facing the glass carrier.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Sawadaishi (US 2021/0118698), Palanduz (US 2006/0043567), Takahashi et al. (US 2015/0313020), Nakagawa et al. (US 20070194412), Morganelli (US 2015/0072478), Ludden et al. (US 5,637,925), Jang et al. (US 2008/0284041), Wu et al. (US 2016/0056087), and Inagaki et al. (US 2016/0064318), all of record, and Hirose et al. (US 2001/0042637) and Tsunetomo et al. (US 2017/0229318), both newly cited as applied to claim 1 above, and further in view of Koizumu et al. (US 2014/0015121), and Fujishima et al. (US 2020/0343184), both of record.
(Re Claim 4) Sawadaishi teaches the method of claim 3, further comprising:forming first bumps on the first conductive structure (Formation of first bumps on top of the first conductive structure, corresponding to layer 14; Fig. 6); andforming second bumps on the second conductive structure (Formation of second bumps on the bottom of the second conductive structure, corresponding to layer 15; Fig. 6, whereina dimension of the first bumps is different from a dimension of the second bumps (Formation of second bumps on the second conductive structure 15, where the second bumps have a different dimension than the first bumps; Fig. 6).
However, Sawadaishi does not explicitly teach the method wherein after forming the first bumps, forming second bumps on the second conductive structure, and wherein a dimension of the first bumps is less than a dimension of the second bumps.
Koizumi teaches an interposer (10; Fig. 1B) having bumps (22 and 24) sized according to the contact pads of devices (such as 28) which are intended to be connected to the interposer. Here the bumps have different dimension.
A person having ordinary skill in the art before the effective filing date of the claimed invention would know that the metal features, vias, and bumps of the method of Sawadaishi can be readily changed to accommodate intended connection sizes, according to product requirements (Fujishima: ¶¶43, 54). As the resulting bump dimensional relationships is either such that a dimension of the first bump is less than a dimension of the second bumps, or vice versa, one of ordinary skill in the art would have had a reasonable expectation of success by selecting from this finite list of options, and thus it would have been obvious to try making a dimension of the first bumps less than a dimension of the second bumps, because there are a finite number of identified, predictable solutions. The Supreme Court decided that a claim can be proved obvious merely by showing that the combination of known elements was obvious to try. Therefore, choosing from a finite number of identified, predictable solutions, with a reasonable expectation for success, is likely to be obvious to a person of ordinary skill in the art. See KSR International Co. v. Teleflex Inc., 550 U.S. 398, 415-421, USPQ2d 1385, 1395 - 97 (2007) (see MPEP § 2143, E.).
Additionally, Koizumi teaches forming first bumps (56; Fig. 6B) on a first conductive structure, and then forming second bumps (58; Fig. 6C) on a second conductive structure after that.
A PHOSITA would find it obvious to form second bumps on the second conductive structure after forming first bumps on the first conductive structure of Sawadaishi, as taught by Koizumi, as either order of bump formation has a predictable result. See In re Burhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946).
Claims 9-14 are rejected under 35 U.S.C. 103 as being unpatentable over Sawadaishi (US 2021/0118698), Palanduz (US 2006/0043567), Takahashi et al. (US 2015/0313020), Nakagawa et al. (US 20070194412), Cheng et al. (US 2018/0308825), Chen et al. (US 2019/0131273), Morganelli (US 2015/0072478), Koizumu et al. (US 2014/0015121), and Ludden et al. (US 5,637,925), Wu et al. (US 2016/0056087), Inagaki et al. (US 2016/0064318), Fujishima et al. (US 2020/0343184), Kang et al. (US 2020/0144237), all of record, and Tsunetomo et al. (US 2017/0229318), both newly cited.
(Re Claim 9) Sawadaishi teaches a method of forming a semiconductor structure, comprising:
providing a glass substrate (10; Fig. 2(g), ¶¶51, 57, 61, and 66),) on a carrier (30; Fig. 2(g), ¶¶51, 57, 61, and 66), wherein the glass substrate comprises first (14; Fig. 2(g), ¶¶51, 57, 61, and 66), and second (15; Fig. 2(g), ¶¶51, 57, 61, and 66) conductive structures and a glass layer (Glass of the glass substrate; Fig. 2(g)) interposed therebetween, and wherein the glass layer has a first side (top side; Fig. 2(c)) and a second side (bottom side; Fig. 2(c)) opposite to the first side providing the glass substrate comprises:
forming the first conductive structure on the first side (top side; Fig. 2(c)) of the glass layer;
bonding a glass carrier (30; Fig. 2(d), ¶¶51, 57, 61, and 66) to the first conductive structure;
after bonding the glass carrier to the first conductive structure, performing a patterning process (¶¶65-66) to the second side of the glass layer to directly form through holes (40; Fig. 2(f)) from the second side of the glass layer and penetrating through the glass layer (Fig. 2(f));
forming a copper seed layer (¶65) in direct contact with the second side of the glass layer and covering sidewalls and bottoms of the through holes (the copper seed layer is formed through electroless process; Fig. 2(g), ¶¶65-66);
forming a conductive layer (the plated material that forms the conductive through electrodes within the through holes; ¶¶65-66) in the through holes and on the copper seed layer; and
forming conductive vias (Fig. 2(g), ¶¶51, 57, 61, and 66) in the through holes penetrating the glass layer; and
forming the second conductive structure on a second side of the glass layer opposite to the first side (Fig. 2(g)), the second conductive structure electrically connected to the conductive vias (¶¶51, 57, 61, and 66); and
removing the carrier from the first conductive structure of the glass substrate (Fig. 2(h));
However, Sawadaishi does not explicitly teach a method comprising:
forming the first conductive structure, wherein the first conductive structure comprises first metal features electrically connected to each other and embedded in first polymer layers, and filler particles of a first polymer layer facing away from the first glass layer is lower than filler particles of a first polymer layer facing the first glass layer;
mounting the glass substrate on a frame;
bonding a semiconductor package to the first conductive structure of the glass substrate;
after bonding the glass carrier to the first conductive structure, directly forming through holes penetrating through the glass layer;
removing portions of the copper seed layer and the conductive layer outside of the through holes to form the conductive vias in the through holes;
forming the second conductive structure, wherein the second conductive structure comprises second metal features electrically connected to each other and embedded in second polymer layers, and filler particles of a second polymer layer facing away from the first glass layer is lower than filler particles of a second polymer layer facing the first glass layer, and wherein a number of the second polymer layers is less than a number of the first polymer layers.
Cheng teaches attaching a substrate 250 to a frame 280 on the side of the substrate 250 opposite to the side where the carrier 110 was attached, such that a conductive structure 260 faces the frame 280 (Fig. 1H, 1I, para. [0016, 0041, 0055]).
A person having ordinary skill in the art before the effective filing date of the claimed invention would know that using the frame handling method as taught by Cheng, to the glass substrate 10 of Sawadaishi oriented so that the second conductive structure 15 of Sawadaishi faces the frame is a known method of handling substrates during processing, which provides additional support to the semiconductor structure.
Chen teaches bonding a semiconductor package 300/400 to a conductive structure 108 (Fig. 1F, para. [0028]).
As Sawadaishi states the semiconductor structure as taught thereby is an interposer (para. [0085]), a PHOSITA would know that the first conductive structure 14 of Sawadaishi is able to bond with the semiconductor package 300/400 of Chen, choosing to do so to add logical device functions.
Takahashi teaches forming through holes (145; Fig. 8, ¶78) penetrating through a first glass carrier (110; Fig. 8, ¶78) with a first conductive structure (125; Fig. 8, ¶82) formed on a first side (top; Fig. 8) of the first glass carrier by a laser drilling process (¶77).
A PHOSITA would find it obvious to use a laser drilling process to form the through holes 40 of Sawadaishi, as taught by Takahashi, instead of the chemical etch (Sawadaishi: Fig. 2(f), ¶61) to form through holes with higher density, as laser drilling allows one to form through holes with a closer pitch (Ludden: Col. 5 Ln. 38-46) as compared to chemical etching, allowing for denser patterning.
Furthermore, as the thickness the first glass carrier of Sawadaishi is reduced according to an etch (¶39) to form the through holes that is now replaced with a laser drilling process having no etching step, the through holes are now formed to penetrate through the first glass carrier of the original thickness. Maintaining the original, greater thickness reduces the influence of vibration and flexure on the first glass carrier during processing steps (Takahashi: ¶8).
Wu teaches forming a first (104; Fig. 1) and second (102; Fig. 1, ¶14) conductive structure respectively on a first (bottom) and second (top) side of a first carrier, each conductive structure respectively comprises first and second metal features (112; Fig. 1) electrically connected to each other and embedded in a first and second polymer layer (dielectric layers formed from e.g., polyimide; ¶14).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form each metal feature of the first and second conductive structure according to Wu, as electroplating (e.g., Nakagawa: ¶95) using seed layers is a simple, inexpensive process capable of meeting performance requirements including low temperature operation, high deposition rates, and good step coverage.
Inagaki teaches conductive structures (55F and 55S; Fig. 9) using multiple polymer layers each (Fig. 9).
A PHOSITA would understand that forming multiple polymer layers having metal features is a repeatable processs (Wu: ¶14) that allows for the device interconnects to be fanned out according to design constraints. See also Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004).
Palanduz teaches forming layers of an interposer such that the CTE of each material used to form each respective layer increases the further each respective layer is from one side (Interposer 10 with layers 12, 14, and 16; Fig. 1, ¶22).
Nakagawa teaches adding filler to a polymer layer to reduce the CTE (¶¶70-71).
Morganelli teaches an amount of polymer filler material mixed into a polymer layer, so as to lower the CTE of the layer overall, can be as low as 0 wt %, i.e., filler-free (¶21).
A person having ordinary skill in the art before the effective filing date of the claimed invention would know to add filler as taught by Nakagawa to the first and second polymer layers such that the layers are formed with increasing CTE, as the fill amount may be a range (Morganelli: ¶21), to form the first and second polymer layers of Sawadaishi, in order to reduce stress within the semiconductor structure of Sawadaishi (Palanduz: ¶22), resulting in a CTE of a first polymer layer facing away from the first glass carrier 10 of Sawadaishi being higher than a CTE of a first polymer layer facing the first glass carrier 10, and likewise for a second polymer layer facing away from the first glass carrier 10 and a second polymer layer facing the first glass carrier 10.
As less fill is used for polymer layers having greater CTE values, the filler particles of a first and second polymer layer facing away from the first glass layer will be lower than the filler particles of a first and second polymer layer facing the first glass layer.
Koizumi teaches an interposer (10; Fig. 1B) having bumps (22 and 24) sized according to the contact pads of devices (such as 28) which are intended to be connected to the interposer. Here the bumps have different dimension.
A person having ordinary skill in the art before the effective filing date of the claimed invention would know that the metal features, vias, and bumps of the method of Sawadaishi can be readily changed to accommodate intended connection sizes, according to product requirements (Fujishima: ¶¶43, 54). As the resulting bump dimensional relationships is either such that a dimension of the first bump is less than a dimension of the second bumps, or vice versa, one of ordinary skill in the art would have had a reasonable expectation of success by selecting from this finite list of options, and thus it would have been obvious to try making a dimension of the first bumps less than a dimension of the second bumps, thereby allowing for the first conductive structure to have a fine pitch connection, because there are a finite number of identified, predictable solutions. The Supreme Court decided that a claim can be proved obvious merely by showing that the combination of known elements was obvious to try. Therefore, choosing from a finite number of identified, predictable solutions, with a reasonable expectation for success, is likely to be obvious to a person of ordinary skill in the art. See KSR International Co. v. Teleflex Inc., 550 U.S. 398, 415-421, USPQ2d 1385, 1395 - 97 (2007) (see MPEP § 2143, E.).
Inagaki teaches forming conductive structures (55F and 55S; Fig. 9) on opposite sides of a insulating layer (20z; Fig. 9), where the conductive structure (55F; Fig. 9) having finer-pitch bumps has three polymer layers compared to two for the other conductive structure (55S; Fig. 9).
A PHOSITA would find it obvious to form the first conductive structure using a greater number of polymer layers than that of the second conductive structure, when forming the first conductive structure to have finer-pitch connections than those of the second conductive structure, as forming fine-pitch vias is more readily achieved using multiple layers of thin polymer layers (Kang: ¶91). And forming one conductive structure using fewer polymer layers results in fewer overall steps, saving device processing time.
Modified Sawadaishi has yet to be shown to teach the method comprising removing portions of the copper seed layer and the conductive layer outside of the through holes to form the conductive vias in the through holes.
Hirose teaches that plating using a seed layer (22+52; Fig. 4(M)-4(P)) may be part of a a plating operation that etches through a conductive layer (56; Fig. 4(M)-4(P)) and the seed layer using a mask formed on top of the plated stack after plating. Alternatively, the mask may be formed before plating the conductive layer (Fig. 5(M)’-5(P)’, ¶¶324-329).
Tsunetomo teaches that plating using a seed layer (12; Fig. 5(a)) may be part of a plating operation that etches through a conductive layer (part of material that forms 30 that is outside of a through hole 11; Fig. 5(b) and then 5(e)) and the seed layer using a photolithography process (¶163). Alternatively, portions of the conductive layer and the seed layer that are outside of the through hole may be removed through a backside grinding step (¶162) to form conductive vias (30; Fig. 5(d)), followed by subsequent formation of metal features (40a; Fig. 5(d), ¶162).
A PHOSITA would find it obvious to utilize the removal technique of Hirose where a mask is applied after plating using the seed layer (Hirose: Fig. 4(M)-4(P)) to remove the conductive layer and the seed layer on the second side of the first glass carrier, for forming the conductive vias of modified Sawadaishi, as removal of the conductive layer and the seed layer after plating is an art recognized alternative to forming a mask before plating using the seed layer in order to control where material in a plating operation is ultimately retained (Hirose: ¶¶324-329; Sawadaishi: “Next, the dry film resist no longer needed is dissolved away to form a through electrode. Then, the seed layer no longer needed is removed, and the surface is coated with an outer layer protective film such as an insulating resin or a solder resist layer. If any external connection terminal is required, an opening may be formed.”; Fig. 2(g), ¶65). See In re Fout, 675 F.2d 297, 213 USPQ 532 (CCPA 1982).
Furthermore, a PHOSITA would find it obvious to utilize the plating operation of Tsunetomo, where a grinding operation is performed to remove the parts of a seed layer and a conductive layer outside of a through hole to form conductive vias (Tsunetomo: Fig. 5(c)), with a subsequent formation of metal features (Tsunetomo: Fig. 5(d)), as this is an art recognized alternative method to control where plated material is retained in a plating operation (Tsunetomo: Fig. 5(c) and 5(e), ¶¶161-163). See In re Fout, 675 F.2d 297, 213 USPQ 532 (CCPA 1982).
This results in modified Sawadaishi teaching removing portions of the copper seed layer (Sawadaishi: Fig. 2(d), ¶65) and the conductive layer (Fig. 2(d), the conductive material plated in the through holes; ¶65) outside of the through holes (in the manner taught by Tsunetomo’s Fig. 5(a-d)) to form conductive vias in the through holes penetrating through the first glass carrier (Sawadaishi: conductive vias are formed within through holes 40, penetrating the first glass carrier 10; ¶65).
(Re Claim 10) Modified Sawadaishi teaches the method of claim 9, whereinthe conductive vias are formed by an electroplating process (Conductive vias in through holes 40 are formed by an electroplating process; para. [0065]).
(Re Claim 11) Modified Sawadaishi teaches the method of claim 9, wherein the first conductive structure is formed by an electroplating process (First conductive structure 14 is formed by an electroplating process; para. [0053, 0055]).
(Re Claim 12) Modified Sawadaishi teaches the method of claim 9, but does not explicitly teach the method wherein forming the second conductive structure comprises forming second lines completely covering the through vias, respectively.
Wu teaches forming second vias (the thicker portions of 112; Fig. 1) and second lines (the thinner portions of 112; Fig. 1), wherein the second lines are formed completely covering through vias (120; Fig. 1).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to from the second lines of modified Sawadaishi such that they completely cover the through vias (Sawadaishi: Fig. 2(g), ¶65), as a consequence of forming individual electrical connections to each through via, as taught by Wu, using electroplating. See Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004).
(Re Claim 13) Modified Sawadaishi teaches the method of claim 9, wherein a critical dimension of the first conductive structure is less than a critical dimension of the second conductive structure (as a result of forming the features of the first conductive structure with a finer pitch; Kang: ¶91).
(Re Claim 14) Modified Sawadaishi teaches the method of claim 9, further comprising:forming first bumps on the first conductive structure of the glass substrate, whereinthe semiconductor package is bonded to the first conductive structure of the glass substrate through the first bumps (Sawadaishi: First bumps are formed on the first conductive structure 14 of the glass substrate 10; Fig. 6; Modified Sawadaishi: Semiconductor package 300/400 of Chen is bonded to the first conductive structure, corresponding to layer 14 of Sawadaishi through the first bumps);removing the frame from the second conductive structure of the glass substrate (Modified Sawadaishi: Frame 280 of Cheng is removed from the second conductive structure of the substrate; Cheng: Fig. 1M, para. [0055]); and forming second bumps on the second conductive structure of the glass substrate (Sawadaishi: Second bumps are formed on the second conductive structure, corresponding to layer 15 of the glass substrate 10; Fig. 6).
Claims 21-25 are rejected under 35 U.S.C. 103 as being unpatentable over Sawadaishi (US 2021/0118698), Palanduz (US 2006/0043567), Takahashi et al. (US 2015/0313020), Nakagawa et al. (US 20070194412), Chen et al. (US 2019/0131273), Morganelli (US 2015/0072478), Koizumu et al. (US 2014/0015121), Ludden et al. (US 5,637,925), Wu et al. (US 2016/0056087), and Inagaki et al. (US 2016/0064318), all of record, and Tsunetomo et al. (US 2017/0229318), both newly cited.
(Re Claim 21) Sawadaishi teaches a method of forming a semiconductor structure, comprising:
providing a first glass carrier (10; Fig. 2(c), ¶57), wherein the first glass carrier has a first side (top side; Fig. 2(c)) and a second side (Fig. 2(c)) opposite to the first side;
forming a first conductive structure on the first side of the first glass carrier (First conductive structure 14 is formed on a first side 10a of a first glass carrier 10; Fig. 2(c), para. [0057]), wherein the first conductive structure comprises first metal features (First conductive structure comprises first metal features; Fig. 2(b), para. [0053]) electrically connected to each other and embedded in first polymer layers (First metal via is formed, electrically connected to each other, and embedded in first polymer layers 12, 13; Fig. 2(c), para. [0055]);
bonding a second glass carrier to the first conductive structure (Bonding a second glass carrier 30 to the first conductive structure 14; Fig. 2(d), para. [0057]);
after bonding the second glass carrier to the first conductive structure, performing a patterning process (¶61) to the second side of the first glass carrier to directly form through holes (40; Fig. 2(f)) from the second side (bottom side; Fig. 2(f)) of the first glass carrier opposite to the first side, penetrating through the first glass carrier (Fig. 2(f), ¶61);
forming a copper seed layer (¶65) in direct contact with the second side of the first glass carrier and conformally on sidewalls and bottoms of the through holes (the copper seed layer is formed through electroless process; Fig. 2(g), ¶¶65-66);
forming a conductive layer in the through holes and by using the copper seed layer as a seed (the plated material that forms the conductive through electrodes within the through holes; ¶¶65-66);
forming through holes from a second side of the first glass carrier opposite to the first side (Forming through holes 40 from a second side 10b of the first glass carrier 10 opposite to the first side 10a; Fig. 2(f), para. [0061]);
forming a copper seed layer conformally on sidewalls and bottoms of the through holes (Forming a seed layer conformally on sidewalls and bottoms of the through holes 40; Fig. 2(g), para. [0065]);
forming conductive vias in the through holes, wherein top and bottom surfaces of each conductive via are flushed with the first and second sides of the first glass carrier (Conductive vias are formed in the through holes 40 by using the copper seed layer as a seed, wherein the top and bottom surfaces of each conductive via are flushed with the first and second sides of the first glass carrier; Fig. 2(g), para. [0065]); and forming a second conductive structure on the second side of the first glass carrier opposite to the first side (Second conductive structure 15 is formed on the second side 10b of the first glass carrier 10 opposite to the first side 10; Fig. 2(g), para. [0066]).
However, Sawadaishi does not explicitly teach a method of forming a semiconductor comprising:
after bonding the second glass carrier to the first conductive structure, directly forming through holes from a second side of the first glass carrier opposite to the first side, penetrating through the first glass carrier of the original thickness, wherein the through holes further extend into the first conductive structure, and the through holes expose top surfaces of topmost metal features and sidewalls of topmost seed layers of the first conductive structure;
removing portions of the copper seed layer and the conductive layer outside of the through holes to form the conductive vias;
forming a second conductive structure on the second side of the first glass carrier opposite to the first side, wherein the second conductive structure comprises second metal features electrically connected to each other and embedded in second polymer layers, and a coefficient of thermal expansion (CTE) of a second polymer layer facing away from the first glass carrier is higher than a coefficient of thermal expansion (CTE) of a second polymer layer facing the first glass carrier, and wherein a number of the second polymer layers is less than a number of first polymer layers; and
providing a semiconductor package and bonded to the first conductive structure, wherein the semiconductor package comprises two dies and a redistribution layer structure directly formed on the dies, and the redistribution layer structure is bonded to the first conductive structure through bumps, wherein the CTE of a first polymer layer facing away from the first glass carrier is higher than a CTE of a first polymer layer facing the first glass carrier.
A person having ordinary skill in the art desiring to make the semiconductor structure of Sawadaishi would be motivated to look to related art to teach suitable techniques for adding functionality to the structure.
Chen teaches bonding a semiconductor package with two dies, die 300 and die 400, to a conductive structure 108 through conductive bumps 300e/400e (Fig. 1F, para. [0025, 0028]). Each die has a redistribution layer structure directly formed on the dies (Redistribution layer structures 300b and 400b; Fig. 1G, para. [0024-0025]).
As Sawadaishi states the semiconductor structure as taught thereby is an interposer (para. [0085]), a PHOSITA would know that the first conductive structure 14 of Sawadaishi is able to bond with the semiconductor package containing dies 300 and 400 of Chen, through the conductive bumps formed on the first conductive structure 14 of Sawadaishi (Fig. 6), choosing to do so to add logical device functions.
Takahashi teaches forming through holes (145; Fig. 8, ¶78) penetrating through a first glass carrier (110; Fig. 8, ¶78) with a first conductive structure (125; Fig. 8, ¶82) formed on a first side (top; Fig. 8) of the first glass carrier by a laser drilling process (¶77).
A PHOSITA would find it obvious to use a laser drilling process to form the through holes 40 of Sawadaishi, as taught by Takahashi, instead of the chemical etch (Sawadaishi: Fig. 2(f), ¶61) to form through holes with higher density, as laser drilling allows one to form through holes with a closer pitch (Ludden: Col. 5 Ln. 38-46) as compared to chemical etching, allowing for denser patterning.
Furthermore, as the thickness the first glass carrier of Sawadaishi is reduced according to an etch (¶39) to form the through holes that is now replaced with a laser drilling process having no etching step, the through holes are now formed to penetrate through the first glass carrier of the original thickness. Maintaining the original, greater thickness reduces the influence of vibration and flexure on the first glass carrier during processing steps (Takahashi: ¶8).
Wu teaches forming a first (104; Fig. 1) and second (102; Fig. 1, ¶14) conductive structure respectively on a first (bottom) and second (top) side of a first carrier, each conductive structure respectively comprises first and second metal features (112; Fig. 1) electrically connected to each other and embedded in a first and second polymer layer (dielectric layers formed from e.g., polyimide; ¶14).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form each metal feature of the first and second conductive structure according to Wu, as electroplating (e.g., Nakagawa: ¶95) using seed layers is a simple, inexpensive process capable of meeting performance requirements including low temperature operation, high deposition rates, and good step coverage.
Inagaki teaches conductive structures (55F and 55S; Fig. 9) using multiple polymer layers each (Fig. 9).
A PHOSITA would understand that forming multiple polymer layers having metal features is a repeatable processs (Wu: ¶14) that allows for the device interconnects to be fanned out according to design constraints. See also Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004).
Palanduz teaches forming layers of an interposer such that the CTE of each material used to form each respective layer increases the further each respective layer is from one side (Interposer 10 with layers 12, 14, and 16; Fig. 1, ¶22).
Nakagawa teaches adding filler to a polymer layer to reduce the CTE (¶¶70-71).
Morganelli teaches an amount of polymer filler material mixed into a polymer layer, so as to lower the CTE of the layer overall, can be as low as 0 wt %, i.e., filler-free (¶21).
A person having ordinary skill in the art before the effective filing date of the claimed invention would know to add filler as taught by Nakagawa to the first and second polymer layers such that the layers are formed with increasing CTE, as the fill amount may be a range (Morganelli: ¶21), to form the first and second polymer layers of Sawadaishi, in order to reduce stress within the semiconductor structure of Sawadaishi (Palanduz: ¶22), resulting in a CTE of a first polymer layer facing away from the first glass carrier 10 of Sawadaishi being higher than a CTE of a first polymer layer facing the first glass carrier 10, and likewise for a second polymer layer facing away from the first glass carrier 10 and a second polymer layer facing the first glass carrier 10.
Modified Sawadaishi has yet to be shown to teach the method comprising removing portions of the copper seed layer and the conductive layer outside of the through holes to form the conductive vias in the through holes.
Hirose teaches that plating using a seed layer (22+52; Fig. 4(M)-4(P)) may be part of a a plating operation that etches through a conductive layer (56; Fig. 4(M)-4(P)) and the seed layer using a mask formed on top of the plated stack after plating. Alternatively, the mask may be formed before plating the conductive layer (Fig. 5(M)’-5(P)’, ¶¶324-329).
Tsunetomo teaches that plating using a seed layer (12; Fig. 5(a)) may be part of a plating operation that etches through a conductive layer (part of material that forms 30 that is outside of a through hole 11; Fig. 5(b) and then 5(e)) and the seed layer using a photolithography process (¶163). Alternatively, portions of the conductive layer and the seed layer that are outside of the through hole may be removed through a backside grinding step (¶162) to form conductive vias (30; Fig. 5(d)), followed by subsequent formation of metal features (40a; Fig. 5(d), ¶162).
A PHOSITA would find it obvious to utilize the removal technique of Hirose where a mask is applied after plating using the seed layer (Hirose: Fig. 4(M)-4(P)) to remove the conductive layer and the seed layer on the second side of the first glass carrier, for forming the conductive vias of modified Sawadaishi, as removal of the conductive layer and the seed layer after plating is an art recognized alternative to forming a mask before plating using the seed layer in order to control where material in a plating operation is ultimately retained (Hirose: ¶¶324-329; Sawadaishi: “Next, the dry film resist no longer needed is dissolved away to form a through electrode. Then, the seed layer no longer needed is removed, and the surface is coated with an outer layer protective film such as an insulating resin or a solder resist layer. If any external connection terminal is required, an opening may be formed.”; Fig. 2(g), ¶65). See In re Fout, 675 F.2d 297, 213 USPQ 532 (CCPA 1982).
Furthermore, a PHOSITA would find it obvious to utilize the plating operation of Tsunetomo, where a grinding operation is performed to remove the parts of a seed layer and a conductive layer outside of a through hole to form conductive vias (Tsunetomo: Fig. 5(c)), with a subsequent formation of metal features (Tsunetomo: Fig. 5(d)), as this is an art recognized alternative method to control where plated material is retained in a plating operation (Tsunetomo: Fig. 5(c) and 5(e), ¶¶161-163). See In re Fout, 675 F.2d 297, 213 USPQ 532 (CCPA 1982).
This results in modified Sawadaishi teaching removing portions of the copper seed layer (Sawadaishi: Fig. 2(d), ¶65) and the conductive layer (Fig. 2(d), the conductive material plated in the through holes; ¶65) outside of the through holes (in the manner taught by Tsunetomo’s Fig. 5(a-d)) to form conductive vias in the through holes penetrating through the first glass carrier (Sawadaishi: conductive vias are formed within through holes 40, penetrating the first glass carrier 10; ¶65).
(Re Claim 22) Modified Sawadaishi teaches the method of claim 21, whereinsolder bumps are not present between the redistribution layer structure and each of the dies (Solder bumps are not present between the redistribution layer structures 300b and 400b, and the dies 300 and 400, respectively; Chen: Fig. 1G).
(Re Claim 23) Modified Sawadaishi teaches the method of claim 21, further comprising forming an underfill layer between the redistribution layer structure and the first conductive structure and around the bumps (Modified Sawadaishi: underfill layer UF is formed between the redistribution layer structures 300b and 400b of Chen, and the first conductive structure 14 of Sawadaishi, in the manner taught by Chen; Chen: Fig. 1G, para. [0030]).
(Re Claim 24) Modified Sawadaishi teaches the method of claim 21, wherein forming the first conductive structure comprises:
forming a first copper seed material layer on the first side of the first glass carrier (First seed layer on the first side 10a of the first glass carrier 10; Fig. 2(b), para. [0053]; Wu: ¶14);
forming a first metal line by using the first copper seed material layer as a seed (First metal feature is formed by using the first seed layer as a seed; Fig. 2(b), para. [0053]; Wu: ¶14);
forming a first metal via by using the first metal line as a seed (First metal via is formed by using the first metal feature as a seed; Fig. 2(c), para. [0055]).
(Re Claim 25) Modified Sawadaishi teaches the method of claim 21, but does not explicitly teach the method wherein forming the second conductive structure comprises: forming second lines completely covering the through vias, respectively.
Wu teaches forming second vias (the thicker portions of 112; Fig. 1) and second lines (the thinner portions of 112; Fig. 1), wherein the second lines are formed completely covering through vias (120; Fig. 1).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to from the second lines of modified Sawadaishi such that they completely cover the through vias (Sawadaishi: Fig. 2(g), ¶65), as a consequence of forming individual electrical connections to each through via, as taught by Wu, using electroplating. See Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004).
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Sawadaishi (US 2021/0118698), Palanduz (US 2006/0043567), Takahashi et al. (US 2015/0313020), Nakagawa et al. (US 20070194412), Chen et al. (US 2019/0131273), Morganelli (US 2015/0072478), Koizumu et al. (US 2014/0015121), Ludden et al. (US 5,637,925), Wu et al. (US 2016/0056087), and Inagaki et al. (US 2016/0064318), all of record, and Tsunetomo et al. (US 2017/0229318), both newly cited, as applied to claim 21 above, and further in view of Fujishima et al. (US 2020/0343184), and Kang et al. (US 2020/0144237), both of record.
(Re Claim 26) Modified Sawadaishi teaches the method of claim 21, but does not explicitly teach the method wherein a critical dimension of the first conductive structure is different from a critical dimension of the second conductive structure.
Koizumi teaches an interposer (10; Fig. 1B) having bumps (22 and 24) sized according to the contact pads of devices (such as 28) which are intended to be connected to the interposer. Here the bumps have different dimension.
A person having ordinary skill in the art before the effective filing date of the claimed invention would know that the metal features, vias, and bumps of the method of Sawadaishi can be readily changed to accommodate intended connection sizes, according to product requirements (Fujishima: ¶¶43, 54). As the resulting bump dimensional relationships is either such that a dimension of the first bump is less than a dimension of the second bumps, or vice versa, one of ordinary skill in the art would have had a reasonable expectation of success by selecting from this finite list of options, and thus it would have been obvious to try making a dimension of the first bumps less than a dimension of the second bumps, thereby allowing for the first conductive structure to have a fine pitch connection, because there are a finite number of identified, predictable solutions. The Supreme Court decided that a claim can be proved obvious merely by showing that the combination of known elements was obvious to try. Therefore, choosing from a finite number of identified, predictable solutions, with a reasonable expectation for success, is likely to be obvious to a person of ordinary skill in the art. See KSR International Co. v. Teleflex Inc., 550 U.S. 398, 415-421, USPQ2d 1385, 1395 - 97 (2007) (see MPEP § 2143, E.).
Inagaki teaches forming conductive structures (55F and 55S; Fig. 9) on opposite sides of a insulating layer (20z; Fig. 9), where the conductive structure (55F; Fig. 9) having finer-pitch bumps has three polymer layers compared to two for the other conductive structure (55S; Fig. 9).
A PHOSITA would find it obvious to form the first conductive structure using a greater number of polymer layers than that of the second conductive structure, when forming the first conductive structure to have finer-pitch connections than those of the second conductive structure, as forming fine-pitch vias is more readily achieved using multiple layers of thin polymer layers (Kang: ¶91). And forming one conductive structure using fewer polymer layers results in fewer overall steps, saving device processing time.
Forming the first conductive structure with metal features having comparatively finer pitch with the metal feature of the second conductive structure results in the critical dimension of the first conductive structure being different from a critical dimension of the second conductive structure.
Response to Arguments
Applicant's arguments filed 10/22/2025 have been fully considered but they are not persuasive.
Applicant appears to argue that any alteration in the thickness of a substrate or carrier having an identified second side, where the second side undergoes a process operation, results in that second side no longer being present in subsequent process operations (remarks, p. 15). However, Applicant never disclosed that the thickness of the substrate or carrier is retained between method steps described (such as between Fig. 6 and 7), and the presence of additional steps between any explicitly disclosed step is possible (instant: “Additional operations can be provided before, during, and/or after the method”; ¶9). Additionally, it is conventional within the art to describe sides or surfaces that are worked on to thin a substrate or carrier to retain their names and identifying marks even after the thinning step. For examples see Trovarelli et al. (US 2006/0270104), Fig. 1(a) to 1(e) with respect to the backside 6, and Grupen-Shemansky (5,268,068), Fig. 1 to 3 with respect to the back-side 13.
This argument based on thickness however, and others present in the remarks, are moot in view of the new rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lai et al. (US 2013/0320522) teaches alternately stacking metal features (14) and vias (16; 1c). Chen et al. (US 2018/0151530) teaches sequentially forming metal lines and vias to form an RDL structures (Fig. 6, ¶27).
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/CHRISTOPHER A. SCHODDE/Examiner, Art Unit 2898 /JESSICA S MANNO/SPE, Art Unit 2898