DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 08 September 2025 have been fully considered, and the response is set forth below:
Regarding the prior claim rejections under 35 U.S.C. 112(b) (Remarks; page 6), claims 2 and 26 have been amended to sufficiently clarify the issues outlines in the previous Office action. Therefore, the 112(b) rejections of claims 2 and 26 dated 08 April 2025 are withdrawn.
Regarding the argument that the prior art of record does not teach the newly amended limitations of claim 1 (Remarks; pages 6-7). Applicant’s arguments have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Newly cited Shunpei Yamazaki et al. (US 20220406981) teaches these features, and a new grounds of rejection, necessitated by the amendment, is presented below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6, 11, 21-22, and 24-25 are rejected under 35 U.S.C. 103 as being unpatentable over Shunpei Yamazaki et al. (US 2022/0406981; hereinafter Yamazaki) in view of Min Soo Kang (US 2017/0352791 A1; hereinafter Kang).
Regarding Claim 1, Yamazaki teaches a semiconductor processing method for forming an LED structure, the method comprising:
forming a backplane substrate (Fig. 3B; 150B; ¶0077) comprising control circuitry for activating LEDs of the LED structure (¶0090) and an electrically insulating passivation layer (Fig. 3B; 188; ¶0104);
forming an LED substrate (Fig. 3A; 150A; ¶0078) comprising:
a substrate layer (101; ¶0079);
a gallium-and-nitrogen-containing layer (GaN layer 115; ¶0081) formed on the LED substrate layer (101);
a first conductive layer (112; ¶0079; ¶0083) formed over the gallium-and-nitrogen- containing layer (115);
a mirror layer (metal layer of multi-layer stack of 112) formed over the transparent conductive layer (112); and
a bonding layer (104; ¶0087) formed over the mirror layer (metal layer of multi-layer stack of 112);
bonding the backplane substrate (150B) to the LED substrate (150A) to form bonded substrates (as shown in Fig. 4 and Fig. 5; ¶0087, ¶0114);
removing the substrate layer (101) from the bonded substrates to expose the gallium-and- nitrogen-containing layer (115) (as shown in Fig. 6A);
forming a second conductive layer (Fig. 7A; 117a, 117b, 117c; ¶0131) on the gallium-and-nitrogen- containing layer (115); and
patterning and forming LED structures (113a/114a/115a and 113b/114b/115b, which are respectively LED structure patterns 110a and 110b; ¶0068) in the bonded substrates after the LED substrate (150A) is bonded to the backplane substrate (150B) (as shown by the progression in Figs. 5, 6A, and 6B), wherein the bonded substrates comprise an array of LED pixels (Fig. 1, Fig. 2, Fig. 7B; or Fig. 8, ¶0068-¶0070) that are isolated on the backplane substrate by pixel isolation structures (Fig. 7B; BM isolated light from adjacent LEDs; ¶0137).
Yamazaki is silent regarding the multi-layer electrode stack (112) comprises a transparent conductive layer and a mirror layer formed over the transparent conductive layer, and wherein the second conductive layer is transparent, but does disclose that 112 is a stacked-layer structure (¶0079) and lists reflective metals (silver and aluminum) and alloy oxide compounds that are used in traditionally transparent electrodes (tin and zinc oxides) (¶0083).
In the same field of endeavor, Kang teaches a LED display (¶0144) comprising a stacked electrode structure of indium tin oxide (ITO) or indium zinc oxide (IZO) and a reflective (mirror) layer of silver (Ag) or Aluminum (Al) formed under the transparent electrode layer (in the finished product) (¶0092).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the stacked electrode structure of Kang in the method/device of Yamazaki to aid in light extraction of the finished LED (Kang; ¶0092-¶0091). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the transparent conductive material (ITO/IZO) of Kang for the second electrode layer (Yamazaki; 117a,117b,117c) in order to improve light extraction from the device in the output direction of the light (Yamazaki; Fig. 8, where the light R or B light passes the electrodes 117a,117b, 117c). The substitution of a known equivalent for another known equivalent is prima facie case of obviousness. The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945).
Regarding Claim 6, modified Yamazaki teaches the semiconductor processing method of claim 1, wherein the array of LED pixels has a pixel density of greater than or about 1000 pixels per inch (as described in Yamazaki ¶0302; “further preferably higher than or equal to 1000 ppi, still further preferably higher than or equal to 3000 ppi, still further preferably higher than or equal to 5000 ppi, and yet further preferably higher than or equal to 7000 ppi. With the display unit with such high resolution and/or high definition, the electronic device can have higher realistic sensation, sense of depth, and the like in personal use such as portable use and home use”).
Regarding Claim 11, modified Yamazaki teaches the semiconductor processing method of claim 1, wherein the pixel isolation structures (Yamazaki; BM) are formed in the bonded substrates after the LED substrate (150A) is bonded to the backplane substrate (150B) (as shown in Yamazaki Fig. 3A to 7B).
Regarding Claim 21, modified Yamazaki teaches the semiconductor processing method of claim 1, wherein the backplane substrate (Yamazaki; Fig. 3B and 7B; 150B) comprises a first contact (190b; ¶0104) and a second contact (190a; ¶0104) for each LED in the array of LED pixels.
Regarding Claim 22, modified Yamazaki teaches the semiconductor processing method of claim 21, further comprising forming an electrically conductive via (Yamazaki; Fig. 7B; 116a; ¶0129) between the second contact (190a) and a surface of the gallium-and-nitrogen-containing layer (115a) (wherein via 116a is between the electric path from the top surface of 115a and the top surface of 190a) such that the first contact (190b) is electrically isolated from the second contact (190a) by the electrically insulating passivation layer (188) (as shown in Yamazaki Fig. 7B).
Regarding Claim 24, modified Yamazaki teaches the semiconductor processing method of claim 1, further comprising forming a second electrically insulating passivation layer (Yamazaki; Fig. 6A to 6B; 102; ¶0126) around each LED (113a,114a,115a and 113b,114b,115b respectively) in the array of LED pixels after patterning and forming the LED structures in the bonded substrates (as shown in Fig. 6A to 6B; 102 is formed after the individual LEDs are patterned from the LED substrate 150A after bonding with 150B; and 102 is formed around each respective LED structure).
Regarding Claim 25, modified Yamazaki teaches the semiconductor processing method of claim 1, further comprising forming the pixel isolation structures (Yamazaki; BM) around the LEDs in the array of LED pixels (as described in Yamazaki ¶0137: “Note that an opening that surrounds the light-emitting diode may be provided in the insulating layer 102 and a light-blocking layer BM may be provided to fill the opening as illustrated in FIG. 7B. Thus, light emitted from the light-emitting diode is inhibited from reaching an adjacent subpixel, which can improve the display quality of the display unit. There is no particular limitation on materials of the light-blocking layer BM”) after patterning and forming the LED structures in the bonded substrates (as shown in Fig. 7B).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki in view of Kang and Chao-Hsing Che et al. (US 2017/0373226 A1; hereinafter Chen).
Regarding Claim 2, modified Yamazaki teaches the semiconductor processing method of claim 1, wherein each of the LED pixels comprises a gallium-and-nitrogen-containing light-emitting-diode structure (Yamazaki; ¶0081) operable to emit a first-wavelength light characterized by an ultraviolet wavelength (Yamazaki; ¶0081).
Yamazaki is silent regarding the ultraviolet wavelength being a wavelength less than or about equal to 400 nm. However, this is the wavelength range of ultraviolet light. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, that the ultraviolet light of Yamazaki is characterized by a wavelength of 400nm or less, because that is the wavelength range of UV light, as shown in the evidentiary reference Chen in ¶0015 wherein a LED comprising GaN emits UV light in a wavelength range of 400-250nm.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki in view of Kang and Hung-Cheng Lin et al. (US 2022/0093834 A1; hereinafter Lin).
Regarding Claim 7, modified Yamazaki teaches the semiconductor processing method of claim 1, wherein the area of each LED is less than 700µm, but is silent regarding a longest dimension of each of the isolated pixels is less than or about 10 µm.
In the same field of endeavor, Lin teaches a similar device and method. Lin teaches in ¶0625 that the microLED device can have a dimension as small as 2µm.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have dimensions of the LED of Yamazaki at 2µm (as in Lin) in order to support good display quality for near-eye displays (Lin; ¶0635) applicable to Yamazaki’s near-eye display use (Fig. 11A; Fig. 12A; Fig. 12B) while continuing the trend in the art to downscale the size of components to meet the demand for smaller devices.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki in view of Kang and Rajendra D. Pendse (US 2022/0285601 A1; hereinafter Pendse).
Regarding Claim 8, modified Yamazaki teaches the semiconductor processing method of claim 1, but does not expressly disclose wherein the method further comprises forming a microlens on at least one of the LED pixels (254).
In the same field of endeavor, Pendse teaches a micro-LED display for use in near-eye applications (Pendse; Fig. 2 and Fig. 3) with bonded backplane and LED substrates (Pendse; Fig. 8A/8B; LED substrate 802 and backplane substrate 803), and forming a microlens (Pendse; Fig. 10; 1082; ¶0111) on at least one of the pixels.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the microlens on at least one LED pixel of Pendse in the method of Yamazaki in order to improve light extraction for the device (Pendse; ¶0110).
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki in view of Kang and Katsuji Iguchi et al. (US 2021/0151422 A1; hereinafter Iguchi).
Regarding Claim 26, modified Yamazaki teaches the semiconductor processing method of claim 25, but is silent regarding wherein the pixel isolation structures (BM) are enclosed in an additional mirror layer operable to reflect light emitted from the gallium-and-nitrogen-containing layers (15) of the array of LED pixels.
In the same field of endeavor, Iguchi teaches forming pixel isolation structures (Iguchi; Fig. 3C; 35) enclosed in a mirror layer (Iguchi; Fig. 3C; reflective material film 36L; ¶0094).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the mirror layer on the pixel isolation structures (of Iguchi) in the device/method of Yamazaki. One of ordinary skill in the art would have motivation to make this combination in order to achieve a reduction in cross-talk between adjacent sub-pixels (Iguchi; ¶0124).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN PRIDEMORE whose telephone number is (703)756-4640. The examiner can normally be reached Monday - Friday 8:00am - 4:00pm EST.
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NATHAN PRIDEMORE
Examiner
Art Unit 2898
/NATHAN PRIDEMORE/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898