DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02 July 2025 has been entered.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the:
“at least one through opening in the first portion”…“wherein the semiconductor die is attached by an adhesive” (Claim 2),
“at least one through opening in the first portion”…“an active surface of the semiconductor die faces away from the inner surface of the first portion of the cap…further including a plurality of wires electrically connected between the active surface of the semiconductor die and the plurality of electrical leads” (Claim 8),
“at least one through opening in the first portion”…“a die pad between the semiconductor die and the cap” (Claim 10), and
“at least one more opening in the cap” (Claim 25)
must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 2, 8, and 10 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding Claim 2, the limitation “wherein the semiconductor die is attached by an adhesive” in combination with the previous limitation in Claim 1 of “where the at least one through opening in the first portion” was not disclosed in the originally filed application. The amendment appears to combine the embodiment of Figures 3a-b (Claim 1) with that of Figures 1a-b/2a-b/4d (Claim 2). There is no disclosure of a cap having an aperture with a semiconductor chip mounted on it using adhesive.
Regarding Claim 8, the limitation “an active surface of the semiconductor die faces away from the inner surface of the first portion of the cap…a plurality of wires electrically connected between the active surface of the semiconductor die and the plurality of electrical leads” in combination with the previous limitation in Claim 1 of “where the at least one through opening in the first portion” was not disclosed in the originally filed application. The amendment appears to combine the embodiment of Figures 3a-b (Claim 1) with that of Figures 1a-b/2a-b/4d (Claim 8). There is no disclosure of a cap having an aperture with a semiconductor chip wire bonded to it with an active surface facing away from the aperture.
Regarding Claim 10, the limitation “a die pad between the semiconductor die and the cap” in combination with the previous limitation in Claim 1 of “where the at least one through opening in the first portion” was not disclosed in the originally filed application. The amendment appears to combine the embodiment of Figures 3a-b (Claim 1) with that of Figures 2a-b (Claim 10). There is no disclosure of a cap having an aperture with a semiconductor chip mounted thereon with a die pad in between.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 4 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites the limitation “the first surface of the first portion of the cap” in line 2. There is insufficient antecedent basis for this limitation in the claim. The parent claim establishes a “each wall…having..a first surface” and “each electrical lead having a first surface”, but there is no established first surface of the first portion of the cap. Furthermore, the parent claim already requires “a plurality of leads…extending on the first portion”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Peterson (U.S. 6,956,283) in view of Lin et al. (U.S. 2012/0018830)
Regarding Claim 1, Peterson Figure 5e discloses a semiconductor device package, comprising:
a cap (20) having:
a first portion;
a plurality of walls extending from the first portion, each wall of the plurality of walls having:
a first surface transverse to the first portion;
a second surface transverse to the first surface; and
a third surface opposite the first surface (cap 20); and
at least one through opening in the first portion (opening 36);
a plurality of electrical leads disposed along a perimeter of the cap and extending on the first portion ad the plurality of walls, each electrical lead of the plurality of electrical leads being on the first and second surface of a respective wall, (leads 22); and
a semiconductor die (4) coupled to the first portion of the cap, the semiconductor die electrically coupled to the plurality of electrical leads and in fluid communication with an exterior environment via the at least one through opening.
However, they do not explicitly disclose wherein each electrical lead has a first surface that is coplanar with the third surface of the respective wall. In the same field of endeavor Lin et al. discloses a device mounted to an apertured cap, wherein a plurality of electrical leads disposed along a perimeter of the cap extend on a first portion of a plurality of walls and wherein each electrical lead has a first surface that is coplanar with a third surface of the respective wall (Lin et al., chip 3, cap 21, leads 212, third surface 2111, first surface 2113, Figures 2 and 4). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form each electrical lead to have a first surface that is coplanar with the third surface of the respective wall in Peterson in view of Lin et al. in order to reduce device height and reduce risk of short-circuiting (Lin et al., [0007] and[0042]).
Regarding Claim 2, Peterson in view of Lin et al. further discloses wherein the semiconductor die is attached by an adhesive (Peterson, adhesive 23, Figure 5e) .
Regarding Claim 3, Peterson in view of Lin et al. further discloses wherein the semiconductor die is attached by solder (Peterson, cap 20, chip 4, solder 33, Figure 5e).
Regarding Claim 4. Peterson in view of Lin et al. further discloses wherein the plurality of electrical leads extend at least partially on the first surface of the first portion of the cap (Peterson, leads 22, cap 20, Figure 5e).
Regarding Claim 5 Peterson in view of Lin et al. further discloses wherein the at least one through opening is in a central region of the first portion of the cap (Peterson, opening 36, Figure 5e).
Regarding Claim 6, Peterson in view of Lin et al. further discloses wherein the semiconductor die includes at least one sensor in fluid communication with the exterior environment via the at least one through opening (Peterson, cap 20, opening 38, sensor 4, Figure 5d, Column 6, Lines 17-45).
Regarding Claim 7, Peterson in view of Lin et al. further discloses wherein the at least one sensor includes at least one of a pressure sensor, a temperature sensor, a humidity sensor, a sound sensor, or an optical sensor (Peterson, Column 6, Lines 17-45)
Regarding Claim 9 Peterson in view of Lin et al. further discloses wherein the semiconductor die is on the plurality of electrical leads (Peterson, leads 22, cap 20, Figure 1, Lin et al., leads 211).
Regarding Claim 10. Peterson in view of Lin et al. further discloses wherein a die pad between the semiconductor die and the inner surface of the cap (Peterson, die pad 39, 5e, Lin et al. die pad 23, Figure 1).
Claims 5 is rejected under 35 U.S.C. 103 as being unpatentable over Peterson (U.S. 6,956,283) in view of Lin et al. (U.S. 2012/0018830) as applied to Claim 1.
Regarding Claim 8. Peterson in view of Lin et al. do not explicitly wherein the first portion has an inner surface and an active surface of the semiconductor die faces away from the inner surface of the first portion of the cap, the semiconductor device package further including a plurality of wires electrically connected between the active surface of the semiconductor die and the plurality of electrical leads. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to mount the chip in the opposite orientation as flip chip in Peterson in view of Lin et al., as Peterson teaches that the cap structure can be used for both wire bonded and flip chips (Peterson, Column 8, Lines 48-56). Furthermore The Examiner takes Official Notice of the fact that it was known in the art to mount a semiconductor die to face away from an inner surface of a package cavity and wire bond the semiconductor die to a plurality of electrical leads on the package so as to have flexible package design.
Claims 21-24 and 26-28 are rejected under 35 U.S.C. 103 as being unpatentable over Peterson (U.S. 6,956,283) in view of Lin et al. (U.S. 2012/0018830)
Regarding Claim 21. Peterson Figure 5e discloses a semiconductor device package, comprising:
a cap (20) having:
an inner surface extending along a first direction;
an outer surface opposite the inner surface; and
walls along a perimeter of the cap and extending along a second direction that is transverse to the first direction (cap 20), each of the walls having:
a first surface transverse the inner surface of the cap;
a second surface transverse the outer surface of the cap; and
a third surface extending between the first and second surfaces (cap 20);
a plurality of electrical leads (22) on the cap, the plurality of electrical leads extending on the inner surface, the first surface, and the third surface (leads 22, cap 20);
a semiconductor die (4) on and coupled to the inner surface of the cap; and
an opening (36) extending along the second direction through the cap.
However, they do not explicitly disclose wherein each of the plurality of electrical leads has a surface that is coplanar with the second surface of the cap. In the same field of endeavor Lin et al. discloses a device mounted to an apertured cap, wherein a plurality of electrical leads disposed along a perimeter of the cap extend along the inner surfaces and wherein each of the plurality of electrical leads has a surface that is coplanar with the second surface of the cap (Lin et al., chip 3, cap 21, leads 212, third surface 2111, first surface 2113, Figures 2 and 4). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form each of the plurality of electrical leads to have a surface that is coplanar with the second surface of the cap in Peterson in view of Lin et al. in order to reduce device height and reduce risk of short-circuiting (Lin et al., [0007] and [0042]).
Regarding Claim 22. Peterson in view of Lin et al. further discloses wherein the opening is through a central portion of the cap (Peterson, opening 36, Figure 5e).
Regarding Claim 23. Peterson in view of Lin et al. further discloses wherein an active surface of the semiconductor die faces the inner surface of the cap (Peterson, die 4, cap 20 Figure 5e).
Regarding Claim 24, Peterson in view of Lin et al. further discloses wherein the opening is configured to allow a path through which ambient air, pressure, temperature, or an external environment is fluidically connected to the inner surface of the cap (Peterson, cap 20, opening 36, sensor 4, Figure 5d, Column 6, Lines 17-45).
Regarding Claim 26, Peterson in view of Lin et al. further discloses wherein the semiconductor die is configured as a pressure sensor and includes a diaphragm configured to sense pressure, wherein the diaphragm is located at an active surface of the semiconductor die (Peterson, cap 20, opening 38, sensor 4, Figure 5d, Column 6, Lines 17-45).
Regarding Claim 27, Peterson in view of Lin et al. further discloses wherein the semiconductor die is configured as an optical sensor and includes a light emitting device and a light receiving device, wherein a respective opening in the cap is aligned with each of the light emitting device and the light receiving device of the semiconductor die (Peterson, cap 20, opening 38, sensor 4, Figure 5d, Column 6, Lines 17-45)
Regarding Claim 28. Peterson in view of Lin et al. further discloses wherein the semiconductor die is configured to emit or receive radiation through the (opening (Peterson, cap 20, opening 38, sensor 4, Figure 5d, Column 6, Lines 17-45).
Claims 25 is rejected under 35 U.S.C. 103 as being unpatentable over Peterson (U.S. 6,956,283) in view of Lin et al. (U.S. 2012/0018830) as applied to Claim 21, further in view of Kim (U.S. 10,903,134).
Regarding Claim 25. Peterson in view of Lin et al. discloses the limitations of Claim 21 but does not explicitly disclose at least one or more opening in the cap. Kim discloses a similar device wherein a cap having a die mounted thereon with electrical leads on the underside has two or more openings (Kim, cover 13/14a/14b, opening holding lens 11, leads 13a/b chip 10, Figures 2, 3, and 6, Column 14, Lines 22-42). Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to include two or more openings in the cap in Peterson in view of Lin et al., further in view of Kim in order to satisfy emission or detection purposes (Kim, Column 14, Lines 22-42). Furthermore it has been held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced, In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960), see MPEP 2144.04.
Claims 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Peterson (U.S. 6,956,283) in view of Sano et al. (U.S. 5,589,711) and Lin et al. (U.S. 2012/0018830).
Regarding Claim 19, Chia et al. discloses an electronic device, comprising:
a semiconductor device package electrically, the semiconductor device package including:
a cap having
a first surface extending along a first direction;
a second surface opposite the first surface;
at least one opening extending through the first and second surfaces along a second direction that is transverse to the first direction;
a third surface traverse the first surface;
a further surface transverse the third surface and opposite the second surface; and
a fifth surface opposite the third surface, the fourth surface extending between the third and fifth surfaces (cap 210, Figure 3);
a plurality of electrical leads arranged around a perimeter of the cap and extending on the first, third, and further surfaces of the cap; and
a semiconductor die coupled to the first surface of the cap, the semiconductor die electrically coupled to the plurality of electrical leads (die 130, Figure 3).
However, they do not explicitly disclose a microprocessor connected to the semiconductor package or each electrical lead of the plurality of electrical leads having a surface that is coplanar with the fifth surface of the cap.
In the same field of endeavor, Sano et al. discloses that microprocessors are conventional in multi-chip packages (Sano et al., cover 22, microprocessor 21, Figure 2, Column 1, Lines 25-35, Column 4, Lines 15-25). Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to form the processor as a microprocessor in Peterson in view of Sano et al. as it was conventional to use microprocessors as processors in multi-chip packages (Sano et al., Column 1, Lines 25-35, Column 4, Lines 15-25).
In the same field of endeavor Lin et al. discloses a device mounted to an apertured cap, wherein a plurality of electrical leads disposed along a perimeter of the cap extend along the cap and wherein each electrical lead of the plurality of electrical leads has a surface that is coplanar with the fifth surface of the cap (Lin et al., chip 3, cap 21, leads 212, third surface 2111, first surface 2113, Figures 2 and 4). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form each lead of the plurality of electrical leads to have a surface that is coplanar with the fifth surface of the cap in Peterson in view of Lin et al. in order to reduce device height and reduce risk of short-circuiting (Lin et al., [0007] and [0042]).
Regarding Claim 20, Peterson in view of Sano et al. and Lin et al.1 further discloses wherein the electronic device is at least one of a cell phone, a smartphone, a tablet computer device, a camera, a wearable computing device, a vehicle, or a robotic machine (Lin et al., [0004)).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 19, and 21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Abbigale Boyle whose telephone number is 571-270-7919. The Examiner can normally be reached from 11 A.M to 7 P.M., Monday through Friday.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, Zandra Smith, can be reached at 571-272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance form a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
Abbigale Boyle
Examiner, Art Unit 2899
/ABBIGALE A BOYLE/Examiner, Art Unit 2899
/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899