The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA
DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 3-5 and 21-24 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claimed limitation of “the first gate electrode is electrically connected to the second transistor without any circuit elements”, as recited in claims 1 and 21 are unclear as to how the first gate electrode can be electrically connected to the second transistor without any circuit elements, since a wire or a conductor are “elements” (as being a “chemical element”) and being located in a circuit, rendering it a “circuit element”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-5, 7-11, 13-15 and 17-24, as best understood, are rejected under 35 U.S.C. 103 as being unpatentable over Tanizawa et al. (JP 04360570) in view of Yamazaki et al. (7,750,476) and Kurokawa et al. (2011/0215323).Regarding claims 1, 11 and 21, Tanizawa et al. teach in figure 5 and related text a semiconductor device comprising
a first transistor comprising:
a first channel formation region (located in substrate 11 between elements 13 and 14) included in a first semiconductor;
a first insulator (gate dielectric) over the first channel formation region; and
a first gate electrode 15 over the first insulator, the first gate electrode overlapping with the first channel formation region;
a second insulator 16 over the first gate electrode;
a second transistor comprising:
a second gate electrode (another 15 on the second level) and a first metal layer (un-numbered electrically connected to element 17) over the second insulator 16;
a third insulator (another 16) over the second gate electrode (another 15 on the second level)
a second channel formation region 19 (on the third level) over the third insulator, a semiconductor layer comprising the second channel formation region;
a fourth insulator (another 16) over the second channel formation region 19 (on the third level);
a third gate electrode (another 15on the third level) over the fourth insulator, the third gate electrode overlapping with the second channel formation region;
a fifth insulator (another 16) over the third second gate electrode (another 15 (on the third level), the fifth insulator having an opening (where the interconnects are located), wherein the opening overlaps with a first region included in the second semiconductor; and
a first metal 14/17 over the fifth insulator and in the opening, the first metal layer 14/17 directly contacted with the second semiconductor through the opening,
wherein a second region (arbitrarily chosen) included in the second semiconductor does not overlap with the opening,
wherein the first gate electrode 15 (of section 20) is electrically connected to the second transistor (of section 21) without any circuit elements (see figure 6),
wherein a part of the third gate electrode is positioned over the second channel formation region included in the second semiconductor, and
wherein a part of a bottom surface of the second gate electrode is positioned under a top surface of the second semiconductor.
Tanizawa et al. do not teach that the first channel formation region comprises silicon and the second semiconductor comprises an oxide semiconductor, and do not teach that the first region is thinner than the second region.
Yamazaki et al. teach in figures 3A-3C and related text that the first region is thinner than the second region.
Kurokawa et al. teach in figure 9 and related text that the amplifier first channel formation region 1902 comprises silicon and the reset transistor second semiconductor 1904 comprises an oxide semiconductor.
Kurokawa et al., Tanizawa et al. and Yamazaki et al. are analogous art because they are directed to interconnects of semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Tanizawa et al. because they are from the same field of endeavor.It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the first channel formation region comprises silicon and the second semiconductor comprises an oxide semiconductor, as taught by Kurokawa et al., and to form the first region is thinner than the second region, as taught by Yamazaki et al., in Tanizawa et al.’s device, in order to improve the device characteristics by implementing well known materials when using the device in an application which uses amplifiers and which requires low off-state current transistors, and in order to provide better electrical connection to the active region of the device, respectively.
The combination is motivated by the teaching of Kurokawa et al. who states that transistors 1902 are used as amplifiers and reset transistors 1904 are formed of silicon semiconductor. Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form some transistors formed of oxide semiconductor and some of silicon semiconductor when using Tanizawa et al.’s device in application which requires amplifiers and selection transistors.
Regarding claims 3 and 13, Tanizawa et al. teach in figure 1 and related text a transistor comprising the first channel formation region is a p-channel transistor.
Regarding claims 4 and 14, it would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the first channel formation region as an n-channel transistor in Tanizawa et al.’s device in order to use the device in application which requires an n-channel transistor because it is well known in the art to reverse the polarity of the device.
Regarding claims 5 and 5, in the combined device the second metal penetrates the second semiconductor.
Regarding claims 7 and 17, Tanizawa et al. teach in figure 1 and related text a first edge of the third second gate electrode overlaps with the second gate electrode.
Regarding claims 8 and 18, it would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to use Tanizawa et al.’s device as a display device in order to enhance the capabilities of the device.
Regarding claims 9-10 and 19, it would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to use Tanizawa et al.’s device as a module comprising an FPC, a frame and at least one of a battery batter, a touch panel, and a backlight unit, in order to use the device in a practical application.
Regarding claims 11 and 22, Tanizawa et al. teach in figure 6 and related text that the first gate electrode (of section 20) is directly electrically connected to the second transistor (of section 21) in a circuit diagram only by a conductor configured to be a wiring. Tanizawa et al. do not teach that the first channel formation region comprises single crystal silicon.
it would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the first channel formation region comprises single crystal silicon in Tanizawa et al.’s device in order to improve the device characteristics.
Regarding claim 21, Tanizawa et al. teach in figure 1 and related text that a first edge of the third second gate electrode overlaps with the second gate electrode, a third metal layer over the fifth insulating layer, the third metal layer electrically connected to the third gate electrode and wherein the third metal layer overlaps with and is electrically connected to the first metal layer.
Regarding claims 23-24, a second metal (another element 17) between the second insulator and the third insulator, wherein the first metal and the second metal overlap each other.
Response to Arguments
1. Applicants argue that “Tanizawa expressly links fixed-potential wiring to crosstalk prevention”.
1. The examiner does not find any argument against the rejection over Tanizawa.
2. Applicants argue that “Tanizawa's own teachings - demonstrating that such modification renders Tanizawa unsatisfactory for its intended purpose”, because the “Examiner proposes modifying Tanizawa's interlayer connections (e.g., elements 31, 32, 33, 34 and their variants) using transistor structures from Kurokawa (e.g., 1902, 1904, 1912). However, Tanizawa teaches that the interlayer connections must be formed with fixed-potential shielding lines to suppress crosstalk”.
2. The rejection recites “Tanizawa et al. do not teach that the first channel formation region comprises silicon and the second semiconductor comprises an oxide semiconductor” and that “Kurokawa et al. teach in figure 9 and related text that the amplifier first channel formation region 1902 comprises silicon and the reset transistor second semiconductor 1904 comprises an oxide semiconductor”.
The examiner does not find that the above argument prevents an artisan from modifying Tanizawa in view of Kurokawa.
3. Applicants argue that Tanizawa does not teach circuits but rather “first and third layers: three inverters in series, second layer: logic circuit of NAND and NOR, fourth layer: photodiode circuit with switching transistors. These "circuits" are structured functional units, not single isolated transistors. Nothing in Tanizawa teaches connecting individual transistors across layers. The Examiner's interpretation expands the meaning of "circuit" beyond its reasonable scope and beyond what a person of ordinary skill would understand from Tanizawa. Such reinterpretation cannot form a proper basis for a combination under the broadest reasonable interpretation standard”.
3. The Examiner disagree that the “interpretation expands the meaning of "circuit" beyond its reasonable scope and beyond what a person of ordinary skill would understand from Tanizawa”. Even applicants agree that the second layer comprises a circuit, by stating that “second layer: logic circuit of NAND and NOR” (emphasis added).
4. Applicants argue that “The Advisory Action states that "transistor 1912 is also an OS transistor" and is connected to a power supply potential. Applicant submits that this is incorrect.
Element 1912 is labeled 'FD' in Kurokawa and is not a transistor. Applicant understood the Examiner's reference to "also OS transistor" as a typographical error referring to element 1902”.
4. The statement "transistor 1912 is also an OS transistor" recited in the advisory action refers to the OS transistor 1904 which is located at the source/drain point 112 being a point potential of a signal charge accumulation portion 112 (FD).
5. Applicants argue that “even if FD 1912 were connected to a fixed potential, this does not make it equivalent to Tanizawa's dedicated ground/power supply wirings designed explicitly for shielding”.
5. As stated earlier, the rejection recites “Tanizawa et al. do not teach that the first channel formation region comprises silicon and the second semiconductor comprises an oxide semiconductor” and that “Kurokawa et al. teach in figure 9 and related text that the amplifier first channel formation region 1902 comprises silicon and the reset transistor second semiconductor 1904 comprises an oxide semiconductor”. Point FD 1912 is connected to a fixed potential Vdd, as depicted in figure 9 of Kurokawa et al.
6. Applicants argue that “Independent claims 1 and 11 recite a first transistor having a silicon channel and a second transistor having an oxide-semiconductor channel, wherein the gate of the first transistor is connected to the second transistor
in the circuit diagram. The Advisory Action does not explain how the proposed modification of Tanizawa using FD 1912 or other elements from Kurokawa would satisfy this claimed relationship”.
6. The rejection recites that Tanizawa et al. teach in figure 6 and related text that the first gate electrode 15 (of section 20) is electrically connected to the second transistor (of section 21) without any circuit elements (see figure 6).
The rejection further recites that the modified device of Tanizawa et al. teach a first transistor having a silicon channel and a second transistor having an oxide-semiconductor channel. It is unclear as to what explanation applicants require in addition to the explanation provided in the rejection wherein it is asserted that the “combination [recited in the rejection] is motivated by the teaching of Kurokawa et al. who states that transistors 1902 are used as amplifiers and reset transistors 1904 are formed of silicon semiconductor. Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form some transistors formed of oxide semiconductor and some of silicon semiconductor when using Tanizawa et al.’s device in application which requires amplifiers and selection transistors”.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ORI NADAV whose telephone number is 571-272-1660. The examiner can normally be reached between the hours of 7 AM to 4 PM (Eastern Standard Time) Monday through Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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O.N. /ORI NADAV/
2/5/2026 PRIMARY EXAMINER
TECHNOLOGY CENTER 2800