DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/26/2026 has been entered.
Status of Claims
Claims 21-25, 28-32, 36-38 and 40-44 are pending.
Claims 1-20, 26-27, 33-35 and 39 are canceled.
Claims 21 and 36 are currently amended.
Claims 23, 28-32 and 40-44 are original.
Claims 22, 24-25 and 37-38 are previously presented.
Claims 21-25, 28-32, 36-38 and 40-44 are rejected herein.
Response to Arguments
Applicant's arguments filed 01/26/2026 have been fully considered but they are not persuasive.
Applicant argues that “the term ‘substantially’ in claim 22, is definite.” Remarks, page 7. This argument is not persuasive.
Notably, the Applicant’s argument appears to rely at least in part on the mistaken belief that the rejection of claims 22-24 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph is made because the use of the word “substantially” inevitably introduces fatal ambiguity into the claim. This is not the case. Rather, the rejection is based on the fact that the specification fails to provide any explanation or guidelines whatsoever by which one or ordinary skill in the art could determine what is meant by the phase “substantially in alignment” as used in claim 22. Indeed, absent the use in claim 22, the phase does not otherwise appear in the Applicant’s specification and there is no indication whatsoever of what constitutes “substantial” alignment of the gap region along the wordline direction. Accordingly, it is unclear what range of alignments along the wordline direction the gap region must conform to in order to be “substantially in alignment” therewith and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. For example, it is unclear if the scope of the invention includes a gap region which is, for example, within 5 degrees in alignment with the wordline direction, or within 1 degree of such alignment, or within 10 degrees of such alignment, or otherwise. Again, this is not an instance where the use of the word “substantially” has been reflexively objected to because it inevitably introduces fatal ambiguity into the claim. Rather, the specific use of the word “substantially” in this particular circumstance is at issue and the term has been thus evaluated given the particulars of this case.
When a term of degree (e.g., such as “substantially”) is used in a claim, it is proper to determine whether the specification provides some standard for measuring that degree, and if the specification does not provide some standard for measuring that degree, it is proper to determine whether one of ordinary skill in the art could nevertheless ascertain the scope of the claim, e.g., from a standard that is recognized in the art for measuring the meaning of the term of degree. See, e.g., MPEP §2173.05(b)(I). In the present case, it is found that the specification provides no such standard measuring the degree, and there is no standard that is recognized in the art for measuring the meaning of the term of degree, i.e., “substantially,” as used in the context of claim 22.
Accordingly, the rejection of claims 22-24 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph is maintained herein.
With respect to claim 21, Applicant argues that Kondo fails to disclose certain claim limitations recited therein. Remarks, page 8. However, the rejections of the claims herein are not based on Kondo. Accordingly, Applicant’s arguments against Kondo are moot.
With regard to claim 21, Applicant also argues that Shin fails to disclose certain claim limitation recited therein. Remarks, page 8. However, the rejections of the claims herein are not based on Shin as a primary reference. Rather, Shin is applied as a secondary reference herein for teaching the interchangeability of a charge storage layer comprising a charge trapping layer and a charge storage layer comprising a floating gate layer. See, e.g., the rejections of claims 30 and 43 herein below. That is to say, Applicant’s arguments against Shim are not directed to the limitation for which Shim is being applied. Accordingly, Applicant’s arguments against Shin are likewise moot and/or otherwise not persuasive.
Further with respect to claim 21, Applicant’s also argues that “each trench 54 of Sakike [sic] is not separated from other trenches 54 of Sakike [sic] by at least one slit ST.” Remarks, page 8. This argument is not persuasive.
Notably, with respect to claim 21, only the two grooves (541) and (542) of Sakaike are being read as the claimed “plurality of groove.” See, e.g., annotated FIG. 1 herein. Accordingly, each one of the grooves (541) and (542) of the plurality of grooves is separated from the other one of the grooves (541) and (542) of the plurality of grooves by at least one separation trench (ST), namely, the separation trench (ST2). See, e.g., annotated FIG. 1 herein.
Applicant also argues that “[c]laim 36 is patentable for similar reasons as to why claim 21 is patentable. Remarks, page 9. This argument is not persuasive. Notably, claim 21 has not been found patentable. Moreover, it is noted that claim 36 differs from claim 21 in that claim 36 does not recite “a plurality of grooves” as does claim 21, but rather claim 36 recites “first and second grooves” which claim 21 does not.
Applicant also argues that “[t]he currently-pending dependent claims are also patentable for at least” the reasons alleged with respect to claim 21. This argument is not persuasive. Notably, claim 21 has not been found patentable. Moreover, the Applicant fails to identify any limitation in any dependent claim which further distinguishes such dependent claim over the prior art of record nor does Applicant argue with any particularity how the rejection of any dependent claim is further in error.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 22-24 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “substantially” in claim 22 is a relative term which renders the claim indefinite. The term “substantially” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. In particular, the degree to which the gap region must be in alignment along the wordline direction is made unclear by the use of the offending term. For examination purpose, “substantially in alignment” as claimed shall be read as in alignment to some undefined degree.
Claims 23-24 depend from claim 22 and hence are rejected for at least the same reasons as claim 22.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 21-25, 28-29, 31 and 32 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sakaike (US 20170263615 A1).
[AltContent: textbox (542)][AltContent: arrow][AltContent: textbox (541)][AltContent: arrow][AltContent: textbox (ANNOTATED FIG. 1 OF SAKAIKE)][AltContent: rect][AltContent: textbox (SCR)][AltContent: textbox (ST3)][AltContent: textbox (ST2)][AltContent: textbox (ST1)][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: textbox (GR)][AltContent: rect]
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Regarding claim 21, Sakaike (see generally annotated FIGS. 1 and 6 herein, and FIGS. 5A-9B and 24-27B) discloses:
a method of manufacturing a 3-dimensional NAND (3D- NAND) memory device (1), the method comprising:
depositing a plurality of alternating first and second layers (12, 51) to form a stack (15), wherein the first layers (12) comprising a first material (e.g., silicon oxide – see paragraph [0055]) and the second layers (51) comprising a second material (e.g., silicon nitride – see paragraph [0055]);
forming a plurality of grooves (see, e.g., grooves 541 and 542 of annotated FIG. 1 herein, and FIGS. 8A-B) in the stack (15), wherein:
the grooves (541, 542) extend along a wordline direction (Y) of the 3D-NAND memory device (3); and
the grooves (541, 542) divide the second layers (51) into strips (see, e.g., FIG. 8A) extending along the wordline direction (Y);
depositing the first material (silicon oxide) in the grooves (541, 542) (see also., e.g., paragraph [0063] – “insulating member 17 is formed inside the trench 54 by depositing silicon oxide onto the entire surface”);
etching a plurality of channel holes (MH) in the stack (15), each channel hole (MH) overlapping one of the grooves (541, 542) and being wider than the one of the grooves (541, 542) in a bitline direction (X) orthogonal to the wordline direction (Y) (see also paragraph [0055]);
depositing a memory layer (21, 22, 26) and a channel layer (20) into the channel holes (MH) to form vertical NAND strings (see also paragraphs [0058]-[0060]);
after depositing the memory layer (21, 22, 26) and the channel layer (20), forming separation trenches (see, e.g., ST1, ST2 and ST3 of annotated FIG. 1 herein, and more generally ST) (see also, e.g., FIG. 11A and paragraph [0065] – note, the memory layer and channel layer are already deposited when the separation trenches ST are formed) on both sides (i.e., left side and right side) of each groove of the plurality of grooves (541, 542), wherein:
each groove of the plurality of grooves (541, 542) is separated from the other grooves of the plurality of grooves (541, 542) by at least one separation trench (ST2) (note, groove 541 is separated from groove 542 by the separation trench ST2 – moreover, insomuch as only grooves 541 and 542 are being read on the claimed plurality of grooves, then each groove (e.g., groove 541) of the plurality of grooves is separated from the other grooves (e.g., groove 542) of the plurality of grooves by at least one separation trench, namely, separation trench ST2); and
the separation trenches (ST1, ST2, ST3) extend along the wordline direction (Y) of the 3D-NAND memory device (1, 3) (see, e.g., FIG. 1); and
depositing the first material (silicon oxide) in the separation trenches (ST1, ST2, ST3) (see also, e.g., paragraph [0068] – “the insulating plate 16 is formed by filling silicon oxide into the slit ST”).
Note, as disclosed by Sakaike, each groove (54) has a trench (ST) formed on both sides of it. As disclosed by Sakaike, each groove (e.g., shown in FIG. 1 as being filled with insulating members 17) has a trench (ST) on its left side and a trench (ST) on its right side. Moreover, only one of the grooves (e.g., shown in FIG. 1 of Sakaike being filled with insulating members 17) in each of the fingers 13b is being read to comprise the claimed plurality of grooves. That is to say, with reference to FIG. 1 of Sakaike, the claimed plurality of groove is being read on by only one groove (541) from the leftmost finger 13b of Sakaike and only one groove (542) from the middle finger 13b of Sakaike. Accordingly, a trench (ST) is formed between and on both the left and right sides of each groove in the plurality grooves.
Regarding claim 22, Sakaike discloses:
the method of claim 21, wherein forming the plurality of grooves (541, 542) comprises defining a gap region (GR) between two adjacent grooves (541, 542) substantially in alignment along the wordline direction (Y) (see, e.g., annotated FIG. 1 herein, showing a gap region (GR) between two adjacent grooves (541, 542)).
Regarding claim 23, Sakaike discloses:
the method of claim 22, wherein the channel holes (MH) etched in the stack (15) are not overlapping the gap region (GR).
Regarding claim 24, Sakaike discloses the method of claim 22, further comprising:
etching the separation trenches (ST1, ST2, ST3, ST) in the stack (15);
selectively removing the second material (e.g., silicon nitride – see paragraph [0055]) of the second layers (51) from exposed sidewalls of the second layers (51) in the separation trenches (ST1, ST2, ST3, ST) (see also, e.g., paragraph [0066]);
depositing gate metal (13) into spaces revealed by the removed second material (e.g., silicon nitride – see paragraph [0055]), wherein the gap region (GR) provides a path for removing the second material (e.g., silicon nitride – see paragraph [0055]) and depositing the gate metal (13) (see also, e.g., paragraph [0067]);
removing materials left in the separation trenches (ST1, ST2, ST3, ST) (see also, e.g., paragraph [0068]); and
filling the separation trenches (ST1, ST2, ST3, ST) with a dielectric material (16) (see also, e.g., paragraph [0068]).
Regarding claim 25, Sakaike discloses:
the method of claim 21, further comprising: forming a staircase region (SCR) on at least one side (e.g., the upper side) of the stack (15), wherein the plurality of grooves (541, 542) extend into the staircase region (SCR).
Regarding claim 28, Sakaike discloses:
the method of claim 21, wherein the channel holes (MH) are arranged in a staggered manner. See, e.g., FIGS. 1 and 5A-B.
Note, that the elements 20p overlapping grooves 541 and 542 as shown in annotated FIG. 1 herein are arranged in a staggered manner and the elements 20p are formed in the memory holes (MH), e.g., as shown in FIGS. 5A-B. Accordingly, the memory holes (MH) corresponding to the element 20p overlapping grooves 541 and 542 are likewise arranged in a staggered manner.
Regarding claim 29, Sakaike discloses:
the method of claim 21, wherein the memory layer (21, 22, 26) comprises a charge storage layer (22), a blocking dielectric (26) between a channel hole (MH) sidewall and the charge storage layer (22), and a tunneling dielectric (21) between the charge storage layer (22) and the channel layer (20).
Regarding claim 31, Sakaike discloses:
the method of claim 29, wherein the charge storage layer (22) comprises floating gates (22a, 22b) (see, e.g., paragraph [0051]).
Regarding claim 32, Sakaike discloses:
the method of claim 31, wherein the channel layer (20) comprises polycrystalline silicon (see, e.g., paragraph [0037]).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 30 is rejected under 35 U.S.C. 103 as being unpatentable over Sakaike in view of Shin (US 20190027490 A1).
Regarding claim 30, Sakaike as applied to claim 29 discloses the method of claim 29.
Sakaike discloses that the charge storage layer (22) comprises floating gates (22a, 22b) (see, e.g., paragraph [0051]). Sakaike does not explicitly disclose wherein the charge storage layer comprises a charge trapping layer.
However, in analogous art, Shin discloses a charge storage layer (143) that comprises a charge trapping layer (see paragraph [0043]). Shin further discloses that the charge storage layer (143) may alternately comprise a floating gate layer or a charge trapping layer. See, e.g., paragraph [0043].
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have used a charge storage layer comprising a charge trapping layer as taught by Shin for the charge storage layer of Sakaike according to known methods to yield predictable results, for example, as a matter of simple substitution of a charge storage layer comprising a charge trapping layer for a charge storage layer comprising a floating gate layer. Note, Shin discloses that a charge storage layer comprising a floating gate layer is interchangeable with a charge storage layer comprising a charge trapping layer.
Claims 36-38, 41-42 and 44 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sakaike in view of Sharangpani (US 9230983 B1).
Regarding claim 36, Sakaike (see generally annotated FIG. 1 herein and FIGS. 2-12B) discloses:
a method of manufacturing a NAND string for a 3-dimensional NAND (3D-NAND) memory device (1), the method comprising:
providing a substrate (10);
depositing a plurality of alternating first and second layers (12, 51) to form a stack (15), wherein the first layers (12) comprise a first material (e.g., silicon oxide – see paragraph [0055]) and the second layers (51) comprise a second material (e.g., silicon nitride – see paragraph [0055]);
forming first and second grooves (541, 542) in the stack (15), wherein:
the first and second grooves (541, 542) extend along a wordline direction (Y) of the 3D-NAND memory device (1); and
the first and second grooves (541, 542) divide the second layers (51) into strips (see, e.g., FIG. 8A) extending along the wordline direction (Y);
depositing the first material (silicon oxide) in the first and second grooves (541, 542) (see also., e.g., paragraph [0063] – “insulating member 17 is formed inside the trench 54 by depositing silicon oxide onto the entire surface”);
etching first and second channel holes (MH) in the stack (15) to partially expose the substrate (10), wherein the first channel hole (MH) overlaps the first groove (541) and is wider than the first groove (541) in a bitline direction (X) orthogonal to the wordline direction (Y), and wherein the second channel hole (MH) overlaps the second groove (542) and is wider than the second groove (542) in the bitline direction (X); and
depositing a memory layer (21, 22, 26) and a channel layer (20) into the first and second channel holes (MH) to form the NAND string (see also paragraphs [0058]-[0060]);
after depositing the memory layer (21, 22, 26) and the channel layer (20), forming separation trenches (see, e.g., ST1, ST2 and ST3 of annotated FIG. 1 herein, and more generally ST) (see also, e.g., FIG. 11A and paragraph [0065] – note, the memory layer and channel layer are already deposited when the separation trenches ST are formed) on both sides (i.e., left side and right side) of each groove of the first and second grooves (541, 542), wherein:
the first grooves (541) is separated from the second groove (542) by at least one separation trench (ST2); and
the separation trenches (ST1, ST2, ST3) extend along the wordline direction (Y) of the 3D-NAND memory device (1) (see, e.g., FIG. 1); and
depositing the first material (silicon oxide) in the separation trenches (ST1, ST2, ST3) (see also, e.g., paragraph [0068] – “the insulating plate 16 is formed by filling silicon oxide into the slit ST”).
Note, as disclosed by Sakaike, each of the first and second grooves (541 and 542) has a trench (ST) formed on both sides of it. As disclosed by Sakaike, each of the first and second grooves (541 and 542) (e.g., shown in FIG. 1 as being filled with insulating members 17) has a trench (ST) on its left side and a trench (ST) on its right side. Moreover, only the grooves (541 and 542) are being read to comprise the claimed first and second grooves, respectively. Accordingly, a trench (ST) is formed between and on both the left and right sides of the first and second grooves (541 and 542).
Sakaike does not explicitly disclose the substrate having a pipe connection.
However, in analogous art, similar to the 3D NAND memory device (1) of Sakaike, Sharangpani (see generally, e.g., FIG. 2) discloses a U-shape NAND string (150) for a 3D-NAND memory device including a substrate (100) having a pipe connection (1c).
It would have been obvious to and well within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have exchanged the substrate (10) of Sakaike with the substrate (100) of Sharangpani and/or included the pipe connection (1c) of Sharangpani in the substrate (10) of Sakaike according to known methods to yield predictable results, e.g., in order to achieve a U-shaped NAND string for a 3D NAND memory device with desired properties and/or performance using materials and/or methods already known in the art which are suitable for the intended purpose and compatible with semiconductor manufacturing processes. Further, the U-shaped NAND string architecture allows both of the source/drain connections to be made from a top of the 3D NAND memory device. See, e.g., Sharangpani, column 3, lines 47-59. Additionally, Sharangpani further discloses vertical NAND strings (see, e.g., FIG. 1) and that U-shaped NAND strings (see, e.g., FIG. 2) are an alternative thereto. In particular, Sharangpani discloses that “[i]n some embodiments, the monolithic three dimensional NAND string 150 comprises a semiconductor channel 1 … extending substantially perpendicular to a major surface 100a of a substrate 100” (column 3, lines 33-36) and that “[a]lternatively, the semiconductor channel 1 may have a U-shaped pipe shape, as shown in FIG. 2” (column 3, lines 47-48). Accordingly, Sharangpani discloses the two architectures as interchangeable alternatives for one another.
Notably, when Sakaike is modified in accordance with the teachings of Sharangpani as discussed herein, Sakaike in view of Sharangpani discloses a method of manufacturing a U-shape NAND string for a 3-dimensional NAND (3D-NAND) memory device as claimed. Further, insomuch as Sakaike discloses etching the first and second channel holes (MH) in the stack (15) to partially expose the substrate (10), when modified in accordance with the teachings of Sharangpani to include a pipe connection in the substrate, Sakaike in view of Sharangpani discloses etching first and second channel holes in the stack to partially expose the pipe connection in the substrate as claimed.
Regarding claim 37, Sakaike in view of Sharangpani, as applied to claim 36 above, discloses:
the method of claim 36, further comprising (see generally annotated FIG. 1 of Sakaike herein):
etching first, second, and third separation trenches (ST1, ST2, ST3) in the stack (15), wherein the first groove (541) is located between the first and second separation trenches (ST1, ST2), the second separation trench (ST2) is located between the first and second grooves (541, 542), and the second groove (542) located between the second and third separation trenches (ST2, ST3); and
filling the first and second separation trenches (ST1, ST2) with a dielectric material (16).
Regarding claim 38, Sakaike in view of Sharangpani, as applied to claim 36 above, discloses:
the method of claim 36, further comprising (see generally annotated FIG. 1 of Sakaike herein):
forming a staircase region (SCR) on at least one side of the stack (15), wherein the first and second grooves (541, 542) extend into the staircase region (SCR).
Regarding claim 41, Sakaike in view of Sharangpani, as applied to claim 36 above, discloses the method of claim 36.
Sakaike further discloses wherein the first material is silicon oxide (see, e.g., paragraph [0055]).
Regarding claim 42, Sakaike in view of Sharangpani, as applied to claim 36 above, discloses the method of claim 36.
Sakaike further discloses wherein the memory layer (21, 22, 26) comprises a charge storage layer (22), a blocking dielectric (26) between the second material and the charge storage layer (22), and a tunneling dielectric (21) between the charge storage layer (22) and the channel layer (20) (see, e.g., FIGS. 3 and 4 and paragraphs [0051], [0059] and [0060]).
Regarding claim 44, Sakaike in view of Sharangpani, as applied to claim 42 above, discloses the method of claim 42.
Sakaike further discloses wherein the charge storage layer (22) comprises floating gates (22a, 22b) (see, e.g., paragraph [0051]).
Claim 40 is rejected under 35 U.S.C. 103 as being unpatentable over Sakaike in view of Sharangpani as applied to claim 36 above, and further in view of Chien (US 9165940 B2).
Regarding claim 40, Sakaike in view of Sharangpani as applied to claim 36 discloses the method of claim 36.
Sakaike further discloses that the second material is tungsten (see, e.g., paragraph [0067]). Note, the second layers (51) (e.g., shown in FIGS. 8A-B) are replaced with electrode layers (13) (e.g., shown in FIGS. 12A-B).
Sakaike does not explicitly disclose that the second material is doped polysilicon.
However, in analogous art, Chien discloses a 3D NAND memory device in which the conductive layer, i.e., control gate electrode (3), of an alternating insulating/conductive stack (2, 3) is doped polysilicon. Chien further discloses that tungsten and doped polysilicon are interchangeable materials known in the art to be suitable control gate materials. See, e.g., column 3, line 59 through column 4, line 9 – “The control gate material may comprise any one or more suitable conductive or semiconductor control gate material known in the art, such as doped polysilicon, tungsten, copper, aluminum, tantalum, titanium, cobalt, titanium nitride or alloys thereof.”
It would have been obvious to and well within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have exchanged the tungsten material of the second layer (51, 13) of Sakaike with doped polysilicon as taught by Chien according to known methods to yield predictable results, e.g., in order to achieve a second layer with desired properties and/or performance using a material known in the art which is suitable for the intended purpose and compatible with semiconductor manufacturing processes.
Claim 43 is rejected under 35 U.S.C. 103 as being unpatentable over Sakaike in view of Sharangpani as applied to claim 42 above, and further in view of Shin.
Regarding claim 43, Sakaike in view of Sharangpani, as applied to claim 42 above, discloses the method of claim 42.
Sakaike discloses that the charge storage layer (22) comprises floating gates (22a, 22b) (see, e.g., paragraph [0051]). Sakaike does not explicitly disclose wherein the charge storage layer comprises a charge trapping layer.
However, in analogous art, Shin discloses a charge storage layer (143) that comprises a charge trapping layer (see paragraph [0043]). Shin further discloses that the charge storage layer (143) may alternately comprise a floating gate layer or a charge trapping layer. See, e.g., paragraph [0043].
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have used a charge storage layer comprising a charge trapping layer as taught by Shin for the charge storage layer of Sakaike according to known methods to yield predictable results, for example, as a matter of simple substitution of a charge storage layer comprising a charge trapping layer for a charge storage layer comprising a floating gate layer. Note, Shin discloses that a charge storage layer comprising a floating gate layer is interchangeable with a charge storage layer comprising a charge trapping layer.
Conclusion
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JOHN P. CORNELY
Examiner
Art Unit 2812
/J.P.C./Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812