DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on March 23, 2026 has been entered.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
Regarding claim 6. Claim 6 recites the limitations “the first gate structure and the second gate structure are arranged along a first direction in a top view such that respective long sides thereof extend in alignment, and respective short sides thereof are spaced apart from each other”, “a third gate structure disposed at one long side of the first gate structure”, “a fourth gate structure disposed at an opposite long side of the first gate structure relative to the third gate structure in top view”, and “wherein the first portion of the silicide layer is disposed adjacent to the one long side of the first gate structure, and the second portion of the silicide layer is disposed adjacent to the opposite long side of the first gate structure” in the claim language.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Ching et al (U.S. 2010/0265755), Toh et al (U.S. 2019/0280108), and Chuang et al (U.S. 2017/0317074).
Regarding claim 6. Ching et al discloses an one time programmable (OTP) memory device (FIG. 6A/6B), comprising:
a first shallow trench isolation (STI) (FIG. 6B, item 120 on left) and a second STI (FIG. 6B, item 120 on right) in a substrate (FIG. 6B, item 100);
a first gate structure (FIG. 6A/6B, item 142a) disposed on the first STI (FIG. 6B, item 120 on left) and the substrate (FIG. 6B, item 100); and
a second gate structure (FIG. 6A/6B, item 142b) disposed on the second STI (FIG. 6B, item 120 on right) and the substrate (FIG. 6B, item 100), wherein the first gate structure (FIG. 6A/6B, item 142a) and the second gate structure (FIG. 6A/6B, item 142b) are arranged along a first direction (FIG. 6A) in a top view (FIG. 6A) such that respective long sides (FIG. 6A/6B, item 142a/142b cross section B) thereof extend in alignment (FIG. 6A/6B, item cross section B), and respective short sides (FIG. 6A/6B, item 124a; [0072]) thereof are spaced apart (FIG. 6A/6B, item 124a) from each other ([0072]), and no silicide layer (FIG. 6A, item 108a; [0077] i.e. Referring to FIGS. 6A and 6B, the silicide-blocking structure 140 further includes a silicide blocking layer 108a. The silicide blocking layer 108a is disposed on the substrate 100, and the silicide-blocking structure 140 is surrounded by the silicide blocking layer 108a) is disposed between the respective short sides (FIG. 6A, item 124a) the first gate structure (FIG. 6B, item 142a) and the second gate structure (FIG. 6A/6B, item 142b),
an interlayer dielectric (ILD) layer (FIG. 6A/6B, item 108a; [0077], i.e. Referring to FIGS. 6A and 6B, the silicide-blocking structure 140 further includes a silicide blocking layer 108a; [0068], i.e. The silicide blocking layer 108 is, for example, made of silicon oxide) between the first gate structure (FIG. 6A/6B, item 142a) and the second gate structure (FIG. 6A/6B, item 142b).
a third gate structure (FIG. 6A, item 110) extending along the first direction in the top view (FIG. 6A), and disposed at one long side of the first gate structure (FIG. 6A, item 142a);
a silicide layer (FIG. 6A/6B, item 122) having a first portion (FIG. 6A/6B, item 122b) disposed between the first gate structure (FIG. 6A/6B, item 142a) and the third gate structure (FIG. 6A, item 110),
and a second portion (FIG. 6A/6B, item 122c)
wherein a sidewall of the first portion (FIG. 6A, item 122b) of the silicide layer (FIG. 6A, item 122) abutting (FIG. 6A/6B, item 108a; [0077], as best understood by the 112b above) the one long side ([0076], [0070], [0063]) of the first gate structure (FIG. 6A/6B, item 142a), and a sidewall of the second portion (FIG. 6A/6B, item 122c) of the silicide layer (FIG. 6A/6B, item 122) abutting (FIG. 6A/6B, item 108a; [0077], as best understood by the 112b above) the opposite long side ([0076], [0070], [0063]) of the first gate structure (FIG. 6A/6B, item 142a)
Ching et al fails to explicitly disclose a fourth gate structure extending along the first direction in the top view, and is posed at an opposite long side of the first gate structure relative to the third gate structure in the top view; a portion disposed between the first gate structure and the fourth gate structure, a gate dielectric on the substrate and extending from the first gate structure to the second gate structure; an interlayer dielectric on the gate dielectric layer, wherein the gate dielectric layer between the first gate structure and the second gate structure and directly under the ILD layer contacts the substrate directly.
However, Toh et al teaches a fourth gate structure (annotated FIG. 5, item fourth gate structure) extending along the first direction (annotated FIG. 5, item first direction) in the top view (annotated FIG. 5, item top view), and is posed at an opposite long side ([0028]) of the first gate structure (annotated FIG. 5, item first gate structure) relative (annotated FIG. 5, item first gate structure) to the third gate structure (annotated FIG. 5, item third gate structure) in the top view (annotated FIG. 5, item top view); a portion (annotated FIG. 5, item 501) disposed between ([0028]) the first gate structure (annotated FIG. 5, item first gate structure) and the fourth gate structure (annotated FIG. 5, item fourth gate structure)
PNG
media_image1.png
518
698
media_image1.png
Greyscale
Since Both Ching et al and Toh et al teach One Time Programmable memory, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the OTP memory device as disclosed to modify Ching et al with the teachings of the fourth gate structure extending along the first direction in the top view, and is posed at an opposite long side of the first gate structure relative to the third gate structure in the top view, a portion disposed between the first gate structure and the fourth gate structure as disclosed by Toh et al. The use of a third gate structure and a fourth gate structure in Toh et al provides for forming an OTP/MTP on FDSOI or FinFET architecture that can alleviate program disturb while realizing a compact cell size greater than 50% smaller than known designs, e.g., a 20-30 feature size squared (F.sup.2) versus 47-50 F.sup.2 (28 nm OTP) or 298 F.sup.2 (16 nm MTP), without requiring any additional masks, i.e., at a low cost (Toh et al, [0037]).
Ching et al and Toh et al fail to explicitly disclose a gate dielectric on the substrate and extending from the first gate structure to the second gate structure; an interlayer dielectric on the gate dielectric layer, wherein the gate dielectric layer between the first gate structure and the second gate structure and directly under the ILD layer contacts the substrate directly.
However, Chuang et al teaches a gate dielectric layer (FIG. 21, item 217) on the substrate (FIG. 21, item 202) and extending (Claim 1, i.e. a first gate structure adjacent the source/drain region, a first floating gate over the first dielectric layer and the first dielectric layer extends across a top surface of the source/drain region; Claim 5, i.e. a second gate structure, wherein: the source/drain region is between the first gate structure and the second gate structure) from the first gate structure (FIG. 21, item 228a) to the second gate structure (FIG. 21, item 228b); an interlayer dielectric (FIG. 21, item 246) on the gate dielectric layer (FIG. 21, item 217), wherein the gate dielectric layer between (Claim 1, i.e. a first gate structure adjacent the source/drain region, a first floating gate over the first dielectric layer and the first dielectric layer extends across a top surface of the source/drain region; Claim 5, i.e. a second gate structure, wherein: the source/drain region is between the first gate structure and the second gate structure) the first gate structure (FIG. 21, item 228a) and the second gate structure (FIG. 21, item 228b) and directly under the ILD layer (FIG. 21, item 246) contacts (FIG. 21, item 242 of item 202) the substrate (FIG. 21, item 242 of item 202) directly ([0032], i.e. that the deep implant 208 is merely formed within the substrate 202 at that location; [0036], i.e. a shallow implant 242 is formed in top portions 209 of the deep implant 208).
Since Ching et al, Toh et al, and Chuang et al teach gate structures, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the one time programmable (OTP) memory device as disclosed to modify Ching et al and Toh et al with the teachings of the semiconductor device as disclosed by Chuang et al. The use of a first gate structure adjacent the source/drain region, a first floating gate over the first dielectric layer and the first dielectric layer extends across a top surface of the source/drain region, a second gate structure, wherein: the source/drain region is between the first gate structure and the second gate structure in Chuang et al provides for forming the deep implant prior to forming the first gate structure alleviates the need for an etching process that degrades the first gate structure. The first gate structure thus has a desired configuration and is able to be formed closer to other gate structures to enhance device density (Chuang et al, Abstract).
Response to Arguments
Applicant's arguments filed March 23, 2026 have been fully considered but they are not persuasive.
Regarding rejection of claims 6 with Ching et al, Toh et al and Chuang et al. Applicant argues on page 7 that Toh provides no motivation to combine with Ching et al.
Examiner respectfully disagrees. In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, since both Ching et al and Toh et al teach one time programmable memory, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the OTP memory device as disclosed to modify Ching et al with the teachings of the fourth gate structure extending along the first direction in the top view, and is posed at an opposite long side of the first gate structure relative to the third gate structure in the top view, a portion disposed between the first gate structure and the fourth gate structure as disclosed by Toh et al. The use of a third gate structure and a fourth gate structure in Toh et al provides for forming an OTP/MTP on FDSOI or FinFET architecture that can alleviate program disturb while realizing a compact cell size greater than 50% smaller than known designs, e.g., a 20-30 feature size squared (F.sup.2) versus 47-50 F.sup.2 (28 nm OTP) or 298 F.sup.2 (16 nm MTP), without requiring any additional masks, i.e., at a low cost (Toh et al, [0037]).
On page 8, applicant appears to argue impermissible hindsight reconstruction rather than on a teaching or rational found in the prior art.
Examiner respectfully disagrees with applicant’s assertion. In response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
In response to applicant's argument in page 8 that to modify Ching by “replacing” the inter-gate region between 142a and 142b with Chuang’s continuous gate dielectric plus ILD would necessarily remove or fundamentally alter Ching’s silicide blocking layer, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
Here, Ching et al, Toh et al, and Chuang et al teach gate structures. Furthermore, Ching et al discloses the blocking layer is silicon oxide ([0063]) and Chuang’s gate oxide is silicon oxide ([0034]). It is unclear to the examiner how Chuang et al silicon oxide breaks the silicon oxide of Ching et al device. "Products of identical chemical composition cannot have mutually exclusive properties." In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990). MPEP 2112.01 II. Furthermore, Ching et al discloses the ILD, and Chuang et al teaches the gate dielectric layer on the substrate and extending from the first gate structure to the second gate structure. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
On page 9, applicant appears to be arguing against the source/drains of the prior art and their interoperability.
Examiner respectfully points, that applicant has not claimed any source/drains nor how they interact with each other. Applicant has not disclosed any circuit operation of applicant’s structure. Applicant appears to be only claiming the structure of a device, but arguing against the functionality and operation of the prior art. The prior art of record discloses applicant’s claimed structure.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chen et al (U.S. 2014/0098591) antifuse OTP memory cell.
Kurjanowicz (U.S. 9129687) discloses an OTP memory cell.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SCOTT E BAUMAN whose telephone number is (469)295-9045. The examiner can normally be reached M-F, 9-5 CST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/S.E.B./ Examiner, Art Unit 2815 /JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815
Prosecution Insights