DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Ching et al (U.S. 2010/0265755), Toh et al (U.S. 2019/0280108), and Chuang et al (U.S. 2017/0317074).
Regarding claim 6. Ching et al discloses an one time programmable (OTP) memory device (FIG. 6A/6B), comprising:
a first shallow trench isolation (STI) (FIG. 6B, item 120 on left) and a second STI (FIG. 6B, item 120 on right) in a substrate (FIG. 6B, item 100);
a first gate structure (FIG. 6A/6B, item 142a) disposed on the first STI (FIG. 6B, item 120 on left) and the substrate (FIG. 6B, item 100); and
a second gate structure (FIG. 6A/6B, item 142b) disposed on the second STI (FIG. 6B, item 120 on right) and the substrate (FIG. 6B, item 100), wherein the first gate structure (FIG. 6A/6B, item 142a) and the second gate structure (FIG. 6A/6B, item 142b) are arranged along a first direction (FIG. 6A) in a top view (FIG. 6A) such that
a first long side (FIG. 6A/6B, left side of item 142a) of the first gate structure (FIG. 6A/6B, item 142a) and a second long side (FIG. 6A/6B, left side of item 142b) of the second gate structure (FIG. 6A/6B, item 142b) extend in alignment along the first direction, a third long side (FIG. 6A/6B, right side of item 142a) of the first gate structure (FIG. 6A/6B, item 142a) and a fourth long side (FIG. 6A/6B, right side of item 142b) of the second gate structure (FIG. 6A/6B, item 142b) extend in alignment along the first direction, wherein the first long side (FIG. 6A/6B, left side of item 142a) and the third (FIG. 6A/6B, right side of item 142a) long side are on opposite sides (FIG. 6A/6B, left and right sides of item 142a) of the first gate structure (FIG. 6A/6B, item 142a), and the second long side (FIG. 6A/6B, left side of item 142b) and the fourth long side (FIG. 6A/6B, right side of item 142b) are on opposite sides (FIG. 6A/6B, left and right sides of item 142b) of the second gate structure (FIG. 6A/6B, item 142b), a first short side (FIG. 6A/6B, item 124a; [0072]; FIG. 6A/6B, bottom side of item 142a) of the first gate structure (FIG. 6A/6B, item 142a) and a second short side (FIG. 6A/6B, item 124a; [0072]; FIG. 6A/6B, top side of item 142a) of the second gate structure (FIG. 6A/6B, of item 142b) are opposite (FIG. 6A/6B, item 124a; [0072]) to and spaced apart (FIG. 6A/6B, item 124a) from each other (FIG. 6A/6B, the top and bottom sides of item 142a/142b are spaced apart from each other), and no silicide layer (FIG. 6A, item 108a; [0077] i.e. Referring to FIGS. 6A and 6B, the silicide-blocking structure 140 further includes a silicide blocking layer 108a. The silicide blocking layer 108a is disposed on the substrate 100, and the silicide-blocking structure 140 is surrounded by the silicide blocking layer 108a) is disposed between (FIG. 6A, item 108a) the first (FIG. 6A/6B, item 124a; [0072]; FIG. 6A/6B, bottom side of item 142a) and second (FIG. 6A/6B, item 124a; [0072]; FIG. 6A/6B, top side of item 142a) short sides (FIG. 6A/6B, item 124a) the first gate structure (FIG. 6B, item 142a) and the second gate structure (FIG. 6A/6B, item 142b),
a third gate structure (FIG. 6A, item 110) extending along the first direction in the top view (FIG. 6A), and disposed at the first long side (FIG. 6A/6B, left side of item 142a)of the first gate structure (FIG. 6A, item 142a);
an interlayer dielectric (ILD) layer (FIG. 6A/6B, item 108a; [0077], i.e. Referring to FIGS. 6A and 6B, the silicide-blocking structure 140 further includes a silicide blocking layer 108a; [0068], i.e. The silicide blocking layer 108 is, for example, made of silicon oxide) between the first gate structure (FIG. 6A/6B, item 142a) and the second gate structure (FIG. 6A/6B, item 142b).
a silicide layer (FIG. 6A/6B, item 122) having a first portion (FIG. 6A/6B, item 122b) disposed between the first gate structure (FIG. 6A/6B, item 142a) and the third gate structure (FIG. 6A, item 110),
and a second portion (FIG. 6A/6B, item 122c)
wherein the first portion (FIG. 6A, item 122b) of the silicide layer (FIG. 6A, item 122) is disposed adjacent the first long side (FIG. 6A/6B, left side of item 142a) of the first gate structure (FIG. 6A/6B, item 142a), and the second portion (FIG. 6A/6B, item 122c) of the silicide layer (FIG. 6A/6B, item 122) is disposed adjacent to the third long side ((FIG. 6A/6B, right side of item 142a) [0076]) of the first gate structure (FIG. 6A/6B, item 142a)
Ching et al fails to explicitly disclose a fourth gate structure extending along the first direction in the top view, and disposed at the third long side of the first gate structure in top view;
a portion disposed between the first gate structure and the fourth gate structure,
a gate dielectric on the substrate and extending from the first gate structure to the second gate structure;
an interlayer dielectric on the gate dielectric layer, wherein the gate dielectric layer between the first gate structure and the second gate structure and directly under the ILD layer contacts the substrate directly.
However, Toh et al teaches a fourth gate structure (annotated FIG. 5, item fourth gate structure) extending along the first direction (annotated FIG. 5, item first direction) in the top view (annotated FIG. 5, item top view), and disposed at the third long side (annotated FIG. 5, right side item first gate structure) ([0028]) of the first gate structure (annotated FIG. 5, item first gate structure) in the top view (annotated FIG. 5, item top view); a portion (FIG. 5, item 501) disposed between ([0028]) the first gate structure (annotated FIG. 5, item first gate structure) and the fourth gate structure (annotated FIG. 5, item fourth gate structure)
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Since Both Ching et al and Toh et al teach One Time Programmable memory, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the OTP memory device as disclosed to modify Ching et al with the teachings of a fourth gate structure extending along the first direction in the top view, and disposed at the third long side of the first gate structure in top view a portion disposed between the first gate structure and the fourth gate structure as disclosed by Toh et al. The use of a third gate structure and a fourth gate structure in Toh et al provides for forming an OTP/MTP on FDSOI or FinFET architecture that can alleviate program disturb while realizing a compact cell size greater than 50% smaller than known designs, e.g., a 20-30 feature size squared (F.sup.2) versus 47-50 F.sup.2 (28 nm OTP) or 298 F.sup.2 (16 nm MTP), without requiring any additional masks, i.e., at a low cost (Toh et al, [0037]).
Ching et al and Toh et al fail to explicitly disclose a gate dielectric on the substrate and extending from the first gate structure to the second gate structure; an interlayer dielectric on the gate dielectric layer, wherein the gate dielectric layer between the first gate structure and the second gate structure and directly under the ILD layer contacts the substrate directly.
However, Chuang et al teaches a gate dielectric layer (FIG. 21, item 217) on the substrate (FIG. 21, item 202) and extending (Claim 1, i.e. a first gate structure adjacent the source/drain region, a first floating gate over the first dielectric layer and the first dielectric layer extends across a top surface of the source/drain region; Claim 5, i.e. a second gate structure, wherein: the source/drain region is between the first gate structure and the second gate structure) from the first gate structure (FIG. 21, item 228a) to the second gate structure (FIG. 21, item 228b); an interlayer dielectric (FIG. 21, item 246) on the gate dielectric layer (FIG. 21, item 217), wherein the gate dielectric layer between (Claim 1, i.e. a first gate structure adjacent the source/drain region, a first floating gate over the first dielectric layer and the first dielectric layer extends across a top surface of the source/drain region; Claim 5, i.e. a second gate structure, wherein: the source/drain region is between the first gate structure and the second gate structure) the first gate structure (FIG. 21, item 228a) and the second gate structure (FIG. 21, item 228b) and directly under the ILD layer (FIG. 21, item 246) contacts (FIG. 21, item 242 of item 202) the substrate (FIG. 21, item 242 of item 202) directly ([0032], i.e. that the deep implant 208 is merely formed within the substrate 202 at that location; [0036], i.e. a shallow implant 242 is formed in top portions 209 of the deep implant 208).
Since Ching et al, Toh et al, and Chuang et al teach gate structures, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the one time programmable (OTP) memory device as disclosed to modify Ching et al and Toh et al with the teachings of the semiconductor device as disclosed by Chuang et al. The use of a first gate structure adjacent the source/drain region, a first floating gate over the first dielectric layer and the first dielectric layer extends across a top surface of the source/drain region, a second gate structure, wherein: the source/drain region is between the first gate structure and the second gate structure in Chuang et al provides for forming the deep implant prior to forming the first gate structure alleviates the need for an etching process that degrades the first gate structure. The first gate structure thus has a desired configuration and is able to be formed closer to other gate structures to enhance device density (Chuang et al, Abstract).
Response to Arguments
Applicant's arguments filed July 21, 2026 have been fully considered but they are not persuasive.
Regarding rejection of claims 6 with Ching et al, Toh et al and Chuang et al.
On page 9 of applicant’s remarks, applicant appears to that argue that Ching does not disclose active gate lines of a memory array connected to external voltage sources.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., active gate lines of a memory array connected to external voltage sources) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
On page 9 of applicant’s remarks, applicant appears to argue that Toh’s does not disclose nor suggest a split-gate silicide-blocking configuration having opposing short sides separated by a silicide-free gap.
Examiner respectfully points out that Toh was not used to disclose applicant’s amended claim limitation, and that Ching disclose applicant’s amended claim limitations. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
On page 10 of applicant’s remarks, appears to argue that there is no motivation for the combination of Ching and Toh
Examiner respectfully disagrees. In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, since both Ching et al and Toh et al teach one time programmable memory, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention.
On page 11 of applicant’s remarks applicant appears argue that there is no motivation for the combination of Ching and Chaung to teach the structure of applicant’s amended claim 6.
Examiner respectfully disagrees with applicant’s assertion. Examiner respectfully points out that Ching et al, Toh, and Chaung et al in combination teaches applicant’s amended claim 6. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
On page 12 of applicant’s remarks, applicant appears to argue that individually Ching et al, Toh, and Chuang et al fails to disclose applicant’s amended claim 6.
Examiner respectfully points out that Ching et al, Toh, and Chaung et al in combination teaches applicant’s amended claim 6. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
On page 12 of applicant’s remarks, applicant appears to argue that there is no motivation to combine the Ching et al, Toh, and Chuang et al references.
In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, Since Ching et al, Toh et al, and Chuang et al teach gate structures, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chen et al (U.S. 2014/0098591) antifuse OTP memory cell.
Kurjanowicz (U.S. 9129687) discloses an OTP memory cell.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
/S.E.B./ Examiner, Art Unit 2815 /JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815
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