DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections – 356 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 and 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over .
Sadie, J.A. and Subramanian, V. (2014), Three-Dimensional Inkjet-Printed Interconnects using Functional Metallic Nanoparticle Inks. Adv. Funct. Mater., 24: 6834-6842, hereinafter referred to as Sadie, in view of Crocker et. al. (US Pub. No. 20040175631) and further in view of Wachtler et. al. (US20170309549A1)
Regarding claim 1, Sadie teaches, a three-dimensionally printed flip chip interconnect that includes an electrically conductive ink material (Abstract, 2.1 Printing Process, therefore the electrically conducive ink material is comparable with 3D a printing technology). Sadie teaches that three-dimensionally printed flip chip interconnects are suitable for use as vertical interconnects in semiconductor packaging applications, (Section 3. Conclusion) but does not explicitly state , the three-dimensionally printed flip chip interconnect configured to be connected to a chip pad of a printed circuit board, the three-dimensionally printed flip chip interconnect configured to be positioned between the metal surface of the semiconductor chip and the chip pad of the printed circuit board when the semiconductor chip is flipped and connected to the printed circuit board to form a flip chip assembly.
Sadie does not appear to disclose that the 3D printing technology prints by moving muti-directionally along a printing direction in a two-dimensional plane and in multiple layers to deposit the electrically conductive ink material on a metal surface of a semiconductor chip or the interconnect being connected to a chip pad on a PCB.
The applicant is claiming the product of semiconductor device including a method (i.e. a process) of “moving muti-directionally along a printing direction in a two-dimensional plane” consequently, claim 1 is considered “product-by-process” claim. In spite of the fact that the product-by-process claim may recite only process limitations, it is the product and not the recited process that is covered by the claim. Further, patentability of a claim to a product does not rest merely on the difference in the method by which the product is made. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior art product was made by a different process.
Furthermore, it is well established that a claimed apparatus cannot be distinguished over the prior art by a process limitation. Consequently, absent a showing of an unobvious difference between the claimed product and the prior art, the subject product-by-process claim limitation is not afforded patentable weight (see MPEP 2113).
However, Crocker teaches a conductive ink material (para. 323) that is compatible with a three-dimensional printing technology that prints by moving muti-directionally along a printing direction in a two-dimensional plane (para. 124) and in multiple layers (para. 149) to deposit the electrically conductive ink material on a metal surface (para. 084) of a semiconductor chip.
It would have been obvious to one of ordinary skill in the art, prior to the filing date of the application, to use the moving multi-directional process of Crocker to form metal patterns of various shapes.
Wachtler teaches forming a flip chip interconnect (Wachtler, Fig. 7, 704) on a metal pad (Wachtler, Fig. 7, 703) on a chip surface (Wachtler, Fig. 7, 702 para. 47-48).
It would have been obvious to one of ordinary skill in the art, prior to the filing date of the application, to use the conductive ink and method of Crocker with the structure of Wachtler in order to create a metal-to-metal connection that results in a bond that increases the maximum current allowed in a flip chip package, improves joint cracking that has resulted from brittle Pb-free solder, and prevents solder voiding during assembly and reliability stress (Watchler: par 17).
Regarding claim 2, modified Sadie teaches the semiconductor device of claim 1, wherein the three-dimensional printing technology is a direct write printing technology, an inkjet printing technology, or an aerosol jet printing technology (Crocker, Para. 11).
Regarding claim 3, modified Sadie teaches the semiconductor device of claim 1, wherein the electrically conductive ink material comprises at least one member selected from the group consisting of gold, aluminum, copper, tantalum, cobalt, ruthenium, titanium, tin, silver, solder, or an alloy thereof (Crocker, para. 133).
Regarding claim 5, modified Sadie teaches the semiconductor device of claim 1, wherein the metal surface is a chip pad comprising at least one metal selected from the group consisting of gold, aluminum, copper, tungsten, tantalum, silver, and palladium (Crocker, para. 084).
Regarding claim 7, modified Sadie teaches the semiconductor device of claim 1, wherein the three-dimensionally printed flip chip interconnect further includes a second electrically conductive ink material that is also compatible with the three-dimensional printing technology (Crocker, para. 350).
Claims 4, 8 and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Sadie, Crocker and Wachtler, and further in view of Gratson et. al. (US Pub. 20070228335) hereinafter referred to as Gratson.
Regarding claim 4, modified Sadie teaches the semiconductor device of claim 3, but fail to teach wherein the three- dimensionally printed flip chip interconnect has a cylindrical shape.
However, Gratson teaches a microscale printing technique wherein the printed features have tight and broad angles (Gratson, Fig 3C).
It would have been obvious to one having ordinary skill in the art prior to the filing date of the invention to combine the 3D printed flip chip of modified Sadie with the techniques of Gratson to create an interconnect with a cylindrical shape.
PNG
media_image1.png
505
736
media_image1.png
Greyscale
Regarding claim 8, modified Sadie teaches the semiconductor device of claim 1, but fail to teach wherein a distal end of the three-dimensionally printed flip chip interconnect positioned on the metal surface of the semiconductor chip has a polygon shaped surface.
However, Gratson teaches a microscale printing technique wherein the printed features have tight and broad angles (Gratson, Fig 3C).
It would have been obvious to one having ordinary skill in the art prior to the filing date of the invention to combine the 3D printed flip chip of modified Sadie with the techniques of Gratson to create an interconnect with a cylindrical shape.
PNG
media_image2.png
505
736
media_image2.png
Greyscale
Regarding claim 21, modified Sadie teaches the semiconductor device of claim 1, but does not teach wherein the printing direction is defined by a geometry of a distal end of the three-dimensionally printed flip chip interconnect.
However, Gratson describes a microscale printing technique wherein the micropositioner moves to form a two-dimensional pattern on the substrate (Gratson, Para. 14).
It would have been obvious to one having ordinary skill in the art prior to the filing date of the invention to combine the 3D printed flip chip of modified Sadie with the techniques of Gratson such that the printing direction is defined by a geometry of a distal end of the three-dimensionally printed flip chip interconnect.
Regarding claim 22, modified Sadie teaches the semiconductor device of claim 8, wherein the micropositioner moves to form a two-dimensional pattern on the substrate (Gratson, Para. 14).
It would have been obvious to one having ordinary skill in the art prior to the filing date of the invention to further combine the 3D printed flip chip of modified Sadie with the techniques of Gratson such that wherein the printing direction is defined by the polygon shaped surface.
Response to arguments
Applicant’s arguments with respect to claim(s) 1-8 have been considered but are moot because of the new ground of rejection.
Regarding claim 1, Crocker teaches a printing technology that moves along a printing direction in a two-dimensional plane.
Regarding claim 8, Gratson teaches a polygon shape interconnect.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIERAN M CUNNINGHAM whose telephone number is (571)272-9654. The examiner can normally be reached Mon-Fri 7:30-5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 5712703042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KIERAN M. CUNNINGHAM/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893