Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections 35 U.S.C.§ 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-8 and 23-27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shim et al. (US Pub. 20170358546), hereinafter known as Shim, Sadie, J.A. and Subramanian, V. (2014), Three-Dimensional Inkjet-Printed Interconnects using Functional Metallic Nanoparticle Inks. Adv. Funct. Mater., 24: 6834-6842. https://doi.org/10.1002/adfm.201401312, hereinafter known as Sadie and Crocker et. al. (US Pub. 20040175631), hereinafter known as Crocker.
Regarding claim 1, Shim teaches semiconductor device, comprising: a semiconductor substrate (Shim, 10, Figs. 3(a), 3(b), para. 47); a semiconductor chip positioned on the semiconductor substrate (Shim teaches a flip chip die assembly that constitutes the claimed semiconductor chip, comprising the substrate 10 and active elements), the semiconductor chip including a metal surface (Shim, 50, Figs. 3(a), 3(b), para. 47) opposite the semiconductor substrate; at least one intermediary layer (Shim, 20, Figs. 3a, 3(b), para. 50) positioned on the semiconductor substrate and at least partially on the metal surface; and a flip chip interconnect (Shim, 60, Figs. 3(a) 3(b), para. 47) and wherein the flip chip interconnect configured to be connected to a chip pad of a printed circuit board, the flip chip interconnect configured to be positioned between the metal surface of the semiconductor chip and the chip pad of the printed circuit board when the semiconductor chip is flipped and connected to the printed circuit board to form a flip chip assembly (Shim, paras. 3-6).
Shim does not teach wherein the flip-chip interconnect is three-dimensionally printed, or wherein an electrically conductive ink material that is compatible with a three-dimensional printing technology that prints by moving multi-directionally along a printing direction in a two-dimensional plane and in multiple layers to deposit the electrically conductive ink material on a metal surface of a semiconductor chip,
However, Sadie teaches, a three-dimensionally printed flip chip interconnect that includes an electrically conductive ink material (Abstract, 2.1 Printing Process, therefore the electrically conducive ink material is comparable with 3D a printing technology). Sadie teaches that three-dimensionally printed flip chip interconnects are suitable for use as vertical interconnects in semiconductor packaging applications, (Section 3. Conclusion).
Therefore it would have been obvious to one having ordinary skill in the art to combine the flip chip of Shim with the printed interconnect of Sadie to achieve pillars with properties comparable to bulk gold while saving costs (Sadie, abstract).
Neither Sadie nor Shim appear to disclose that the 3D printing technology prints by moving muti-directionally along a printing direction in a two-dimensional plane and in multiple layers to deposit the electrically conductive ink material on a metal surface of a semiconductor chip or the interconnect being connected to a chip pad on a PCB. The applicant is claiming the product of semiconductor device including a method (i.e. a process) of “moving muti-directionally along a printing direction in a two-dimensional plane” consequently, claim 1 is considered “product-by-process” claim. In spite of the fact that the product-by-process claim may recite only process limitations, it is the product and not the recited process that is covered by the claim. Further, patentability of a claim to a product does not rest merely on the difference in the method by which the product is made. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior art product was made by a different process. Furthermore, it is well established that a claimed apparatus cannot be distinguished over the prior art by a process limitation. Consequently, absent a showing of an unobvious difference between the claimed product and the prior art, the subject product-by-process claim limitation is not afforded patentable weight (see MPEP 2113).
However, Crocker teaches a conductive ink material (para. 323) that is compatible with
a three-dimensional printing technology that prints by moving muti-directionally along a printing direction in a two-dimensional plane (para. 124) and in multiple layers (para. 149) to deposit the electrically conductive ink material on a metal surface (para. 084) of a semiconductor chip. Therefore it would have been obvious to one of ordinary skill in the art, prior to the filing date of
the application, to use the moving multi-directional process of Crocker to form metal patterns
of various shapes.
Regarding claim 2, modified Shim teaches the semiconductor device of claim 1, wherein the three-dimensional printing technology is a direct write printing technology, an inkjet printing technology, or an aerosol jet printing technology (Crocker, para. 11).
Regarding claim 3, modified Shim teaches the semiconductor device of claim 1, wherein the electrically conductive ink material comprises at least one member selected from the group consisting of gold, aluminum, copper, tantalum, cobalt, ruthenium, titanium, tin, silver, solder, or an alloy thereof (Crocker, para. 133).
Regarding claim 4, modified Shim teaches the semiconductor device of claim 3, wherein the three- dimensionally printed flip chip interconnect has a cylindrical shape (Shim, para. 50).
Regarding claim 5, modified Shim teaches the semiconductor device of claim 1, wherein the metal surface comprises at least one metal selected from the group consisting of gold, aluminum, copper, tungsten, tantalum, silver, and palladium (Shim para. 49).
Regarding claim 6, modified Shim teaches the semiconductor device of claim 1, wherein the semiconductor device is an integrated circuit device (Crocker, para. 320).
Regarding claim 7, modified Shim teaches the semiconductor device of claim 1, wherein the three-dimensionally printed flip chip interconnect further includes a second electrically conductive ink material that is also compatible with the three-dimensional printing technology (Crocker, para. 350).
Regarding claim 8, modified Shim teaches the semiconductor device of claim 1, wherein a distal end of the three-dimensionally printed flip chip interconnect positioned on the metal surface of the semiconductor chip has a polygon shaped surface (Shim, para. shows it may be a quadrangle).
Regarding claim 23, modified Shim teaches the semiconductor device of claim 1, further comprising: at least one passivation layer (Shim, 40, Figs. 3(a), 3(b), para. 47) positioned at least partially on the at least one intermediary layer.
Regarding claim 24, modified Shim teaches the semiconductor device of claim 1, wherein the three-dimensionally printed flip chip interconnect is spaced a first distance from the at least one intermediary layer (Shim, Figs. 3(a), 3(b), the intermediary layer 20 is separated from the interconnect by the under bump metallization layer 50 and the electrode pad layer 30).
Regarding claim 25, modified Shim teaches the semiconductor device of claim 24, wherein the first distance is greater than or equal to 0.05 micrometers and less than or equal to 8 micrometers (Shim, Fig. 3a, shows that the thickness of the under bump metallization is approximately the same, or smaller than that of the passivation layer 40, the passivation layer 40 is 0.35 micrometers (Shim, para. 18) additionally the aluminum pad layer has a thickness of 0.35 micrometers (Shim, para. 18), therefore the distance between intermediary layer 20 and the interconnect 60 is between 0.35 and 0.70 micrometers).
Regarding claim 26, modified Shim teaches the semiconductor device of claim 24, wherein the three-dimensionally printed flip chip interconnect extends past the at least one intermediary layer such that the at least one intermediary layer is positioned a second distance from the chip pad of the printed circuit board when the semiconductor chip is flipped and connected to the printed circuit board to form the flip chip assembly (Shim, Figs. 3(a), 3(b), the interconnect, 60 extends past the intermediary layer 20 in the vertical direction, the second distance is the sum of the thickness of the under bump metallization layers and the interconnect).
Regarding claim 27, Shim teaches a flip chip assembly, comprising: a semiconductor device comprising: a semiconductor substrate (Shim, 10, Figs. 3(a), 3(b), para. 47);
a semiconductor chip positioned on the semiconductor substrate, the semiconductor chip including a metal surface opposite the semiconductor substrate (Shim, 50, Figs. 3(a), 3(b), para. 47); one or more intermediary layers positioned on the semiconductor substrate and at least partially on the metal surface (Shim, 20, Figs. 3(a) 3(b) para. 50); a flip chip interconnect (Shim, 60, Figs. 3(a) 3(b), para. 47), and a printed circuit board (Shim, paras. 4-5) comprising:
a chip pad (Shi, para. 5), wherein the flip chip interconnect is configured to be connected to the chip pad, and wherein the flip chip interconnect is configured to be positioned between the metal surface of the semiconductor chip and the chip pad when the semiconductor chip is flipped and connected to the printed circuit board to form the flip chip assembly (Shim, para. 5).
Shim does not teach wherein the flip chip interconnect is a three-dimensionally printed flip chip interconnect that includes an electrically conductive ink material that is compatible with a three-dimensional printing technology that prints by moving multi-directionally along a printing direction in a two-dimensional plane and in multiple layers to deposit the electrically conductive ink material on a predetermined portion of the metal surface of the semiconductor chip.
However, Sadie teaches, a three-dimensionally printed flip chip interconnect that includes an electrically conductive ink material (Abstract, 2.1 Printing Process, therefore the electrically conducive ink material is comparable with 3D a printing technology). Sadie teaches that three-dimensionally printed flip chip interconnects are suitable for use as vertical interconnects in semiconductor packaging applications, (Section 3. Conclusion).
Therefore it would have been obvious to one having ordinary skill in the art to combine the flip chip of Shim with the printed interconnect of Sadie to achieve pillars with properties comparable to bulk gold while saving costs (Sadie, abstract).
Neither Sadie nor Shim appear to disclose that the 3D printing technology prints by moving muti-directionally along a printing direction in a two-dimensional plane and in multiple layers to deposit the electrically conductive ink material on a metal surface of a semiconductor chip or the interconnect being connected to a chip pad on a PCB. The applicant is claiming the product of semiconductor device including a method (i.e. a process) of “moving muti-directionally along a printing direction in a two-dimensional plane” consequently, claim 1 is considered “product-by-process” claim. In spite of the fact that the product-by-process claim may recite only process limitations, it is the product and not the recited process that is covered by the claim. Further, patentability of a claim to a product does not rest merely on the difference in the method by which the product is made. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior art product was made by a different process. Furthermore, it is well established that a claimed apparatus cannot be distinguished over the prior art by a process limitation. Consequently, absent a showing of an unobvious difference between the claimed product and the prior art, the subject product-by-process claim limitation is not afforded patentable weight (see MPEP 2113).
However, Crocker teaches a conductive ink material (para. 323) that is compatible with
a three-dimensional printing technology that prints by moving muti-directionally along a printing direction in a two-dimensional plane (para. 124) and in multiple layers (para. 149) to deposit the electrically conductive ink material on a metal surface (para. 084) of a semiconductor chip. Therefore it would have been obvious to one of ordinary skill in the art, prior to the filing date of
the application, to use the moving multi-directional process of Crocker to form metal patterns
of various shapes.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Shim, Sadie and Crocker as applied to claim 1 above, and further in view of Gratson et. al. (US Pub. 20070228335), hereinafter referred to as Gratson.
Regarding claim 21, modified Shim teaches the semiconductor device of claim 1, but does not teach wherein the printing direction is defined by a geometry of a distal end of the three-dimensionally printed flip chip interconnect.
However, Gratson describes a microscale printing technique wherein the micro positioner moves to form a two-dimensional pattern on the substrate (Gratson, Para. 14).
Therefore it would have been obvious to one having ordinary skill in the art prior to the filing date of the invention to combine the 3D printed flip chip of modified Sadie with the techniques of Gratson such that the printing direction is defined by a geometry of a distal end of the three-dimensionally printed flip chip interconnect. A person of ordinary skill in the art would have been motivated to define the printing path based on the desired geometry of the distal end in order to accurately deposit the ink within the required spatial boundaries of the intended interconnect shape, ensuring proper alignment and bonding during the flip-chip packaging process.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Shim, Sadie and Crocker as applied to claim 8 above, and further in view of Gratson.
Regarding claim 22, modified Shim teaches the semiconductor device of claim 8, but does not teach wherein the printing direction is defined by the polygon shaped surface
However, Gratson describes a microscale printing technique wherein the micro positioner moves to form a two-dimensional pattern on the substrate(Gratson, Para. 14).
Therefore it would have been obvious to one having ordinary skill in the art prior to the filing date of the invention to further combine the 3D printed flip chip of modified Sadie with the
techniques of Gratson such that wherein the printing direction is defined by the polygon
shaped surface. A person of ordinary skill in the art would have been motivated to define the printing path based on the desired geometry of the distal end in order to accurately deposit the ink within the required spatial boundaries of the intended interconnect shape, ensuring proper alignment and bonding during the flip-chip packaging process.
Response to Arguments
Applicant’s arguments, see page 1 line 9 – page 3, line 20, filed 6/05/2026, with respect to the rejection of claim 1 under 35 U.S.C. § 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of rejection is made in view of Shim, Sadie, and Crocker.
The applicant’s argument was directed to the lack of a semiconductor substrate; a semiconductor chip positioned on the semiconductor substrate, the semiconductor chip including a metal surface opposite the semiconductor substrate; at least one intermediary layer positioned on the semiconductor substrate and at least partially on the metal surface in the references.
Shim teaches a chip which includes a semiconductor substrate, the semiconductor chip including a metal surface opposite the semiconductor substrate; and at least one intermediary layer positioned on the semiconductor substrate and at least partially on the metal surface in the references and a flip chip interconnect. Therefore it would have been obvious to one having ordinary skill in the art to combine the teachings of Sadie and Crocker with the chip of Shim to produce a three-dimensionally printed flip chip interconnect locate don a semiconductor chip.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lu et al. (US 8178429) teaches a method of nano-fabrication using dip pen nanolithography.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIERAN M CUNNINGHAM whose telephone number is (571)272-9654. The examiner can normally be reached Mon-Fri 8:30-5:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 5712703042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KIERAN M. CUNNINGHAM/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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